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OMAP STI/XTI console.
[qemu.git] / hw / omap2.c
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22 #include "hw.h"
23 #include "arm-misc.h"
24 #include "omap.h"
25 #include "sysemu.h"
26 #include "qemu-timer.h"
27 #include "qemu-char.h"
28 #include "flash.h"
29
30 /* GP timers */
31 struct omap_gp_timer_s {
32 qemu_irq irq;
33 qemu_irq wkup;
34 qemu_irq in;
35 qemu_irq out;
36 omap_clk clk;
37 target_phys_addr_t base;
38 QEMUTimer *timer;
39 QEMUTimer *match;
40 struct omap_target_agent_s *ta;
41
42 int in_val;
43 int out_val;
44 int64_t time;
45 int64_t rate;
46 int64_t ticks_per_sec;
47
48 int16_t config;
49 int status;
50 int it_ena;
51 int wu_ena;
52 int enable;
53 int inout;
54 int capt2;
55 int pt;
56 enum {
57 gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
58 } trigger;
59 enum {
60 gpt_capture_none, gpt_capture_rising,
61 gpt_capture_falling, gpt_capture_both
62 } capture;
63 int scpwm;
64 int ce;
65 int pre;
66 int ptv;
67 int ar;
68 int st;
69 int posted;
70 uint32_t val;
71 uint32_t load_val;
72 uint32_t capture_val[2];
73 uint32_t match_val;
74 int capt_num;
75
76 uint16_t writeh; /* LSB */
77 uint16_t readh; /* MSB */
78 };
79
80 #define GPT_TCAR_IT (1 << 2)
81 #define GPT_OVF_IT (1 << 1)
82 #define GPT_MAT_IT (1 << 0)
83
84 static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
85 {
86 if (timer->it_ena & it) {
87 if (!timer->status)
88 qemu_irq_raise(timer->irq);
89
90 timer->status |= it;
91 /* Or are the status bits set even when masked?
92 * i.e. is masking applied before or after the status register? */
93 }
94
95 if (timer->wu_ena & it)
96 qemu_irq_pulse(timer->wkup);
97 }
98
99 static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
100 {
101 if (!timer->inout && timer->out_val != level) {
102 timer->out_val = level;
103 qemu_set_irq(timer->out, level);
104 }
105 }
106
107 static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
108 {
109 uint64_t distance;
110
111 if (timer->st && timer->rate) {
112 distance = qemu_get_clock(vm_clock) - timer->time;
113 distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
114
115 if (distance >= 0xffffffff - timer->val)
116 return 0xffffffff;
117 else
118 return timer->val + distance;
119 } else
120 return timer->val;
121 }
122
123 static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
124 {
125 if (timer->st) {
126 timer->val = omap_gp_timer_read(timer);
127 timer->time = qemu_get_clock(vm_clock);
128 }
129 }
130
131 static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
132 {
133 int64_t expires, matches;
134
135 if (timer->st && timer->rate) {
136 expires = muldiv64(0x100000000ll - timer->val,
137 timer->ticks_per_sec, timer->rate);
138 qemu_mod_timer(timer->timer, timer->time + expires);
139
140 if (timer->ce && timer->match_val >= timer->val) {
141 matches = muldiv64(timer->match_val - timer->val,
142 timer->ticks_per_sec, timer->rate);
143 qemu_mod_timer(timer->match, timer->time + matches);
144 } else
145 qemu_del_timer(timer->match);
146 } else {
147 qemu_del_timer(timer->timer);
148 qemu_del_timer(timer->match);
149 omap_gp_timer_out(timer, timer->scpwm);
150 }
151 }
152
153 static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
154 {
155 if (timer->pt)
156 /* TODO in overflow-and-match mode if the first event to
157 * occurs is the match, don't toggle. */
158 omap_gp_timer_out(timer, !timer->out_val);
159 else
160 /* TODO inverted pulse on timer->out_val == 1? */
161 qemu_irq_pulse(timer->out);
162 }
163
164 static void omap_gp_timer_tick(void *opaque)
165 {
166 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
167
168 if (!timer->ar) {
169 timer->st = 0;
170 timer->val = 0;
171 } else {
172 timer->val = timer->load_val;
173 timer->time = qemu_get_clock(vm_clock);
174 }
175
176 if (timer->trigger == gpt_trigger_overflow ||
177 timer->trigger == gpt_trigger_both)
178 omap_gp_timer_trigger(timer);
179
180 omap_gp_timer_intr(timer, GPT_OVF_IT);
181 omap_gp_timer_update(timer);
182 }
183
184 static void omap_gp_timer_match(void *opaque)
185 {
186 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
187
188 if (timer->trigger == gpt_trigger_both)
189 omap_gp_timer_trigger(timer);
190
191 omap_gp_timer_intr(timer, GPT_MAT_IT);
192 }
193
194 static void omap_gp_timer_input(void *opaque, int line, int on)
195 {
196 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
197 int trigger;
198
199 switch (s->capture) {
200 default:
201 case gpt_capture_none:
202 trigger = 0;
203 break;
204 case gpt_capture_rising:
205 trigger = !s->in_val && on;
206 break;
207 case gpt_capture_falling:
208 trigger = s->in_val && !on;
209 break;
210 case gpt_capture_both:
211 trigger = (s->in_val == !on);
212 break;
213 }
214 s->in_val = on;
215
216 if (s->inout && trigger && s->capt_num < 2) {
217 s->capture_val[s->capt_num] = omap_gp_timer_read(s);
218
219 if (s->capt2 == s->capt_num ++)
220 omap_gp_timer_intr(s, GPT_TCAR_IT);
221 }
222 }
223
224 static void omap_gp_timer_clk_update(void *opaque, int line, int on)
225 {
226 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
227
228 omap_gp_timer_sync(timer);
229 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
230 omap_gp_timer_update(timer);
231 }
232
233 static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
234 {
235 omap_clk_adduser(timer->clk,
236 qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);
237 timer->rate = omap_clk_getrate(timer->clk);
238 }
239
240 static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
241 {
242 s->config = 0x000;
243 s->status = 0;
244 s->it_ena = 0;
245 s->wu_ena = 0;
246 s->inout = 0;
247 s->capt2 = 0;
248 s->capt_num = 0;
249 s->pt = 0;
250 s->trigger = gpt_trigger_none;
251 s->capture = gpt_capture_none;
252 s->scpwm = 0;
253 s->ce = 0;
254 s->pre = 0;
255 s->ptv = 0;
256 s->ar = 0;
257 s->st = 0;
258 s->posted = 1;
259 s->val = 0x00000000;
260 s->load_val = 0x00000000;
261 s->capture_val[0] = 0x00000000;
262 s->capture_val[1] = 0x00000000;
263 s->match_val = 0x00000000;
264 omap_gp_timer_update(s);
265 }
266
267 static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
268 {
269 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
270 int offset = addr - s->base;
271
272 switch (offset) {
273 case 0x00: /* TIDR */
274 return 0x21;
275
276 case 0x10: /* TIOCP_CFG */
277 return s->config;
278
279 case 0x14: /* TISTAT */
280 /* ??? When's this bit reset? */
281 return 1; /* RESETDONE */
282
283 case 0x18: /* TISR */
284 return s->status;
285
286 case 0x1c: /* TIER */
287 return s->it_ena;
288
289 case 0x20: /* TWER */
290 return s->wu_ena;
291
292 case 0x24: /* TCLR */
293 return (s->inout << 14) |
294 (s->capt2 << 13) |
295 (s->pt << 12) |
296 (s->trigger << 10) |
297 (s->capture << 8) |
298 (s->scpwm << 7) |
299 (s->ce << 6) |
300 (s->pre << 5) |
301 (s->ptv << 2) |
302 (s->ar << 1) |
303 (s->st << 0);
304
305 case 0x28: /* TCRR */
306 return omap_gp_timer_read(s);
307
308 case 0x2c: /* TLDR */
309 return s->load_val;
310
311 case 0x30: /* TTGR */
312 return 0xffffffff;
313
314 case 0x34: /* TWPS */
315 return 0x00000000; /* No posted writes pending. */
316
317 case 0x38: /* TMAR */
318 return s->match_val;
319
320 case 0x3c: /* TCAR1 */
321 return s->capture_val[0];
322
323 case 0x40: /* TSICR */
324 return s->posted << 2;
325
326 case 0x44: /* TCAR2 */
327 return s->capture_val[1];
328 }
329
330 OMAP_BAD_REG(addr);
331 return 0;
332 }
333
334 static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
335 {
336 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
337 uint32_t ret;
338
339 if (addr & 2)
340 return s->readh;
341 else {
342 ret = omap_gp_timer_readw(opaque, addr);
343 s->readh = ret >> 16;
344 return ret & 0xffff;
345 }
346 }
347
348 static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
349 omap_badwidth_read32,
350 omap_gp_timer_readh,
351 omap_gp_timer_readw,
352 };
353
354 static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
355 uint32_t value)
356 {
357 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
358 int offset = addr - s->base;
359
360 switch (offset) {
361 case 0x00: /* TIDR */
362 case 0x14: /* TISTAT */
363 case 0x34: /* TWPS */
364 case 0x3c: /* TCAR1 */
365 case 0x44: /* TCAR2 */
366 OMAP_RO_REG(addr);
367 break;
368
369 case 0x10: /* TIOCP_CFG */
370 s->config = value & 0x33d;
371 if (((value >> 3) & 3) == 3) /* IDLEMODE */
372 fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
373 __FUNCTION__);
374 if (value & 2) /* SOFTRESET */
375 omap_gp_timer_reset(s);
376 break;
377
378 case 0x18: /* TISR */
379 if (value & GPT_TCAR_IT)
380 s->capt_num = 0;
381 if (s->status && !(s->status &= ~value))
382 qemu_irq_lower(s->irq);
383 break;
384
385 case 0x1c: /* TIER */
386 s->it_ena = value & 7;
387 break;
388
389 case 0x20: /* TWER */
390 s->wu_ena = value & 7;
391 break;
392
393 case 0x24: /* TCLR */
394 omap_gp_timer_sync(s);
395 s->inout = (value >> 14) & 1;
396 s->capt2 = (value >> 13) & 1;
397 s->pt = (value >> 12) & 1;
398 s->trigger = (value >> 10) & 3;
399 if (s->capture == gpt_capture_none &&
400 ((value >> 8) & 3) != gpt_capture_none)
401 s->capt_num = 0;
402 s->capture = (value >> 8) & 3;
403 s->scpwm = (value >> 7) & 1;
404 s->ce = (value >> 6) & 1;
405 s->pre = (value >> 5) & 1;
406 s->ptv = (value >> 2) & 7;
407 s->ar = (value >> 1) & 1;
408 s->st = (value >> 0) & 1;
409 if (s->inout && s->trigger != gpt_trigger_none)
410 fprintf(stderr, "%s: GP timer pin must be an output "
411 "for this trigger mode\n", __FUNCTION__);
412 if (!s->inout && s->capture != gpt_capture_none)
413 fprintf(stderr, "%s: GP timer pin must be an input "
414 "for this capture mode\n", __FUNCTION__);
415 if (s->trigger == gpt_trigger_none)
416 omap_gp_timer_out(s, s->scpwm);
417 /* TODO: make sure this doesn't overflow 32-bits */
418 s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0);
419 omap_gp_timer_update(s);
420 break;
421
422 case 0x28: /* TCRR */
423 s->time = qemu_get_clock(vm_clock);
424 s->val = value;
425 omap_gp_timer_update(s);
426 break;
427
428 case 0x2c: /* TLDR */
429 s->load_val = value;
430 break;
431
432 case 0x30: /* TTGR */
433 s->time = qemu_get_clock(vm_clock);
434 s->val = s->load_val;
435 omap_gp_timer_update(s);
436 break;
437
438 case 0x38: /* TMAR */
439 omap_gp_timer_sync(s);
440 s->match_val = value;
441 omap_gp_timer_update(s);
442 break;
443
444 case 0x40: /* TSICR */
445 s->posted = (value >> 2) & 1;
446 if (value & 2) /* How much exactly are we supposed to reset? */
447 omap_gp_timer_reset(s);
448 break;
449
450 default:
451 OMAP_BAD_REG(addr);
452 }
453 }
454
455 static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
456 uint32_t value)
457 {
458 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
459
460 if (addr & 2)
461 return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
462 else
463 s->writeh = (uint16_t) value;
464 }
465
466 static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
467 omap_badwidth_write32,
468 omap_gp_timer_writeh,
469 omap_gp_timer_write,
470 };
471
472 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
473 qemu_irq irq, omap_clk fclk, omap_clk iclk)
474 {
475 int iomemtype;
476 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
477 qemu_mallocz(sizeof(struct omap_gp_timer_s));
478
479 s->ta = ta;
480 s->irq = irq;
481 s->clk = fclk;
482 s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);
483 s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);
484 s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
485 omap_gp_timer_reset(s);
486 omap_gp_timer_clk_setup(s);
487
488 iomemtype = cpu_register_io_memory(0, omap_gp_timer_readfn,
489 omap_gp_timer_writefn, s);
490 s->base = omap_l4_attach(ta, 0, iomemtype);
491
492 return s;
493 }
494
495 /* 32-kHz Sync Timer of the OMAP2 */
496 static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
497 return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec);
498 }
499
500 static void omap_synctimer_reset(struct omap_synctimer_s *s)
501 {
502 s->val = omap_synctimer_read(s);
503 }
504
505 static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
506 {
507 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
508 int offset = addr - s->base;
509
510 switch (offset) {
511 case 0x00: /* 32KSYNCNT_REV */
512 return 0x21;
513
514 case 0x10: /* CR */
515 return omap_synctimer_read(s) - s->val;
516 }
517
518 OMAP_BAD_REG(addr);
519 return 0;
520 }
521
522 static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
523 {
524 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
525 uint32_t ret;
526
527 if (addr & 2)
528 return s->readh;
529 else {
530 ret = omap_synctimer_readw(opaque, addr);
531 s->readh = ret >> 16;
532 return ret & 0xffff;
533 }
534 }
535
536 static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
537 omap_badwidth_read32,
538 omap_synctimer_readh,
539 omap_synctimer_readw,
540 };
541
542 static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
543 uint32_t value)
544 {
545 OMAP_BAD_REG(addr);
546 }
547
548 static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
549 omap_badwidth_write32,
550 omap_synctimer_write,
551 omap_synctimer_write,
552 };
553
554 void omap_synctimer_init(struct omap_target_agent_s *ta,
555 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
556 {
557 struct omap_synctimer_s *s = &mpu->synctimer;
558
559 omap_synctimer_reset(s);
560 s->base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
561 omap_synctimer_readfn, omap_synctimer_writefn, s));
562 }
563
564 /* General-Purpose Interface of OMAP2 */
565 struct omap2_gpio_s {
566 target_phys_addr_t base;
567 qemu_irq irq[2];
568 qemu_irq wkup;
569 qemu_irq *in;
570 qemu_irq handler[32];
571
572 uint8_t config[2];
573 uint32_t inputs;
574 uint32_t outputs;
575 uint32_t dir;
576 uint32_t level[2];
577 uint32_t edge[2];
578 uint32_t mask[2];
579 uint32_t wumask;
580 uint32_t ints[2];
581 uint32_t debounce;
582 uint8_t delay;
583 };
584
585 static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,
586 int line)
587 {
588 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
589 }
590
591 static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)
592 {
593 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
594 return;
595 if (!(s->config[0] & (3 << 3))) /* Force Idle */
596 return;
597 if (!(s->wumask & (1 << line)))
598 return;
599
600 qemu_irq_raise(s->wkup);
601 }
602
603 static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,
604 uint32_t diff)
605 {
606 int ln;
607
608 s->outputs ^= diff;
609 diff &= ~s->dir;
610 while ((ln = ffs(diff))) {
611 ln --;
612 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
613 diff &= ~(1 << ln);
614 }
615 }
616
617 static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)
618 {
619 s->ints[line] |= s->dir &
620 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
621 omap_gpio_module_int_update(s, line);
622 }
623
624 static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
625 {
626 s->ints[0] |= 1 << line;
627 omap_gpio_module_int_update(s, 0);
628 s->ints[1] |= 1 << line;
629 omap_gpio_module_int_update(s, 1);
630 omap_gpio_module_wake(s, line);
631 }
632
633 static void omap_gpio_module_set(void *opaque, int line, int level)
634 {
635 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
636
637 if (level) {
638 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
639 omap_gpio_module_int(s, line);
640 s->inputs |= 1 << line;
641 } else {
642 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
643 omap_gpio_module_int(s, line);
644 s->inputs &= ~(1 << line);
645 }
646 }
647
648 static void omap_gpio_module_reset(struct omap2_gpio_s *s)
649 {
650 s->config[0] = 0;
651 s->config[1] = 2;
652 s->ints[0] = 0;
653 s->ints[1] = 0;
654 s->mask[0] = 0;
655 s->mask[1] = 0;
656 s->wumask = 0;
657 s->dir = ~0;
658 s->level[0] = 0;
659 s->level[1] = 0;
660 s->edge[0] = 0;
661 s->edge[1] = 0;
662 s->debounce = 0;
663 s->delay = 0;
664 }
665
666 static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
667 {
668 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
669 int offset = addr - s->base;
670
671 switch (offset) {
672 case 0x00: /* GPIO_REVISION */
673 return 0x18;
674
675 case 0x10: /* GPIO_SYSCONFIG */
676 return s->config[0];
677
678 case 0x14: /* GPIO_SYSSTATUS */
679 return 0x01;
680
681 case 0x18: /* GPIO_IRQSTATUS1 */
682 return s->ints[0];
683
684 case 0x1c: /* GPIO_IRQENABLE1 */
685 case 0x60: /* GPIO_CLEARIRQENABLE1 */
686 case 0x64: /* GPIO_SETIRQENABLE1 */
687 return s->mask[0];
688
689 case 0x20: /* GPIO_WAKEUPENABLE */
690 case 0x80: /* GPIO_CLEARWKUENA */
691 case 0x84: /* GPIO_SETWKUENA */
692 return s->wumask;
693
694 case 0x28: /* GPIO_IRQSTATUS2 */
695 return s->ints[1];
696
697 case 0x2c: /* GPIO_IRQENABLE2 */
698 case 0x70: /* GPIO_CLEARIRQENABLE2 */
699 case 0x74: /* GPIO_SETIREQNEABLE2 */
700 return s->mask[1];
701
702 case 0x30: /* GPIO_CTRL */
703 return s->config[1];
704
705 case 0x34: /* GPIO_OE */
706 return s->dir;
707
708 case 0x38: /* GPIO_DATAIN */
709 return s->inputs;
710
711 case 0x3c: /* GPIO_DATAOUT */
712 case 0x90: /* GPIO_CLEARDATAOUT */
713 case 0x94: /* GPIO_SETDATAOUT */
714 return s->outputs;
715
716 case 0x40: /* GPIO_LEVELDETECT0 */
717 return s->level[0];
718
719 case 0x44: /* GPIO_LEVELDETECT1 */
720 return s->level[1];
721
722 case 0x48: /* GPIO_RISINGDETECT */
723 return s->edge[0];
724
725 case 0x4c: /* GPIO_FALLINGDETECT */
726 return s->edge[1];
727
728 case 0x50: /* GPIO_DEBOUNCENABLE */
729 return s->debounce;
730
731 case 0x54: /* GPIO_DEBOUNCINGTIME */
732 return s->delay;
733 }
734
735 OMAP_BAD_REG(addr);
736 return 0;
737 }
738
739 static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
740 uint32_t value)
741 {
742 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
743 int offset = addr - s->base;
744 uint32_t diff;
745 int ln;
746
747 switch (offset) {
748 case 0x00: /* GPIO_REVISION */
749 case 0x14: /* GPIO_SYSSTATUS */
750 case 0x38: /* GPIO_DATAIN */
751 OMAP_RO_REG(addr);
752 break;
753
754 case 0x10: /* GPIO_SYSCONFIG */
755 if (((value >> 3) & 3) == 3)
756 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
757 if (value & 2)
758 omap_gpio_module_reset(s);
759 s->config[0] = value & 0x1d;
760 break;
761
762 case 0x18: /* GPIO_IRQSTATUS1 */
763 if (s->ints[0] & value) {
764 s->ints[0] &= ~value;
765 omap_gpio_module_level_update(s, 0);
766 }
767 break;
768
769 case 0x1c: /* GPIO_IRQENABLE1 */
770 s->mask[0] = value;
771 omap_gpio_module_int_update(s, 0);
772 break;
773
774 case 0x20: /* GPIO_WAKEUPENABLE */
775 s->wumask = value;
776 break;
777
778 case 0x28: /* GPIO_IRQSTATUS2 */
779 if (s->ints[1] & value) {
780 s->ints[1] &= ~value;
781 omap_gpio_module_level_update(s, 1);
782 }
783 break;
784
785 case 0x2c: /* GPIO_IRQENABLE2 */
786 s->mask[1] = value;
787 omap_gpio_module_int_update(s, 1);
788 break;
789
790 case 0x30: /* GPIO_CTRL */
791 s->config[1] = value & 7;
792 break;
793
794 case 0x34: /* GPIO_OE */
795 diff = s->outputs & (s->dir ^ value);
796 s->dir = value;
797
798 value = s->outputs & ~s->dir;
799 while ((ln = ffs(diff))) {
800 diff &= ~(1 <<-- ln);
801 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
802 }
803
804 omap_gpio_module_level_update(s, 0);
805 omap_gpio_module_level_update(s, 1);
806 break;
807
808 case 0x3c: /* GPIO_DATAOUT */
809 omap_gpio_module_out_update(s, s->outputs ^ value);
810 break;
811
812 case 0x40: /* GPIO_LEVELDETECT0 */
813 s->level[0] = value;
814 omap_gpio_module_level_update(s, 0);
815 omap_gpio_module_level_update(s, 1);
816 break;
817
818 case 0x44: /* GPIO_LEVELDETECT1 */
819 s->level[1] = value;
820 omap_gpio_module_level_update(s, 0);
821 omap_gpio_module_level_update(s, 1);
822 break;
823
824 case 0x48: /* GPIO_RISINGDETECT */
825 s->edge[0] = value;
826 break;
827
828 case 0x4c: /* GPIO_FALLINGDETECT */
829 s->edge[1] = value;
830 break;
831
832 case 0x50: /* GPIO_DEBOUNCENABLE */
833 s->debounce = value;
834 break;
835
836 case 0x54: /* GPIO_DEBOUNCINGTIME */
837 s->delay = value;
838 break;
839
840 case 0x60: /* GPIO_CLEARIRQENABLE1 */
841 s->mask[0] &= ~value;
842 omap_gpio_module_int_update(s, 0);
843 break;
844
845 case 0x64: /* GPIO_SETIRQENABLE1 */
846 s->mask[0] |= value;
847 omap_gpio_module_int_update(s, 0);
848 break;
849
850 case 0x70: /* GPIO_CLEARIRQENABLE2 */
851 s->mask[1] &= ~value;
852 omap_gpio_module_int_update(s, 1);
853 break;
854
855 case 0x74: /* GPIO_SETIREQNEABLE2 */
856 s->mask[1] |= value;
857 omap_gpio_module_int_update(s, 1);
858 break;
859
860 case 0x80: /* GPIO_CLEARWKUENA */
861 s->wumask &= ~value;
862 break;
863
864 case 0x84: /* GPIO_SETWKUENA */
865 s->wumask |= value;
866 break;
867
868 case 0x90: /* GPIO_CLEARDATAOUT */
869 omap_gpio_module_out_update(s, s->outputs & value);
870 break;
871
872 case 0x94: /* GPIO_SETDATAOUT */
873 omap_gpio_module_out_update(s, ~s->outputs & value);
874 break;
875
876 default:
877 OMAP_BAD_REG(addr);
878 return;
879 }
880 }
881
882 static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
883 {
884 return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
885 }
886
887 static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
888 uint32_t value)
889 {
890 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
891 int offset = addr - s->base;
892 uint32_t cur = 0;
893 uint32_t mask = 0xffff;
894
895 switch (offset & ~3) {
896 case 0x00: /* GPIO_REVISION */
897 case 0x14: /* GPIO_SYSSTATUS */
898 case 0x38: /* GPIO_DATAIN */
899 OMAP_RO_REG(addr);
900 break;
901
902 case 0x10: /* GPIO_SYSCONFIG */
903 case 0x1c: /* GPIO_IRQENABLE1 */
904 case 0x20: /* GPIO_WAKEUPENABLE */
905 case 0x2c: /* GPIO_IRQENABLE2 */
906 case 0x30: /* GPIO_CTRL */
907 case 0x34: /* GPIO_OE */
908 case 0x3c: /* GPIO_DATAOUT */
909 case 0x40: /* GPIO_LEVELDETECT0 */
910 case 0x44: /* GPIO_LEVELDETECT1 */
911 case 0x48: /* GPIO_RISINGDETECT */
912 case 0x4c: /* GPIO_FALLINGDETECT */
913 case 0x50: /* GPIO_DEBOUNCENABLE */
914 case 0x54: /* GPIO_DEBOUNCINGTIME */
915 cur = omap_gpio_module_read(opaque, addr & ~3) &
916 ~(mask << ((addr & 3) << 3));
917
918 /* Fall through. */
919 case 0x18: /* GPIO_IRQSTATUS1 */
920 case 0x28: /* GPIO_IRQSTATUS2 */
921 case 0x60: /* GPIO_CLEARIRQENABLE1 */
922 case 0x64: /* GPIO_SETIRQENABLE1 */
923 case 0x70: /* GPIO_CLEARIRQENABLE2 */
924 case 0x74: /* GPIO_SETIREQNEABLE2 */
925 case 0x80: /* GPIO_CLEARWKUENA */
926 case 0x84: /* GPIO_SETWKUENA */
927 case 0x90: /* GPIO_CLEARDATAOUT */
928 case 0x94: /* GPIO_SETDATAOUT */
929 value <<= (addr & 3) << 3;
930 omap_gpio_module_write(opaque, addr, cur | value);
931 break;
932
933 default:
934 OMAP_BAD_REG(addr);
935 return;
936 }
937 }
938
939 static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
940 omap_gpio_module_readp,
941 omap_gpio_module_readp,
942 omap_gpio_module_read,
943 };
944
945 static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
946 omap_gpio_module_writep,
947 omap_gpio_module_writep,
948 omap_gpio_module_write,
949 };
950
951 static void omap_gpio_module_init(struct omap2_gpio_s *s,
952 struct omap_target_agent_s *ta, int region,
953 qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
954 omap_clk fclk, omap_clk iclk)
955 {
956 int iomemtype;
957
958 s->irq[0] = mpu;
959 s->irq[1] = dsp;
960 s->wkup = wkup;
961 s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
962
963 iomemtype = cpu_register_io_memory(0, omap_gpio_module_readfn,
964 omap_gpio_module_writefn, s);
965 s->base = omap_l4_attach(ta, region, iomemtype);
966 }
967
968 struct omap_gpif_s {
969 struct omap2_gpio_s module[5];
970 int modules;
971
972 target_phys_addr_t topbase;
973 int autoidle;
974 int gpo;
975 };
976
977 static void omap_gpif_reset(struct omap_gpif_s *s)
978 {
979 int i;
980
981 for (i = 0; i < s->modules; i ++)
982 omap_gpio_module_reset(s->module + i);
983
984 s->autoidle = 0;
985 s->gpo = 0;
986 }
987
988 static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
989 {
990 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
991 int offset = addr - s->topbase;
992
993 switch (offset) {
994 case 0x00: /* IPGENERICOCPSPL_REVISION */
995 return 0x18;
996
997 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
998 return s->autoidle;
999
1000 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1001 return 0x01;
1002
1003 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1004 return 0x00;
1005
1006 case 0x40: /* IPGENERICOCPSPL_GPO */
1007 return s->gpo;
1008
1009 case 0x50: /* IPGENERICOCPSPL_GPI */
1010 return 0x00;
1011 }
1012
1013 OMAP_BAD_REG(addr);
1014 return 0;
1015 }
1016
1017 static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
1018 uint32_t value)
1019 {
1020 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
1021 int offset = addr - s->topbase;
1022
1023 switch (offset) {
1024 case 0x00: /* IPGENERICOCPSPL_REVISION */
1025 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1026 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1027 case 0x50: /* IPGENERICOCPSPL_GPI */
1028 OMAP_RO_REG(addr);
1029 break;
1030
1031 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
1032 if (value & (1 << 1)) /* SOFTRESET */
1033 omap_gpif_reset(s);
1034 s->autoidle = value & 1;
1035 break;
1036
1037 case 0x40: /* IPGENERICOCPSPL_GPO */
1038 s->gpo = value & 1;
1039 break;
1040
1041 default:
1042 OMAP_BAD_REG(addr);
1043 return;
1044 }
1045 }
1046
1047 static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
1048 omap_gpif_top_read,
1049 omap_gpif_top_read,
1050 omap_gpif_top_read,
1051 };
1052
1053 static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
1054 omap_gpif_top_write,
1055 omap_gpif_top_write,
1056 omap_gpif_top_write,
1057 };
1058
1059 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1060 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
1061 {
1062 int iomemtype, i;
1063 struct omap_gpif_s *s = (struct omap_gpif_s *)
1064 qemu_mallocz(sizeof(struct omap_gpif_s));
1065 int region[4] = { 0, 2, 4, 5 };
1066
1067 s->modules = modules;
1068 for (i = 0; i < modules; i ++)
1069 omap_gpio_module_init(s->module + i, ta, region[i],
1070 irq[i], 0, 0, fclk[i], iclk);
1071
1072 omap_gpif_reset(s);
1073
1074 iomemtype = cpu_register_io_memory(0, omap_gpif_top_readfn,
1075 omap_gpif_top_writefn, s);
1076 s->topbase = omap_l4_attach(ta, 1, iomemtype);
1077
1078 return s;
1079 }
1080
1081 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1082 {
1083 if (start >= s->modules * 32 || start < 0)
1084 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
1085 __FUNCTION__, start);
1086 return s->module[start >> 5].in + (start & 31);
1087 }
1088
1089 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1090 {
1091 if (line >= s->modules * 32 || line < 0)
1092 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
1093 s->module[line >> 5].handler[line & 31] = handler;
1094 }
1095
1096 /* Multichannel SPI */
1097 struct omap_mcspi_s {
1098 target_phys_addr_t base;
1099 qemu_irq irq;
1100 int chnum;
1101
1102 uint32_t sysconfig;
1103 uint32_t systest;
1104 uint32_t irqst;
1105 uint32_t irqen;
1106 uint32_t wken;
1107 uint32_t control;
1108
1109 struct omap_mcspi_ch_s {
1110 qemu_irq txdrq;
1111 qemu_irq rxdrq;
1112 uint32_t (*txrx)(void *opaque, uint32_t);
1113 void *opaque;
1114
1115 uint32_t tx;
1116 uint32_t rx;
1117
1118 uint32_t config;
1119 uint32_t status;
1120 uint32_t control;
1121 } ch[4];
1122 };
1123
1124 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
1125 {
1126 qemu_set_irq(s->irq, s->irqst & s->irqen);
1127 }
1128
1129 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
1130 {
1131 qemu_set_irq(ch->txdrq,
1132 (ch->control & 1) && /* EN */
1133 (ch->config & (1 << 14)) && /* DMAW */
1134 (ch->status & (1 << 1)) && /* TXS */
1135 ((ch->config >> 12) & 3) != 1); /* TRM */
1136 qemu_set_irq(ch->rxdrq,
1137 (ch->control & 1) && /* EN */
1138 (ch->config & (1 << 15)) && /* DMAW */
1139 (ch->status & (1 << 0)) && /* RXS */
1140 ((ch->config >> 12) & 3) != 2); /* TRM */
1141 }
1142
1143 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1144 {
1145 struct omap_mcspi_ch_s *ch = s->ch + chnum;
1146
1147 if (!(ch->control & 1)) /* EN */
1148 return;
1149 if ((ch->status & (1 << 0)) && /* RXS */
1150 ((ch->config >> 12) & 3) != 2 && /* TRM */
1151 !(ch->config & (1 << 19))) /* TURBO */
1152 goto intr_update;
1153 if ((ch->status & (1 << 1)) && /* TXS */
1154 ((ch->config >> 12) & 3) != 1) /* TRM */
1155 goto intr_update;
1156
1157 if (!(s->control & 1) || /* SINGLE */
1158 (ch->config & (1 << 20))) { /* FORCE */
1159 if (ch->txrx)
1160 ch->rx = ch->txrx(ch->opaque, ch->tx);
1161 }
1162
1163 ch->tx = 0;
1164 ch->status |= 1 << 2; /* EOT */
1165 ch->status |= 1 << 1; /* TXS */
1166 if (((ch->config >> 12) & 3) != 2) /* TRM */
1167 ch->status |= 1 << 0; /* RXS */
1168
1169 intr_update:
1170 if ((ch->status & (1 << 0)) && /* RXS */
1171 ((ch->config >> 12) & 3) != 2 && /* TRM */
1172 !(ch->config & (1 << 19))) /* TURBO */
1173 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
1174 if ((ch->status & (1 << 1)) && /* TXS */
1175 ((ch->config >> 12) & 3) != 1) /* TRM */
1176 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
1177 omap_mcspi_interrupt_update(s);
1178 omap_mcspi_dmarequest_update(ch);
1179 }
1180
1181 static void omap_mcspi_reset(struct omap_mcspi_s *s)
1182 {
1183 int ch;
1184
1185 s->sysconfig = 0;
1186 s->systest = 0;
1187 s->irqst = 0;
1188 s->irqen = 0;
1189 s->wken = 0;
1190 s->control = 4;
1191
1192 for (ch = 0; ch < 4; ch ++) {
1193 s->ch[ch].config = 0x060000;
1194 s->ch[ch].status = 2; /* TXS */
1195 s->ch[ch].control = 0;
1196
1197 omap_mcspi_dmarequest_update(s->ch + ch);
1198 }
1199
1200 omap_mcspi_interrupt_update(s);
1201 }
1202
1203 static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
1204 {
1205 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1206 int offset = addr - s->base;
1207 int ch = 0;
1208 uint32_t ret;
1209
1210 switch (offset) {
1211 case 0x00: /* MCSPI_REVISION */
1212 return 0x91;
1213
1214 case 0x10: /* MCSPI_SYSCONFIG */
1215 return s->sysconfig;
1216
1217 case 0x14: /* MCSPI_SYSSTATUS */
1218 return 1; /* RESETDONE */
1219
1220 case 0x18: /* MCSPI_IRQSTATUS */
1221 return s->irqst;
1222
1223 case 0x1c: /* MCSPI_IRQENABLE */
1224 return s->irqen;
1225
1226 case 0x20: /* MCSPI_WAKEUPENABLE */
1227 return s->wken;
1228
1229 case 0x24: /* MCSPI_SYST */
1230 return s->systest;
1231
1232 case 0x28: /* MCSPI_MODULCTRL */
1233 return s->control;
1234
1235 case 0x68: ch ++;
1236 case 0x54: ch ++;
1237 case 0x40: ch ++;
1238 case 0x2c: /* MCSPI_CHCONF */
1239 return s->ch[ch].config;
1240
1241 case 0x6c: ch ++;
1242 case 0x58: ch ++;
1243 case 0x44: ch ++;
1244 case 0x30: /* MCSPI_CHSTAT */
1245 return s->ch[ch].status;
1246
1247 case 0x70: ch ++;
1248 case 0x5c: ch ++;
1249 case 0x48: ch ++;
1250 case 0x34: /* MCSPI_CHCTRL */
1251 return s->ch[ch].control;
1252
1253 case 0x74: ch ++;
1254 case 0x60: ch ++;
1255 case 0x4c: ch ++;
1256 case 0x38: /* MCSPI_TX */
1257 return s->ch[ch].tx;
1258
1259 case 0x78: ch ++;
1260 case 0x64: ch ++;
1261 case 0x50: ch ++;
1262 case 0x3c: /* MCSPI_RX */
1263 s->ch[ch].status &= ~(1 << 0); /* RXS */
1264 ret = s->ch[ch].rx;
1265 omap_mcspi_transfer_run(s, ch);
1266 return ret;
1267 }
1268
1269 OMAP_BAD_REG(addr);
1270 return 0;
1271 }
1272
1273 static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
1274 uint32_t value)
1275 {
1276 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1277 int offset = addr - s->base;
1278 int ch = 0;
1279
1280 switch (offset) {
1281 case 0x00: /* MCSPI_REVISION */
1282 case 0x14: /* MCSPI_SYSSTATUS */
1283 case 0x30: /* MCSPI_CHSTAT0 */
1284 case 0x3c: /* MCSPI_RX0 */
1285 case 0x44: /* MCSPI_CHSTAT1 */
1286 case 0x50: /* MCSPI_RX1 */
1287 case 0x58: /* MCSPI_CHSTAT2 */
1288 case 0x64: /* MCSPI_RX2 */
1289 case 0x6c: /* MCSPI_CHSTAT3 */
1290 case 0x78: /* MCSPI_RX3 */
1291 OMAP_RO_REG(addr);
1292 return;
1293
1294 case 0x10: /* MCSPI_SYSCONFIG */
1295 if (value & (1 << 1)) /* SOFTRESET */
1296 omap_mcspi_reset(s);
1297 s->sysconfig = value & 0x31d;
1298 break;
1299
1300 case 0x18: /* MCSPI_IRQSTATUS */
1301 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
1302 s->irqst &= ~value;
1303 omap_mcspi_interrupt_update(s);
1304 }
1305 break;
1306
1307 case 0x1c: /* MCSPI_IRQENABLE */
1308 s->irqen = value & 0x1777f;
1309 omap_mcspi_interrupt_update(s);
1310 break;
1311
1312 case 0x20: /* MCSPI_WAKEUPENABLE */
1313 s->wken = value & 1;
1314 break;
1315
1316 case 0x24: /* MCSPI_SYST */
1317 if (s->control & (1 << 3)) /* SYSTEM_TEST */
1318 if (value & (1 << 11)) { /* SSB */
1319 s->irqst |= 0x1777f;
1320 omap_mcspi_interrupt_update(s);
1321 }
1322 s->systest = value & 0xfff;
1323 break;
1324
1325 case 0x28: /* MCSPI_MODULCTRL */
1326 if (value & (1 << 3)) /* SYSTEM_TEST */
1327 if (s->systest & (1 << 11)) { /* SSB */
1328 s->irqst |= 0x1777f;
1329 omap_mcspi_interrupt_update(s);
1330 }
1331 s->control = value & 0xf;
1332 break;
1333
1334 case 0x68: ch ++;
1335 case 0x54: ch ++;
1336 case 0x40: ch ++;
1337 case 0x2c: /* MCSPI_CHCONF */
1338 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
1339 omap_mcspi_dmarequest_update(s->ch + ch);
1340 if (((value >> 12) & 3) == 3) /* TRM */
1341 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
1342 if (((value >> 7) & 0x1f) < 3) /* WL */
1343 fprintf(stderr, "%s: invalid WL value (%i)\n",
1344 __FUNCTION__, (value >> 7) & 0x1f);
1345 s->ch[ch].config = value & 0x7fffff;
1346 break;
1347
1348 case 0x70: ch ++;
1349 case 0x5c: ch ++;
1350 case 0x48: ch ++;
1351 case 0x34: /* MCSPI_CHCTRL */
1352 if (value & ~s->ch[ch].control & 1) { /* EN */
1353 s->ch[ch].control |= 1;
1354 omap_mcspi_transfer_run(s, ch);
1355 } else
1356 s->ch[ch].control = value & 1;
1357 break;
1358
1359 case 0x74: ch ++;
1360 case 0x60: ch ++;
1361 case 0x4c: ch ++;
1362 case 0x38: /* MCSPI_TX */
1363 s->ch[ch].tx = value;
1364 s->ch[ch].status &= ~(1 << 1); /* TXS */
1365 omap_mcspi_transfer_run(s, ch);
1366 break;
1367
1368 default:
1369 OMAP_BAD_REG(addr);
1370 return;
1371 }
1372 }
1373
1374 static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
1375 omap_badwidth_read32,
1376 omap_badwidth_read32,
1377 omap_mcspi_read,
1378 };
1379
1380 static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
1381 omap_badwidth_write32,
1382 omap_badwidth_write32,
1383 omap_mcspi_write,
1384 };
1385
1386 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1387 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1388 {
1389 int iomemtype;
1390 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
1391 qemu_mallocz(sizeof(struct omap_mcspi_s));
1392 struct omap_mcspi_ch_s *ch = s->ch;
1393
1394 s->irq = irq;
1395 s->chnum = chnum;
1396 while (chnum --) {
1397 ch->txdrq = *drq ++;
1398 ch->rxdrq = *drq ++;
1399 ch ++;
1400 }
1401 omap_mcspi_reset(s);
1402
1403 iomemtype = cpu_register_io_memory(0, omap_mcspi_readfn,
1404 omap_mcspi_writefn, s);
1405 s->base = omap_l4_attach(ta, 0, iomemtype);
1406
1407 return s;
1408 }
1409
1410 void omap_mcspi_attach(struct omap_mcspi_s *s,
1411 uint32_t (*txrx)(void *opaque, uint32_t), void *opaque,
1412 int chipselect)
1413 {
1414 if (chipselect < 0 || chipselect >= s->chnum)
1415 cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
1416 __FUNCTION__, chipselect);
1417
1418 s->ch[chipselect].txrx = txrx;
1419 s->ch[chipselect].opaque = opaque;
1420 }
1421
1422 /* STI/XTI (emulation interface) console - reverse engineered only */
1423 struct omap_sti_s {
1424 target_phys_addr_t base;
1425 target_phys_addr_t channel_base;
1426 qemu_irq irq;
1427 CharDriverState *chr;
1428
1429 uint32_t sysconfig;
1430 uint32_t systest;
1431 uint32_t irqst;
1432 uint32_t irqen;
1433 uint32_t clkcontrol;
1434 uint32_t serial_config;
1435 };
1436
1437 #define STI_TRACE_CONSOLE_CHANNEL 239
1438 #define STI_TRACE_CONTROL_CHANNEL 253
1439
1440 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
1441 {
1442 qemu_set_irq(s->irq, s->irqst & s->irqen);
1443 }
1444
1445 static void omap_sti_reset(struct omap_sti_s *s)
1446 {
1447 s->sysconfig = 0;
1448 s->irqst = 0;
1449 s->irqen = 0;
1450 s->clkcontrol = 0;
1451 s->serial_config = 0;
1452
1453 omap_sti_interrupt_update(s);
1454 }
1455
1456 static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
1457 {
1458 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1459 int offset = addr - s->base;
1460
1461 switch (offset) {
1462 case 0x00: /* STI_REVISION */
1463 return 0x10;
1464
1465 case 0x10: /* STI_SYSCONFIG */
1466 return s->sysconfig;
1467
1468 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
1469 return 0x00;
1470
1471 case 0x18: /* STI_IRQSTATUS */
1472 return s->irqst;
1473
1474 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
1475 return s->irqen;
1476
1477 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
1478 case 0x28: /* STI_RX_DR / XTI_RXDATA */
1479 break;
1480
1481 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
1482 return s->clkcontrol;
1483
1484 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
1485 return s->serial_config;
1486 }
1487
1488 OMAP_BAD_REG(addr);
1489 return 0;
1490 }
1491
1492 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
1493 uint32_t value)
1494 {
1495 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1496 int offset = addr - s->base;
1497
1498 switch (offset) {
1499 case 0x00: /* STI_REVISION */
1500 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
1501 OMAP_RO_REG(addr);
1502 return;
1503
1504 case 0x10: /* STI_SYSCONFIG */
1505 if (value & (1 << 1)) /* SOFTRESET */
1506 omap_sti_reset(s);
1507 s->sysconfig = value & 0xfe;
1508 break;
1509
1510 case 0x18: /* STI_IRQSTATUS */
1511 s->irqst &= ~value;
1512 omap_sti_interrupt_update(s);
1513 break;
1514
1515 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
1516 s->irqen = value & 0xffff;
1517 omap_sti_interrupt_update(s);
1518 break;
1519
1520 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
1521 s->clkcontrol = value & 0xff;
1522 break;
1523
1524 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
1525 s->serial_config = value & 0xff;
1526 break;
1527
1528 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
1529 case 0x28: /* STI_RX_DR / XTI_RXDATA */
1530 default:
1531 OMAP_BAD_REG(addr);
1532 return;
1533 }
1534 }
1535
1536 static CPUReadMemoryFunc *omap_sti_readfn[] = {
1537 omap_badwidth_read32,
1538 omap_badwidth_read32,
1539 omap_sti_read,
1540 };
1541
1542 static CPUWriteMemoryFunc *omap_sti_writefn[] = {
1543 omap_badwidth_write32,
1544 omap_badwidth_write32,
1545 omap_sti_write,
1546 };
1547
1548 static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
1549 {
1550 OMAP_BAD_REG(addr);
1551 return 0;
1552 }
1553
1554 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
1555 uint32_t value)
1556 {
1557 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
1558 int offset = addr - s->channel_base;
1559 int ch = offset >> 6;
1560 uint8_t byte = value;
1561
1562 if (ch == STI_TRACE_CONTROL_CHANNEL) {
1563 /* Flush channel <i>value</i>. */
1564 qemu_chr_write(s->chr, "\r", 1);
1565 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
1566 if (value == 0xc0 || value == 0xc3) {
1567 /* Open channel <i>ch</i>. */
1568 } else if (value == 0x00)
1569 qemu_chr_write(s->chr, "\n", 1);
1570 else
1571 qemu_chr_write(s->chr, &byte, 1);
1572 }
1573 }
1574
1575 static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
1576 omap_sti_fifo_read,
1577 omap_badwidth_read8,
1578 omap_badwidth_read8,
1579 };
1580
1581 static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
1582 omap_sti_fifo_write,
1583 omap_badwidth_write8,
1584 omap_badwidth_write8,
1585 };
1586
1587 struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
1588 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
1589 CharDriverState *chr)
1590 {
1591 int iomemtype;
1592 struct omap_sti_s *s = (struct omap_sti_s *)
1593 qemu_mallocz(sizeof(struct omap_sti_s));
1594
1595 s->irq = irq;
1596 omap_sti_reset(s);
1597
1598 s->chr = chr ?: qemu_chr_open("null");
1599
1600 iomemtype = cpu_register_io_memory(0, omap_sti_readfn,
1601 omap_sti_writefn, s);
1602 s->base = omap_l4_attach(ta, 0, iomemtype);
1603
1604 iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
1605 omap_sti_fifo_writefn, s);
1606 s->channel_base = channel_base;
1607 cpu_register_physical_memory(s->channel_base, 0x10000, iomemtype);
1608
1609 return s;
1610 }
1611
1612 /* L4 Interconnect */
1613 struct omap_target_agent_s {
1614 struct omap_l4_s *bus;
1615 int regions;
1616 struct omap_l4_region_s *start;
1617 target_phys_addr_t base;
1618 uint32_t component;
1619 uint32_t control;
1620 uint32_t status;
1621 };
1622
1623 struct omap_l4_s {
1624 target_phys_addr_t base;
1625 int ta_num;
1626 struct omap_target_agent_s ta[0];
1627 };
1628
1629 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
1630 {
1631 struct omap_l4_s *bus = qemu_mallocz(
1632 sizeof(*bus) + ta_num * sizeof(*bus->ta));
1633
1634 bus->ta_num = ta_num;
1635 bus->base = base;
1636
1637 return bus;
1638 }
1639
1640 static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
1641 {
1642 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1643 target_phys_addr_t reg = addr - s->base;
1644
1645 switch (reg) {
1646 case 0x00: /* COMPONENT */
1647 return s->component;
1648
1649 case 0x20: /* AGENT_CONTROL */
1650 return s->control;
1651
1652 case 0x28: /* AGENT_STATUS */
1653 return s->status;
1654 }
1655
1656 OMAP_BAD_REG(addr);
1657 return 0;
1658 }
1659
1660 static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
1661 uint32_t value)
1662 {
1663 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
1664 target_phys_addr_t reg = addr - s->base;
1665
1666 switch (reg) {
1667 case 0x00: /* COMPONENT */
1668 case 0x28: /* AGENT_STATUS */
1669 OMAP_RO_REG(addr);
1670 break;
1671
1672 case 0x20: /* AGENT_CONTROL */
1673 s->control = value & 0x01000700;
1674 if (value & 1) /* OCP_RESET */
1675 s->status &= ~1; /* REQ_TIMEOUT */
1676 break;
1677
1678 default:
1679 OMAP_BAD_REG(addr);
1680 }
1681 }
1682
1683 static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
1684 omap_badwidth_read16,
1685 omap_l4ta_read,
1686 omap_badwidth_read16,
1687 };
1688
1689 static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
1690 omap_badwidth_write32,
1691 omap_badwidth_write32,
1692 omap_l4ta_write,
1693 };
1694
1695 #define L4TA(n) (n)
1696 #define L4TAO(n) ((n) + 39)
1697
1698 static struct omap_l4_region_s {
1699 target_phys_addr_t offset;
1700 size_t size;
1701 int access;
1702 } omap_l4_region[125] = {
1703 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
1704 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
1705 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
1706 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
1707 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
1708 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
1709 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
1710 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
1711 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
1712 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
1713 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
1714 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
1715 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
1716 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
1717 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
1718 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
1719 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
1720 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
1721 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
1722 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
1723 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
1724 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
1725 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
1726 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
1727 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
1728 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
1729 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
1730 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
1731 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
1732 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
1733 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
1734 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
1735 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
1736 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
1737 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
1738 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
1739 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
1740 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
1741 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
1742 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
1743 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
1744 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
1745 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
1746 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
1747 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
1748 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
1749 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
1750 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
1751 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
1752 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
1753 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
1754 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
1755 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
1756 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
1757 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
1758 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
1759 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
1760 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
1761 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
1762 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
1763 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
1764 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
1765 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
1766 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
1767 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
1768 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
1769 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
1770 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
1771 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
1772 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
1773 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
1774 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
1775 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
1776 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
1777 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
1778 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
1779 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
1780 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
1781 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
1782 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
1783 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
1784 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
1785 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
1786 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
1787 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
1788 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
1789 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
1790 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
1791 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
1792 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
1793 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
1794 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
1795 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
1796 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
1797 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
1798 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
1799 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
1800 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
1801 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
1802 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
1803 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
1804 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
1805 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
1806 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
1807 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
1808 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
1809 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
1810 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
1811 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
1812 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
1813 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
1814 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
1815 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
1816 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
1817 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
1818 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
1819 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
1820 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
1821 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
1822 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
1823 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
1824 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
1825 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
1826 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
1827 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
1828 };
1829
1830 static struct omap_l4_agent_info_s {
1831 int ta;
1832 int region;
1833 int regions;
1834 int ta_region;
1835 } omap_l4_agent_info[54] = {
1836 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
1837 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
1838 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
1839 { L4TAO(3), 7, 3, 2 }, /* PRCM */
1840 { L4TA(1), 10, 2, 1 }, /* BCM */
1841 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
1842 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
1843 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
1844 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
1845 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
1846 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
1847 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
1848 { L4TA(12), 38, 2, 1 }, /* sDMA */
1849 { L4TA(13), 40, 5, 4 }, /* SSI */
1850 { L4TAO(4), 45, 2, 1 }, /* USB */
1851 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
1852 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
1853 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
1854 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
1855 { L4TA(18), 55, 2, 1 }, /* XTI */
1856 { L4TA(19), 57, 2, 1 }, /* UART1 */
1857 { L4TA(20), 59, 2, 1 }, /* UART2 */
1858 { L4TA(21), 61, 2, 1 }, /* UART3 */
1859 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
1860 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
1861 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
1862 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
1863 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
1864 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
1865 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
1866 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
1867 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
1868 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
1869 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
1870 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
1871 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
1872 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
1873 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
1874 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
1875 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
1876 { L4TA(32), 97, 2, 1 }, /* EAC */
1877 { L4TA(33), 99, 2, 1 }, /* FAC */
1878 { L4TA(34), 101, 2, 1 }, /* IPC */
1879 { L4TA(35), 103, 2, 1 }, /* SPI1 */
1880 { L4TA(36), 105, 2, 1 }, /* SPI2 */
1881 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
1882 { L4TAO(10), 109, 2, 1 },
1883 { L4TAO(11), 111, 2, 1 }, /* RNG */
1884 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1885 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1886 { L4TA(37), 117, 2, 1 }, /* AES */
1887 { L4TA(38), 119, 2, 1 }, /* PKA */
1888 { -1, 121, 2, 1 },
1889 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1890 };
1891
1892 #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
1893 #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
1894
1895 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
1896 {
1897 int i, iomemtype;
1898 struct omap_target_agent_s *ta = 0;
1899 struct omap_l4_agent_info_s *info = 0;
1900
1901 for (i = 0; i < bus->ta_num; i ++)
1902 if (omap_l4_agent_info[i].ta == cs) {
1903 ta = &bus->ta[i];
1904 info = &omap_l4_agent_info[i];
1905 break;
1906 }
1907 if (!ta) {
1908 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
1909 exit(-1);
1910 }
1911
1912 ta->bus = bus;
1913 ta->start = &omap_l4_region[info->region];
1914 ta->regions = info->regions;
1915 ta->base = bus->base + ta->start[info->ta_region].offset;
1916
1917 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
1918 ta->status = 0x00000000;
1919 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
1920
1921 iomemtype = cpu_register_io_memory(0, omap_l4ta_readfn,
1922 omap_l4ta_writefn, ta);
1923 cpu_register_physical_memory(ta->base, 0x200, iomemtype);
1924
1925 return ta;
1926 }
1927
1928 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
1929 int iotype)
1930 {
1931 target_phys_addr_t base;
1932 size_t size;
1933
1934 if (region < 0 || region >= ta->regions) {
1935 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
1936 exit(-1);
1937 }
1938
1939 base = ta->bus->base + ta->start[region].offset;
1940 size = ta->start[region].size;
1941 if (iotype)
1942 cpu_register_physical_memory(base, size, iotype);
1943
1944 return base;
1945 }
1946
1947 /* TEST-Chip-level TAP */
1948 static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
1949 {
1950 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
1951 target_phys_addr_t reg = addr - s->tap_base;
1952
1953 switch (reg) {
1954 case 0x204: /* IDCODE_reg */
1955 switch (s->mpu_model) {
1956 case omap2420:
1957 case omap2422:
1958 case omap2423:
1959 return 0x5b5d902f; /* ES 2.2 */
1960 case omap2430:
1961 return 0x5b68a02f; /* ES 2.2 */
1962 case omap3430:
1963 return 0x1b7ae02f; /* ES 2 */
1964 default:
1965 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
1966 }
1967
1968 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
1969 case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
1970 switch (s->mpu_model) {
1971 case omap2420:
1972 return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
1973 case omap2422:
1974 return 0x000400f0;
1975 case omap2423:
1976 return 0x000800f0;
1977 case omap2430:
1978 return 0x000000f0;
1979 case omap3430:
1980 return 0x000000f0;
1981 default:
1982 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
1983 }
1984
1985 case 0x20c:
1986 switch (s->mpu_model) {
1987 case omap2420:
1988 case omap2422:
1989 case omap2423:
1990 return 0xcafeb5d9; /* ES 2.2 */
1991 case omap2430:
1992 return 0xcafeb68a; /* ES 2.2 */
1993 case omap3430:
1994 return 0xcafeb7ae; /* ES 2 */
1995 default:
1996 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
1997 }
1998
1999 case 0x218: /* DIE_ID_reg */
2000 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2001 case 0x21c: /* DIE_ID_reg */
2002 return 0x54 << 24;
2003 case 0x220: /* DIE_ID_reg */
2004 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2005 case 0x224: /* DIE_ID_reg */
2006 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2007 }
2008
2009 OMAP_BAD_REG(addr);
2010 return 0;
2011 }
2012
2013 static void omap_tap_write(void *opaque, target_phys_addr_t addr,
2014 uint32_t value)
2015 {
2016 OMAP_BAD_REG(addr);
2017 }
2018
2019 static CPUReadMemoryFunc *omap_tap_readfn[] = {
2020 omap_badwidth_read32,
2021 omap_badwidth_read32,
2022 omap_tap_read,
2023 };
2024
2025 static CPUWriteMemoryFunc *omap_tap_writefn[] = {
2026 omap_badwidth_write32,
2027 omap_badwidth_write32,
2028 omap_tap_write,
2029 };
2030
2031 void omap_tap_init(struct omap_target_agent_s *ta,
2032 struct omap_mpu_state_s *mpu)
2033 {
2034 mpu->tap_base = omap_l4_attach(ta, 0, cpu_register_io_memory(0,
2035 omap_tap_readfn, omap_tap_writefn, mpu));
2036 }
2037
2038 /* Power, Reset, and Clock Management */
2039 struct omap_prcm_s {
2040 target_phys_addr_t base;
2041 qemu_irq irq[3];
2042 struct omap_mpu_state_s *mpu;
2043
2044 uint32_t irqst[3];
2045 uint32_t irqen[3];
2046
2047 uint32_t sysconfig;
2048 uint32_t voltctrl;
2049 uint32_t scratch[20];
2050
2051 uint32_t clksrc[1];
2052 uint32_t clkout[1];
2053 uint32_t clkemul[1];
2054 uint32_t clkpol[1];
2055 uint32_t clksel[8];
2056 uint32_t clken[12];
2057 uint32_t clkctrl[4];
2058 uint32_t clkidle[7];
2059 uint32_t setuptime[2];
2060
2061 uint32_t wkup[3];
2062 uint32_t wken[3];
2063 uint32_t wkst[3];
2064 uint32_t rst[4];
2065 uint32_t rstctrl[1];
2066 uint32_t power[4];
2067 uint32_t rsttime_wkup;
2068
2069 uint32_t ev;
2070 uint32_t evtime[2];
2071 };
2072
2073 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
2074 {
2075 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
2076 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
2077 }
2078
2079 static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
2080 {
2081 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2082 int offset = addr - s->base;
2083
2084 switch (offset) {
2085 case 0x000: /* PRCM_REVISION */
2086 return 0x10;
2087
2088 case 0x010: /* PRCM_SYSCONFIG */
2089 return s->sysconfig;
2090
2091 case 0x018: /* PRCM_IRQSTATUS_MPU */
2092 return s->irqst[0];
2093
2094 case 0x01c: /* PRCM_IRQENABLE_MPU */
2095 return s->irqen[0];
2096
2097 case 0x050: /* PRCM_VOLTCTRL */
2098 return s->voltctrl;
2099 case 0x054: /* PRCM_VOLTST */
2100 return s->voltctrl & 3;
2101
2102 case 0x060: /* PRCM_CLKSRC_CTRL */
2103 return s->clksrc[0];
2104 case 0x070: /* PRCM_CLKOUT_CTRL */
2105 return s->clkout[0];
2106 case 0x078: /* PRCM_CLKEMUL_CTRL */
2107 return s->clkemul[0];
2108 case 0x080: /* PRCM_CLKCFG_CTRL */
2109 case 0x084: /* PRCM_CLKCFG_STATUS */
2110 return 0;
2111
2112 case 0x090: /* PRCM_VOLTSETUP */
2113 return s->setuptime[0];
2114
2115 case 0x094: /* PRCM_CLKSSETUP */
2116 return s->setuptime[1];
2117
2118 case 0x098: /* PRCM_POLCTRL */
2119 return s->clkpol[0];
2120
2121 case 0x0b0: /* GENERAL_PURPOSE1 */
2122 case 0x0b4: /* GENERAL_PURPOSE2 */
2123 case 0x0b8: /* GENERAL_PURPOSE3 */
2124 case 0x0bc: /* GENERAL_PURPOSE4 */
2125 case 0x0c0: /* GENERAL_PURPOSE5 */
2126 case 0x0c4: /* GENERAL_PURPOSE6 */
2127 case 0x0c8: /* GENERAL_PURPOSE7 */
2128 case 0x0cc: /* GENERAL_PURPOSE8 */
2129 case 0x0d0: /* GENERAL_PURPOSE9 */
2130 case 0x0d4: /* GENERAL_PURPOSE10 */
2131 case 0x0d8: /* GENERAL_PURPOSE11 */
2132 case 0x0dc: /* GENERAL_PURPOSE12 */
2133 case 0x0e0: /* GENERAL_PURPOSE13 */
2134 case 0x0e4: /* GENERAL_PURPOSE14 */
2135 case 0x0e8: /* GENERAL_PURPOSE15 */
2136 case 0x0ec: /* GENERAL_PURPOSE16 */
2137 case 0x0f0: /* GENERAL_PURPOSE17 */
2138 case 0x0f4: /* GENERAL_PURPOSE18 */
2139 case 0x0f8: /* GENERAL_PURPOSE19 */
2140 case 0x0fc: /* GENERAL_PURPOSE20 */
2141 return s->scratch[(offset - 0xb0) >> 2];
2142
2143 case 0x140: /* CM_CLKSEL_MPU */
2144 return s->clksel[0];
2145 case 0x148: /* CM_CLKSTCTRL_MPU */
2146 return s->clkctrl[0];
2147
2148 case 0x158: /* RM_RSTST_MPU */
2149 return s->rst[0];
2150 case 0x1c8: /* PM_WKDEP_MPU */
2151 return s->wkup[0];
2152 case 0x1d4: /* PM_EVGENCTRL_MPU */
2153 return s->ev;
2154 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2155 return s->evtime[0];
2156 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2157 return s->evtime[1];
2158 case 0x1e0: /* PM_PWSTCTRL_MPU */
2159 return s->power[0];
2160 case 0x1e4: /* PM_PWSTST_MPU */
2161 return 0;
2162
2163 case 0x200: /* CM_FCLKEN1_CORE */
2164 return s->clken[0];
2165 case 0x204: /* CM_FCLKEN2_CORE */
2166 return s->clken[1];
2167 case 0x210: /* CM_ICLKEN1_CORE */
2168 return s->clken[2];
2169 case 0x214: /* CM_ICLKEN2_CORE */
2170 return s->clken[3];
2171 case 0x21c: /* CM_ICLKEN4_CORE */
2172 return s->clken[4];
2173
2174 case 0x220: /* CM_IDLEST1_CORE */
2175 /* TODO: check the actual iclk status */
2176 return 0x7ffffff9;
2177 case 0x224: /* CM_IDLEST2_CORE */
2178 /* TODO: check the actual iclk status */
2179 return 0x00000007;
2180 case 0x22c: /* CM_IDLEST4_CORE */
2181 /* TODO: check the actual iclk status */
2182 return 0x0000001f;
2183
2184 case 0x230: /* CM_AUTOIDLE1_CORE */
2185 return s->clkidle[0];
2186 case 0x234: /* CM_AUTOIDLE2_CORE */
2187 return s->clkidle[1];
2188 case 0x238: /* CM_AUTOIDLE3_CORE */
2189 return s->clkidle[2];
2190 case 0x23c: /* CM_AUTOIDLE4_CORE */
2191 return s->clkidle[3];
2192
2193 case 0x240: /* CM_CLKSEL1_CORE */
2194 return s->clksel[1];
2195 case 0x244: /* CM_CLKSEL2_CORE */
2196 return s->clksel[2];
2197
2198 case 0x248: /* CM_CLKSTCTRL_CORE */
2199 return s->clkctrl[1];
2200
2201 case 0x2a0: /* PM_WKEN1_CORE */
2202 return s->wken[0];
2203 case 0x2a4: /* PM_WKEN2_CORE */
2204 return s->wken[1];
2205
2206 case 0x2b0: /* PM_WKST1_CORE */
2207 return s->wkst[0];
2208 case 0x2b4: /* PM_WKST2_CORE */
2209 return s->wkst[1];
2210 case 0x2c8: /* PM_WKDEP_CORE */
2211 return 0x1e;
2212
2213 case 0x2e0: /* PM_PWSTCTRL_CORE */
2214 return s->power[1];
2215 case 0x2e4: /* PM_PWSTST_CORE */
2216 return 0x000030 | (s->power[1] & 0xfc00);
2217
2218 case 0x300: /* CM_FCLKEN_GFX */
2219 return s->clken[5];
2220 case 0x310: /* CM_ICLKEN_GFX */
2221 return s->clken[6];
2222 case 0x320: /* CM_IDLEST_GFX */
2223 /* TODO: check the actual iclk status */
2224 return 0x00000001;
2225 case 0x340: /* CM_CLKSEL_GFX */
2226 return s->clksel[3];
2227 case 0x348: /* CM_CLKSTCTRL_GFX */
2228 return s->clkctrl[2];
2229 case 0x350: /* RM_RSTCTRL_GFX */
2230 return s->rstctrl[0];
2231 case 0x358: /* RM_RSTST_GFX */
2232 return s->rst[1];
2233 case 0x3c8: /* PM_WKDEP_GFX */
2234 return s->wkup[1];
2235
2236 case 0x3e0: /* PM_PWSTCTRL_GFX */
2237 return s->power[2];
2238 case 0x3e4: /* PM_PWSTST_GFX */
2239 return s->power[2] & 3;
2240
2241 case 0x400: /* CM_FCLKEN_WKUP */
2242 return s->clken[7];
2243 case 0x410: /* CM_ICLKEN_WKUP */
2244 return s->clken[8];
2245 case 0x420: /* CM_IDLEST_WKUP */
2246 /* TODO: check the actual iclk status */
2247 return 0x0000003f;
2248 case 0x430: /* CM_AUTOIDLE_WKUP */
2249 return s->clkidle[4];
2250 case 0x440: /* CM_CLKSEL_WKUP */
2251 return s->clksel[4];
2252 case 0x450: /* RM_RSTCTRL_WKUP */
2253 return 0;
2254 case 0x454: /* RM_RSTTIME_WKUP */
2255 return s->rsttime_wkup;
2256 case 0x458: /* RM_RSTST_WKUP */
2257 return s->rst[2];
2258 case 0x4a0: /* PM_WKEN_WKUP */
2259 return s->wken[2];
2260 case 0x4b0: /* PM_WKST_WKUP */
2261 return s->wkst[2];
2262
2263 case 0x500: /* CM_CLKEN_PLL */
2264 return s->clken[9];
2265 case 0x520: /* CM_IDLEST_CKGEN */
2266 /* Core uses 32-kHz clock */
2267 if (!(s->clksel[6] & 3))
2268 return 0x00000377;
2269 /* DPLL not in lock mode, core uses ref_clk */
2270 if ((s->clken[9] & 3) != 3)
2271 return 0x00000375;
2272 /* Core uses DPLL */
2273 return 0x00000376;
2274 case 0x530: /* CM_AUTOIDLE_PLL */
2275 return s->clkidle[5];
2276 case 0x540: /* CM_CLKSEL1_PLL */
2277 return s->clksel[5];
2278 case 0x544: /* CM_CLKSEL2_PLL */
2279 return s->clksel[6];
2280
2281 case 0x800: /* CM_FCLKEN_DSP */
2282 return s->clken[10];
2283 case 0x810: /* CM_ICLKEN_DSP */
2284 return s->clken[11];
2285 case 0x820: /* CM_IDLEST_DSP */
2286 /* TODO: check the actual iclk status */
2287 return 0x00000103;
2288 case 0x830: /* CM_AUTOIDLE_DSP */
2289 return s->clkidle[6];
2290 case 0x840: /* CM_CLKSEL_DSP */
2291 return s->clksel[7];
2292 case 0x848: /* CM_CLKSTCTRL_DSP */
2293 return s->clkctrl[3];
2294 case 0x850: /* RM_RSTCTRL_DSP */
2295 return 0;
2296 case 0x858: /* RM_RSTST_DSP */
2297 return s->rst[3];
2298 case 0x8c8: /* PM_WKDEP_DSP */
2299 return s->wkup[2];
2300 case 0x8e0: /* PM_PWSTCTRL_DSP */
2301 return s->power[3];
2302 case 0x8e4: /* PM_PWSTST_DSP */
2303 return 0x008030 | (s->power[3] & 0x3003);
2304
2305 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2306 return s->irqst[1];
2307 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2308 return s->irqen[1];
2309
2310 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2311 return s->irqst[2];
2312 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2313 return s->irqen[2];
2314 }
2315
2316 OMAP_BAD_REG(addr);
2317 return 0;
2318 }
2319
2320 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
2321 uint32_t value)
2322 {
2323 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2324 int offset = addr - s->base;
2325
2326 switch (offset) {
2327 case 0x000: /* PRCM_REVISION */
2328 case 0x054: /* PRCM_VOLTST */
2329 case 0x084: /* PRCM_CLKCFG_STATUS */
2330 case 0x1e4: /* PM_PWSTST_MPU */
2331 case 0x220: /* CM_IDLEST1_CORE */
2332 case 0x224: /* CM_IDLEST2_CORE */
2333 case 0x22c: /* CM_IDLEST4_CORE */
2334 case 0x2c8: /* PM_WKDEP_CORE */
2335 case 0x2e4: /* PM_PWSTST_CORE */
2336 case 0x320: /* CM_IDLEST_GFX */
2337 case 0x3e4: /* PM_PWSTST_GFX */
2338 case 0x420: /* CM_IDLEST_WKUP */
2339 case 0x520: /* CM_IDLEST_CKGEN */
2340 case 0x820: /* CM_IDLEST_DSP */
2341 case 0x8e4: /* PM_PWSTST_DSP */
2342 OMAP_RO_REG(addr);
2343 return;
2344
2345 case 0x010: /* PRCM_SYSCONFIG */
2346 s->sysconfig = value & 1;
2347 break;
2348
2349 case 0x018: /* PRCM_IRQSTATUS_MPU */
2350 s->irqst[0] &= ~value;
2351 omap_prcm_int_update(s, 0);
2352 break;
2353 case 0x01c: /* PRCM_IRQENABLE_MPU */
2354 s->irqen[0] = value & 0x3f;
2355 omap_prcm_int_update(s, 0);
2356 break;
2357
2358 case 0x050: /* PRCM_VOLTCTRL */
2359 s->voltctrl = value & 0xf1c3;
2360 break;
2361
2362 case 0x060: /* PRCM_CLKSRC_CTRL */
2363 s->clksrc[0] = value & 0xdb;
2364 /* TODO update clocks */
2365 break;
2366
2367 case 0x070: /* PRCM_CLKOUT_CTRL */
2368 s->clkout[0] = value & 0xbbbb;
2369 /* TODO update clocks */
2370 break;
2371
2372 case 0x078: /* PRCM_CLKEMUL_CTRL */
2373 s->clkemul[0] = value & 1;
2374 /* TODO update clocks */
2375 break;
2376
2377 case 0x080: /* PRCM_CLKCFG_CTRL */
2378 break;
2379
2380 case 0x090: /* PRCM_VOLTSETUP */
2381 s->setuptime[0] = value & 0xffff;
2382 break;
2383 case 0x094: /* PRCM_CLKSSETUP */
2384 s->setuptime[1] = value & 0xffff;
2385 break;
2386
2387 case 0x098: /* PRCM_POLCTRL */
2388 s->clkpol[0] = value & 0x701;
2389 break;
2390
2391 case 0x0b0: /* GENERAL_PURPOSE1 */
2392 case 0x0b4: /* GENERAL_PURPOSE2 */
2393 case 0x0b8: /* GENERAL_PURPOSE3 */
2394 case 0x0bc: /* GENERAL_PURPOSE4 */
2395 case 0x0c0: /* GENERAL_PURPOSE5 */
2396 case 0x0c4: /* GENERAL_PURPOSE6 */
2397 case 0x0c8: /* GENERAL_PURPOSE7 */
2398 case 0x0cc: /* GENERAL_PURPOSE8 */
2399 case 0x0d0: /* GENERAL_PURPOSE9 */
2400 case 0x0d4: /* GENERAL_PURPOSE10 */
2401 case 0x0d8: /* GENERAL_PURPOSE11 */
2402 case 0x0dc: /* GENERAL_PURPOSE12 */
2403 case 0x0e0: /* GENERAL_PURPOSE13 */
2404 case 0x0e4: /* GENERAL_PURPOSE14 */
2405 case 0x0e8: /* GENERAL_PURPOSE15 */
2406 case 0x0ec: /* GENERAL_PURPOSE16 */
2407 case 0x0f0: /* GENERAL_PURPOSE17 */
2408 case 0x0f4: /* GENERAL_PURPOSE18 */
2409 case 0x0f8: /* GENERAL_PURPOSE19 */
2410 case 0x0fc: /* GENERAL_PURPOSE20 */
2411 s->scratch[(offset - 0xb0) >> 2] = value;
2412 break;
2413
2414 case 0x140: /* CM_CLKSEL_MPU */
2415 s->clksel[0] = value & 0x1f;
2416 /* TODO update clocks */
2417 break;
2418 case 0x148: /* CM_CLKSTCTRL_MPU */
2419 s->clkctrl[0] = value & 0x1f;
2420 break;
2421
2422 case 0x158: /* RM_RSTST_MPU */
2423 s->rst[0] &= ~value;
2424 break;
2425 case 0x1c8: /* PM_WKDEP_MPU */
2426 s->wkup[0] = value & 0x15;
2427 break;
2428
2429 case 0x1d4: /* PM_EVGENCTRL_MPU */
2430 s->ev = value & 0x1f;
2431 break;
2432 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2433 s->evtime[0] = value;
2434 break;
2435 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2436 s->evtime[1] = value;
2437 break;
2438
2439 case 0x1e0: /* PM_PWSTCTRL_MPU */
2440 s->power[0] = value & 0xc0f;
2441 break;
2442
2443 case 0x200: /* CM_FCLKEN1_CORE */
2444 s->clken[0] = value & 0xbfffffff;
2445 /* TODO update clocks */
2446 break;
2447 case 0x204: /* CM_FCLKEN2_CORE */
2448 s->clken[1] = value & 0x00000007;
2449 /* TODO update clocks */
2450 break;
2451 case 0x210: /* CM_ICLKEN1_CORE */
2452 s->clken[2] = value & 0xfffffff9;
2453 /* TODO update clocks */
2454 break;
2455 case 0x214: /* CM_ICLKEN2_CORE */
2456 s->clken[3] = value & 0x00000007;
2457 /* TODO update clocks */
2458 break;
2459 case 0x21c: /* CM_ICLKEN4_CORE */
2460 s->clken[4] = value & 0x0000001f;
2461 /* TODO update clocks */
2462 break;
2463
2464 case 0x230: /* CM_AUTOIDLE1_CORE */
2465 s->clkidle[0] = value & 0xfffffff9;
2466 /* TODO update clocks */
2467 break;
2468 case 0x234: /* CM_AUTOIDLE2_CORE */
2469 s->clkidle[1] = value & 0x00000007;
2470 /* TODO update clocks */
2471 break;
2472 case 0x238: /* CM_AUTOIDLE3_CORE */
2473 s->clkidle[2] = value & 0x00000007;
2474 /* TODO update clocks */
2475 break;
2476 case 0x23c: /* CM_AUTOIDLE4_CORE */
2477 s->clkidle[3] = value & 0x0000001f;
2478 /* TODO update clocks */
2479 break;
2480
2481 case 0x240: /* CM_CLKSEL1_CORE */
2482 s->clksel[1] = value & 0x0fffbf7f;
2483 /* TODO update clocks */
2484 break;
2485
2486 case 0x244: /* CM_CLKSEL2_CORE */
2487 s->clksel[2] = value & 0x00fffffc;
2488 /* TODO update clocks */
2489 break;
2490
2491 case 0x248: /* CM_CLKSTCTRL_CORE */
2492 s->clkctrl[1] = value & 0x7;
2493 break;
2494
2495 case 0x2a0: /* PM_WKEN1_CORE */
2496 s->wken[0] = value & 0x04667ff8;
2497 break;
2498 case 0x2a4: /* PM_WKEN2_CORE */
2499 s->wken[1] = value & 0x00000005;
2500 break;
2501
2502 case 0x2b0: /* PM_WKST1_CORE */
2503 s->wkst[0] &= ~value;
2504 break;
2505 case 0x2b4: /* PM_WKST2_CORE */
2506 s->wkst[1] &= ~value;
2507 break;
2508
2509 case 0x2e0: /* PM_PWSTCTRL_CORE */
2510 s->power[1] = (value & 0x00fc3f) | (1 << 2);
2511 break;
2512
2513 case 0x300: /* CM_FCLKEN_GFX */
2514 s->clken[5] = value & 6;
2515 /* TODO update clocks */
2516 break;
2517 case 0x310: /* CM_ICLKEN_GFX */
2518 s->clken[6] = value & 1;
2519 /* TODO update clocks */
2520 break;
2521 case 0x340: /* CM_CLKSEL_GFX */
2522 s->clksel[3] = value & 7;
2523 /* TODO update clocks */
2524 break;
2525 case 0x348: /* CM_CLKSTCTRL_GFX */
2526 s->clkctrl[2] = value & 1;
2527 break;
2528 case 0x350: /* RM_RSTCTRL_GFX */
2529 s->rstctrl[0] = value & 1;
2530 /* TODO: reset */
2531 break;
2532 case 0x358: /* RM_RSTST_GFX */
2533 s->rst[1] &= ~value;
2534 break;
2535 case 0x3c8: /* PM_WKDEP_GFX */
2536 s->wkup[1] = value & 0x13;
2537 break;
2538 case 0x3e0: /* PM_PWSTCTRL_GFX */
2539 s->power[2] = (value & 0x00c0f) | (3 << 2);
2540 break;
2541
2542 case 0x400: /* CM_FCLKEN_WKUP */
2543 s->clken[7] = value & 0xd;
2544 /* TODO update clocks */
2545 break;
2546 case 0x410: /* CM_ICLKEN_WKUP */
2547 s->clken[8] = value & 0x3f;
2548 /* TODO update clocks */
2549 break;
2550 case 0x430: /* CM_AUTOIDLE_WKUP */
2551 s->clkidle[4] = value & 0x0000003f;
2552 /* TODO update clocks */
2553 break;
2554 case 0x440: /* CM_CLKSEL_WKUP */
2555 s->clksel[4] = value & 3;
2556 /* TODO update clocks */
2557 break;
2558 case 0x450: /* RM_RSTCTRL_WKUP */
2559 /* TODO: reset */
2560 if (value & 2)
2561 qemu_system_reset_request();
2562 break;
2563 case 0x454: /* RM_RSTTIME_WKUP */
2564 s->rsttime_wkup = value & 0x1fff;
2565 break;
2566 case 0x458: /* RM_RSTST_WKUP */
2567 s->rst[2] &= ~value;
2568 break;
2569 case 0x4a0: /* PM_WKEN_WKUP */
2570 s->wken[2] = value & 0x00000005;
2571 break;
2572 case 0x4b0: /* PM_WKST_WKUP */
2573 s->wkst[2] &= ~value;
2574 break;
2575
2576 case 0x500: /* CM_CLKEN_PLL */
2577 s->clken[9] = value & 0xcf;
2578 /* TODO update clocks */
2579 break;
2580 case 0x530: /* CM_AUTOIDLE_PLL */
2581 s->clkidle[5] = value & 0x000000cf;
2582 /* TODO update clocks */
2583 break;
2584 case 0x540: /* CM_CLKSEL1_PLL */
2585 s->clksel[5] = value & 0x03bfff28;
2586 /* TODO update clocks */
2587 break;
2588 case 0x544: /* CM_CLKSEL2_PLL */
2589 s->clksel[6] = value & 3;
2590 /* TODO update clocks */
2591 break;
2592
2593 case 0x800: /* CM_FCLKEN_DSP */
2594 s->clken[10] = value & 0x501;
2595 /* TODO update clocks */
2596 break;
2597 case 0x810: /* CM_ICLKEN_DSP */
2598 s->clken[11] = value & 0x2;
2599 /* TODO update clocks */
2600 break;
2601 case 0x830: /* CM_AUTOIDLE_DSP */
2602 s->clkidle[6] = value & 0x2;
2603 /* TODO update clocks */
2604 break;
2605 case 0x840: /* CM_CLKSEL_DSP */
2606 s->clksel[7] = value & 0x3fff;
2607 /* TODO update clocks */
2608 break;
2609 case 0x848: /* CM_CLKSTCTRL_DSP */
2610 s->clkctrl[3] = value & 0x101;
2611 break;
2612 case 0x850: /* RM_RSTCTRL_DSP */
2613 /* TODO: reset */
2614 break;
2615 case 0x858: /* RM_RSTST_DSP */
2616 s->rst[3] &= ~value;
2617 break;
2618 case 0x8c8: /* PM_WKDEP_DSP */
2619 s->wkup[2] = value & 0x13;
2620 break;
2621 case 0x8e0: /* PM_PWSTCTRL_DSP */
2622 s->power[3] = (value & 0x03017) | (3 << 2);
2623 break;
2624
2625 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2626 s->irqst[1] &= ~value;
2627 omap_prcm_int_update(s, 1);
2628 break;
2629 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2630 s->irqen[1] = value & 0x7;
2631 omap_prcm_int_update(s, 1);
2632 break;
2633
2634 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2635 s->irqst[2] &= ~value;
2636 omap_prcm_int_update(s, 2);
2637 break;
2638 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2639 s->irqen[2] = value & 0x7;
2640 omap_prcm_int_update(s, 2);
2641 break;
2642
2643 default:
2644 OMAP_BAD_REG(addr);
2645 return;
2646 }
2647 }
2648
2649 static CPUReadMemoryFunc *omap_prcm_readfn[] = {
2650 omap_badwidth_read32,
2651 omap_badwidth_read32,
2652 omap_prcm_read,
2653 };
2654
2655 static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
2656 omap_badwidth_write32,
2657 omap_badwidth_write32,
2658 omap_prcm_write,
2659 };
2660
2661 static void omap_prcm_reset(struct omap_prcm_s *s)
2662 {
2663 s->sysconfig = 0;
2664 s->irqst[0] = 0;
2665 s->irqst[1] = 0;
2666 s->irqst[2] = 0;
2667 s->irqen[0] = 0;
2668 s->irqen[1] = 0;
2669 s->irqen[2] = 0;
2670 s->voltctrl = 0x1040;
2671 s->ev = 0x14;
2672 s->evtime[0] = 0;
2673 s->evtime[1] = 0;
2674 s->clkctrl[0] = 0;
2675 s->clkctrl[1] = 0;
2676 s->clkctrl[2] = 0;
2677 s->clkctrl[3] = 0;
2678 s->clken[1] = 7;
2679 s->clken[3] = 7;
2680 s->clken[4] = 0;
2681 s->clken[5] = 0;
2682 s->clken[6] = 0;
2683 s->clken[7] = 0xc;
2684 s->clken[8] = 0x3e;
2685 s->clken[9] = 0x0d;
2686 s->clken[10] = 0;
2687 s->clken[11] = 0;
2688 s->clkidle[0] = 0;
2689 s->clkidle[2] = 7;
2690 s->clkidle[3] = 0;
2691 s->clkidle[4] = 0;
2692 s->clkidle[5] = 0x0c;
2693 s->clkidle[6] = 0;
2694 s->clksel[0] = 0x01;
2695 s->clksel[1] = 0x02100121;
2696 s->clksel[2] = 0x00000000;
2697 s->clksel[3] = 0x01;
2698 s->clksel[4] = 0;
2699 s->clksel[7] = 0x0121;
2700 s->wkup[0] = 0x15;
2701 s->wkup[1] = 0x13;
2702 s->wkup[2] = 0x13;
2703 s->wken[0] = 0x04667ff8;
2704 s->wken[1] = 0x00000005;
2705 s->wken[2] = 5;
2706 s->wkst[0] = 0;
2707 s->wkst[1] = 0;
2708 s->wkst[2] = 0;
2709 s->power[0] = 0x00c;
2710 s->power[1] = 4;
2711 s->power[2] = 0x0000c;
2712 s->power[3] = 0x14;
2713 s->rstctrl[0] = 1;
2714 s->rst[3] = 1;
2715 }
2716
2717 static void omap_prcm_coldreset(struct omap_prcm_s *s)
2718 {
2719 s->setuptime[0] = 0;
2720 s->setuptime[1] = 0;
2721 memset(&s->scratch, 0, sizeof(s->scratch));
2722 s->rst[0] = 0x01;
2723 s->rst[1] = 0x00;
2724 s->rst[2] = 0x01;
2725 s->clken[0] = 0;
2726 s->clken[2] = 0;
2727 s->clkidle[1] = 0;
2728 s->clksel[5] = 0;
2729 s->clksel[6] = 2;
2730 s->clksrc[0] = 0x43;
2731 s->clkout[0] = 0x0303;
2732 s->clkemul[0] = 0;
2733 s->clkpol[0] = 0x100;
2734 s->rsttime_wkup = 0x1002;
2735
2736 omap_prcm_reset(s);
2737 }
2738
2739 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
2740 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
2741 struct omap_mpu_state_s *mpu)
2742 {
2743 int iomemtype;
2744 struct omap_prcm_s *s = (struct omap_prcm_s *)
2745 qemu_mallocz(sizeof(struct omap_prcm_s));
2746
2747 s->irq[0] = mpu_int;
2748 s->irq[1] = dsp_int;
2749 s->irq[2] = iva_int;
2750 s->mpu = mpu;
2751 omap_prcm_coldreset(s);
2752
2753 iomemtype = cpu_register_io_memory(0, omap_prcm_readfn,
2754 omap_prcm_writefn, s);
2755 s->base = omap_l4_attach(ta, 0, iomemtype);
2756 omap_l4_attach(ta, 1, iomemtype);
2757
2758 return s;
2759 }
2760
2761 /* System and Pinout control */
2762 struct omap_sysctl_s {
2763 target_phys_addr_t base;
2764 struct omap_mpu_state_s *mpu;
2765
2766 uint32_t sysconfig;
2767 uint32_t devconfig;
2768 uint32_t psaconfig;
2769 uint32_t padconf[0x45];
2770 uint8_t obs;
2771 uint32_t msuspendmux[5];
2772 };
2773
2774 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
2775 {
2776 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2777 int offset = addr - s->base;
2778
2779 switch (offset) {
2780 case 0x000: /* CONTROL_REVISION */
2781 return 0x20;
2782
2783 case 0x010: /* CONTROL_SYSCONFIG */
2784 return s->sysconfig;
2785
2786 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2787 return s->padconf[(offset - 0x30) >> 2];
2788
2789 case 0x270: /* CONTROL_DEBOBS */
2790 return s->obs;
2791
2792 case 0x274: /* CONTROL_DEVCONF */
2793 return s->devconfig;
2794
2795 case 0x28c: /* CONTROL_EMU_SUPPORT */
2796 return 0;
2797
2798 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2799 return s->msuspendmux[0];
2800 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2801 return s->msuspendmux[1];
2802 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2803 return s->msuspendmux[2];
2804 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2805 return s->msuspendmux[3];
2806 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2807 return s->msuspendmux[4];
2808 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2809 return 0;
2810
2811 case 0x2b8: /* CONTROL_PSA_CTRL */
2812 return s->psaconfig;
2813 case 0x2bc: /* CONTROL_PSA_CMD */
2814 case 0x2c0: /* CONTROL_PSA_VALUE */
2815 return 0;
2816
2817 case 0x2b0: /* CONTROL_SEC_CTRL */
2818 return 0x800000f1;
2819 case 0x2d0: /* CONTROL_SEC_EMU */
2820 return 0x80000015;
2821 case 0x2d4: /* CONTROL_SEC_TAP */
2822 return 0x8000007f;
2823 case 0x2b4: /* CONTROL_SEC_TEST */
2824 case 0x2f0: /* CONTROL_SEC_STATUS */
2825 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2826 /* Secure mode is not present on general-pusrpose device. Outside
2827 * secure mode these values cannot be read or written. */
2828 return 0;
2829
2830 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2831 return 0xff;
2832 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2833 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2834 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2835 /* No secure mode so no Extended Secure RAM present. */
2836 return 0;
2837
2838 case 0x2f8: /* CONTROL_STATUS */
2839 /* Device Type => General-purpose */
2840 return 0x0300;
2841 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2842
2843 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2844 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2845 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2846 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2847 return 0xdecafbad;
2848
2849 case 0x310: /* CONTROL_RAND_KEY_0 */
2850 case 0x314: /* CONTROL_RAND_KEY_1 */
2851 case 0x318: /* CONTROL_RAND_KEY_2 */
2852 case 0x31c: /* CONTROL_RAND_KEY_3 */
2853 case 0x320: /* CONTROL_CUST_KEY_0 */
2854 case 0x324: /* CONTROL_CUST_KEY_1 */
2855 case 0x330: /* CONTROL_TEST_KEY_0 */
2856 case 0x334: /* CONTROL_TEST_KEY_1 */
2857 case 0x338: /* CONTROL_TEST_KEY_2 */
2858 case 0x33c: /* CONTROL_TEST_KEY_3 */
2859 case 0x340: /* CONTROL_TEST_KEY_4 */
2860 case 0x344: /* CONTROL_TEST_KEY_5 */
2861 case 0x348: /* CONTROL_TEST_KEY_6 */
2862 case 0x34c: /* CONTROL_TEST_KEY_7 */
2863 case 0x350: /* CONTROL_TEST_KEY_8 */
2864 case 0x354: /* CONTROL_TEST_KEY_9 */
2865 /* Can only be accessed in secure mode and when C_FieldAccEnable
2866 * bit is set in CONTROL_SEC_CTRL.
2867 * TODO: otherwise an interconnect access error is generated. */
2868 return 0;
2869 }
2870
2871 OMAP_BAD_REG(addr);
2872 return 0;
2873 }
2874
2875 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
2876 uint32_t value)
2877 {
2878 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2879 int offset = addr - s->base;
2880
2881 switch (offset) {
2882 case 0x000: /* CONTROL_REVISION */
2883 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2884 case 0x2c0: /* CONTROL_PSA_VALUE */
2885 case 0x2f8: /* CONTROL_STATUS */
2886 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2887 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2888 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2889 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2890 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2891 case 0x310: /* CONTROL_RAND_KEY_0 */
2892 case 0x314: /* CONTROL_RAND_KEY_1 */
2893 case 0x318: /* CONTROL_RAND_KEY_2 */
2894 case 0x31c: /* CONTROL_RAND_KEY_3 */
2895 case 0x320: /* CONTROL_CUST_KEY_0 */
2896 case 0x324: /* CONTROL_CUST_KEY_1 */
2897 case 0x330: /* CONTROL_TEST_KEY_0 */
2898 case 0x334: /* CONTROL_TEST_KEY_1 */
2899 case 0x338: /* CONTROL_TEST_KEY_2 */
2900 case 0x33c: /* CONTROL_TEST_KEY_3 */
2901 case 0x340: /* CONTROL_TEST_KEY_4 */
2902 case 0x344: /* CONTROL_TEST_KEY_5 */
2903 case 0x348: /* CONTROL_TEST_KEY_6 */
2904 case 0x34c: /* CONTROL_TEST_KEY_7 */
2905 case 0x350: /* CONTROL_TEST_KEY_8 */
2906 case 0x354: /* CONTROL_TEST_KEY_9 */
2907 OMAP_RO_REG(addr);
2908 return;
2909
2910 case 0x010: /* CONTROL_SYSCONFIG */
2911 s->sysconfig = value & 0x1e;
2912 break;
2913
2914 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2915 /* XXX: should check constant bits */
2916 s->padconf[(offset - 0x30) >> 2] = value & 0x1f1f1f1f;
2917 break;
2918
2919 case 0x270: /* CONTROL_DEBOBS */
2920 s->obs = value & 0xff;
2921 break;
2922
2923 case 0x274: /* CONTROL_DEVCONF */
2924 s->devconfig = value & 0xffffc7ff;
2925 break;
2926
2927 case 0x28c: /* CONTROL_EMU_SUPPORT */
2928 break;
2929
2930 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2931 s->msuspendmux[0] = value & 0x3fffffff;
2932 break;
2933 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2934 s->msuspendmux[1] = value & 0x3fffffff;
2935 break;
2936 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2937 s->msuspendmux[2] = value & 0x3fffffff;
2938 break;
2939 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2940 s->msuspendmux[3] = value & 0x3fffffff;
2941 break;
2942 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2943 s->msuspendmux[4] = value & 0x3fffffff;
2944 break;
2945
2946 case 0x2b8: /* CONTROL_PSA_CTRL */
2947 s->psaconfig = value & 0x1c;
2948 s->psaconfig |= (value & 0x20) ? 2 : 1;
2949 break;
2950 case 0x2bc: /* CONTROL_PSA_CMD */
2951 break;
2952
2953 case 0x2b0: /* CONTROL_SEC_CTRL */
2954 case 0x2b4: /* CONTROL_SEC_TEST */
2955 case 0x2d0: /* CONTROL_SEC_EMU */
2956 case 0x2d4: /* CONTROL_SEC_TAP */
2957 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2958 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2959 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2960 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2961 case 0x2f0: /* CONTROL_SEC_STATUS */
2962 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2963 break;
2964
2965 default:
2966 OMAP_BAD_REG(addr);
2967 return;
2968 }
2969 }
2970
2971 static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
2972 omap_badwidth_read32, /* TODO */
2973 omap_badwidth_read32, /* TODO */
2974 omap_sysctl_read,
2975 };
2976
2977 static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
2978 omap_badwidth_write32, /* TODO */
2979 omap_badwidth_write32, /* TODO */
2980 omap_sysctl_write,
2981 };
2982
2983 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2984 {
2985 /* (power-on reset) */
2986 s->sysconfig = 0;
2987 s->obs = 0;
2988 s->devconfig = 0x0c000000;
2989 s->msuspendmux[0] = 0x00000000;
2990 s->msuspendmux[1] = 0x00000000;
2991 s->msuspendmux[2] = 0x00000000;
2992 s->msuspendmux[3] = 0x00000000;
2993 s->msuspendmux[4] = 0x00000000;
2994 s->psaconfig = 1;
2995
2996 s->padconf[0x00] = 0x000f0f0f;
2997 s->padconf[0x01] = 0x00000000;
2998 s->padconf[0x02] = 0x00000000;
2999 s->padconf[0x03] = 0x00000000;
3000 s->padconf[0x04] = 0x00000000;
3001 s->padconf[0x05] = 0x00000000;
3002 s->padconf[0x06] = 0x00000000;
3003 s->padconf[0x07] = 0x00000000;
3004 s->padconf[0x08] = 0x08080800;
3005 s->padconf[0x09] = 0x08080808;
3006 s->padconf[0x0a] = 0x08080808;
3007 s->padconf[0x0b] = 0x08080808;
3008 s->padconf[0x0c] = 0x08080808;
3009 s->padconf[0x0d] = 0x08080800;
3010 s->padconf[0x0e] = 0x08080808;
3011 s->padconf[0x0f] = 0x08080808;
3012 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
3013 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
3014 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
3015 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
3016 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
3017 s->padconf[0x15] = 0x18181818;
3018 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
3019 s->padconf[0x17] = 0x1f001f00;
3020 s->padconf[0x18] = 0x1f1f1f1f;
3021 s->padconf[0x19] = 0x00000000;
3022 s->padconf[0x1a] = 0x1f180000;
3023 s->padconf[0x1b] = 0x00001f1f;
3024 s->padconf[0x1c] = 0x1f001f00;
3025 s->padconf[0x1d] = 0x00000000;
3026 s->padconf[0x1e] = 0x00000000;
3027 s->padconf[0x1f] = 0x08000000;
3028 s->padconf[0x20] = 0x08080808;
3029 s->padconf[0x21] = 0x08080808;
3030 s->padconf[0x22] = 0x0f080808;
3031 s->padconf[0x23] = 0x0f0f0f0f;
3032 s->padconf[0x24] = 0x000f0f0f;
3033 s->padconf[0x25] = 0x1f1f1f0f;
3034 s->padconf[0x26] = 0x080f0f1f;
3035 s->padconf[0x27] = 0x070f1808;
3036 s->padconf[0x28] = 0x0f070707;
3037 s->padconf[0x29] = 0x000f0f1f;
3038 s->padconf[0x2a] = 0x0f0f0f1f;
3039 s->padconf[0x2b] = 0x08000000;
3040 s->padconf[0x2c] = 0x0000001f;
3041 s->padconf[0x2d] = 0x0f0f1f00;
3042 s->padconf[0x2e] = 0x1f1f0f0f;
3043 s->padconf[0x2f] = 0x0f1f1f1f;
3044 s->padconf[0x30] = 0x0f0f0f0f;
3045 s->padconf[0x31] = 0x0f1f0f1f;
3046 s->padconf[0x32] = 0x0f0f0f0f;
3047 s->padconf[0x33] = 0x0f1f0f1f;
3048 s->padconf[0x34] = 0x1f1f0f0f;
3049 s->padconf[0x35] = 0x0f0f1f1f;
3050 s->padconf[0x36] = 0x0f0f1f0f;
3051 s->padconf[0x37] = 0x0f0f0f0f;
3052 s->padconf[0x38] = 0x1f18180f;
3053 s->padconf[0x39] = 0x1f1f1f1f;
3054 s->padconf[0x3a] = 0x00001f1f;
3055 s->padconf[0x3b] = 0x00000000;
3056 s->padconf[0x3c] = 0x00000000;
3057 s->padconf[0x3d] = 0x0f0f0f0f;
3058 s->padconf[0x3e] = 0x18000f0f;
3059 s->padconf[0x3f] = 0x00070000;
3060 s->padconf[0x40] = 0x00000707;
3061 s->padconf[0x41] = 0x0f1f0700;
3062 s->padconf[0x42] = 0x1f1f070f;
3063 s->padconf[0x43] = 0x0008081f;
3064 s->padconf[0x44] = 0x00000800;
3065 }
3066
3067 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
3068 omap_clk iclk, struct omap_mpu_state_s *mpu)
3069 {
3070 int iomemtype;
3071 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
3072 qemu_mallocz(sizeof(struct omap_sysctl_s));
3073
3074 s->mpu = mpu;
3075 omap_sysctl_reset(s);
3076
3077 iomemtype = cpu_register_io_memory(0, omap_sysctl_readfn,
3078 omap_sysctl_writefn, s);
3079 s->base = omap_l4_attach(ta, 0, iomemtype);
3080 omap_l4_attach(ta, 0, iomemtype);
3081
3082 return s;
3083 }
3084
3085 /* SDRAM Controller Subsystem */
3086 struct omap_sdrc_s {
3087 target_phys_addr_t base;
3088
3089 uint8_t config;
3090 };
3091
3092 static void omap_sdrc_reset(struct omap_sdrc_s *s)
3093 {
3094 s->config = 0x10;
3095 }
3096
3097 static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
3098 {
3099 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3100 int offset = addr - s->base;
3101
3102 switch (offset) {
3103 case 0x00: /* SDRC_REVISION */
3104 return 0x20;
3105
3106 case 0x10: /* SDRC_SYSCONFIG */
3107 return s->config;
3108
3109 case 0x14: /* SDRC_SYSSTATUS */
3110 return 1; /* RESETDONE */
3111
3112 case 0x40: /* SDRC_CS_CFG */
3113 case 0x44: /* SDRC_SHARING */
3114 case 0x48: /* SDRC_ERR_ADDR */
3115 case 0x4c: /* SDRC_ERR_TYPE */
3116 case 0x60: /* SDRC_DLLA_SCTRL */
3117 case 0x64: /* SDRC_DLLA_STATUS */
3118 case 0x68: /* SDRC_DLLB_CTRL */
3119 case 0x6c: /* SDRC_DLLB_STATUS */
3120 case 0x70: /* SDRC_POWER */
3121 case 0x80: /* SDRC_MCFG_0 */
3122 case 0x84: /* SDRC_MR_0 */
3123 case 0x88: /* SDRC_EMR1_0 */
3124 case 0x8c: /* SDRC_EMR2_0 */
3125 case 0x90: /* SDRC_EMR3_0 */
3126 case 0x94: /* SDRC_DCDL1_CTRL */
3127 case 0x98: /* SDRC_DCDL2_CTRL */
3128 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3129 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3130 case 0xa4: /* SDRC_RFR_CTRL_0 */
3131 case 0xa8: /* SDRC_MANUAL_0 */
3132 case 0xb0: /* SDRC_MCFG_1 */
3133 case 0xb4: /* SDRC_MR_1 */
3134 case 0xb8: /* SDRC_EMR1_1 */
3135 case 0xbc: /* SDRC_EMR2_1 */
3136 case 0xc0: /* SDRC_EMR3_1 */
3137 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3138 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3139 case 0xd4: /* SDRC_RFR_CTRL_1 */
3140 case 0xd8: /* SDRC_MANUAL_1 */
3141 return 0x00;
3142 }
3143
3144 OMAP_BAD_REG(addr);
3145 return 0;
3146 }
3147
3148 static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
3149 uint32_t value)
3150 {
3151 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3152 int offset = addr - s->base;
3153
3154 switch (offset) {
3155 case 0x00: /* SDRC_REVISION */
3156 case 0x14: /* SDRC_SYSSTATUS */
3157 case 0x48: /* SDRC_ERR_ADDR */
3158 case 0x64: /* SDRC_DLLA_STATUS */
3159 case 0x6c: /* SDRC_DLLB_STATUS */
3160 OMAP_RO_REG(addr);
3161 return;
3162
3163 case 0x10: /* SDRC_SYSCONFIG */
3164 if ((value >> 3) != 0x2)
3165 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3166 __FUNCTION__, value >> 3);
3167 if (value & 2)
3168 omap_sdrc_reset(s);
3169 s->config = value & 0x18;
3170 break;
3171
3172 case 0x40: /* SDRC_CS_CFG */
3173 case 0x44: /* SDRC_SHARING */
3174 case 0x4c: /* SDRC_ERR_TYPE */
3175 case 0x60: /* SDRC_DLLA_SCTRL */
3176 case 0x68: /* SDRC_DLLB_CTRL */
3177 case 0x70: /* SDRC_POWER */
3178 case 0x80: /* SDRC_MCFG_0 */
3179 case 0x84: /* SDRC_MR_0 */
3180 case 0x88: /* SDRC_EMR1_0 */
3181 case 0x8c: /* SDRC_EMR2_0 */
3182 case 0x90: /* SDRC_EMR3_0 */
3183 case 0x94: /* SDRC_DCDL1_CTRL */
3184 case 0x98: /* SDRC_DCDL2_CTRL */
3185 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3186 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3187 case 0xa4: /* SDRC_RFR_CTRL_0 */
3188 case 0xa8: /* SDRC_MANUAL_0 */
3189 case 0xb0: /* SDRC_MCFG_1 */
3190 case 0xb4: /* SDRC_MR_1 */
3191 case 0xb8: /* SDRC_EMR1_1 */
3192 case 0xbc: /* SDRC_EMR2_1 */
3193 case 0xc0: /* SDRC_EMR3_1 */
3194 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3195 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3196 case 0xd4: /* SDRC_RFR_CTRL_1 */
3197 case 0xd8: /* SDRC_MANUAL_1 */
3198 break;
3199
3200 default:
3201 OMAP_BAD_REG(addr);
3202 return;
3203 }
3204 }
3205
3206 static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
3207 omap_badwidth_read32,
3208 omap_badwidth_read32,
3209 omap_sdrc_read,
3210 };
3211
3212 static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
3213 omap_badwidth_write32,
3214 omap_badwidth_write32,
3215 omap_sdrc_write,
3216 };
3217
3218 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
3219 {
3220 int iomemtype;
3221 struct omap_sdrc_s *s = (struct omap_sdrc_s *)
3222 qemu_mallocz(sizeof(struct omap_sdrc_s));
3223
3224 s->base = base;
3225 omap_sdrc_reset(s);
3226
3227 iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
3228 omap_sdrc_writefn, s);
3229 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3230
3231 return s;
3232 }
3233
3234 /* General-Purpose Memory Controller */
3235 struct omap_gpmc_s {
3236 target_phys_addr_t base;
3237 qemu_irq irq;
3238
3239 uint8_t sysconfig;
3240 uint16_t irqst;
3241 uint16_t irqen;
3242 uint16_t timeout;
3243 uint16_t config;
3244 uint32_t prefconfig[2];
3245 int prefcontrol;
3246 int preffifo;
3247 int prefcount;
3248 struct omap_gpmc_cs_file_s {
3249 uint32_t config[7];
3250 target_phys_addr_t base;
3251 size_t size;
3252 int iomemtype;
3253 void (*base_update)(void *opaque, target_phys_addr_t new);
3254 void (*unmap)(void *opaque);
3255 void *opaque;
3256 } cs_file[8];
3257 int ecc_cs;
3258 int ecc_ptr;
3259 uint32_t ecc_cfg;
3260 struct ecc_state_s ecc[9];
3261 };
3262
3263 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
3264 {
3265 qemu_set_irq(s->irq, s->irqen & s->irqst);
3266 }
3267
3268 static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
3269 {
3270 /* TODO: check for overlapping regions and report access errors */
3271 if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
3272 (base < 0 || base >= 0x40) ||
3273 (base & 0x0f & ~mask)) {
3274 fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
3275 __FUNCTION__);
3276 return;
3277 }
3278
3279 if (!f->opaque)
3280 return;
3281
3282 f->base = base << 24;
3283 f->size = (0x0fffffff & ~(mask << 24)) + 1;
3284 /* TODO: rather than setting the size of the mapping (which should be
3285 * constant), the mask should cause wrapping of the address space, so
3286 * that the same memory becomes accessible at every <i>size</i> bytes
3287 * starting from <i>base</i>. */
3288 if (f->iomemtype)
3289 cpu_register_physical_memory(f->base, f->size, f->iomemtype);
3290
3291 if (f->base_update)
3292 f->base_update(f->opaque, f->base);
3293 }
3294
3295 static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
3296 {
3297 if (f->size) {
3298 if (f->unmap)
3299 f->unmap(f->opaque);
3300 if (f->iomemtype)
3301 cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
3302 f->base = 0;
3303 f->size = 0;
3304 }
3305 }
3306
3307 static void omap_gpmc_reset(struct omap_gpmc_s *s)
3308 {
3309 int i;
3310
3311 s->sysconfig = 0;
3312 s->irqst = 0;
3313 s->irqen = 0;
3314 omap_gpmc_int_update(s);
3315 s->timeout = 0;
3316 s->config = 0xa00;
3317 s->prefconfig[0] = 0x00004000;
3318 s->prefconfig[1] = 0x00000000;
3319 s->prefcontrol = 0;
3320 s->preffifo = 0;
3321 s->prefcount = 0;
3322 for (i = 0; i < 8; i ++) {
3323 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
3324 omap_gpmc_cs_unmap(s->cs_file + i);
3325 s->cs_file[i].config[0] = i ? 1 << 12 : 0;
3326 s->cs_file[i].config[1] = 0x101001;
3327 s->cs_file[i].config[2] = 0x020201;
3328 s->cs_file[i].config[3] = 0x10031003;
3329 s->cs_file[i].config[4] = 0x10f1111;
3330 s->cs_file[i].config[5] = 0;
3331 s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
3332 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
3333 omap_gpmc_cs_map(&s->cs_file[i],
3334 s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
3335 (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
3336 }
3337 omap_gpmc_cs_map(s->cs_file, 0, 0xf);
3338 s->ecc_cs = 0;
3339 s->ecc_ptr = 0;
3340 s->ecc_cfg = 0x3fcff000;
3341 for (i = 0; i < 9; i ++)
3342 ecc_reset(&s->ecc[i]);
3343 }
3344
3345 static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
3346 {
3347 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
3348 int offset = addr - s->base;
3349 int cs;
3350 struct omap_gpmc_cs_file_s *f;
3351
3352 switch (offset) {
3353 case 0x000: /* GPMC_REVISION */
3354 return 0x20;
3355
3356 case 0x010: /* GPMC_SYSCONFIG */
3357 return s->sysconfig;
3358
3359 case 0x014: /* GPMC_SYSSTATUS */
3360 return 1; /* RESETDONE */
3361
3362 case 0x018: /* GPMC_IRQSTATUS */
3363 return s->irqst;
3364
3365 case 0x01c: /* GPMC_IRQENABLE */
3366 return s->irqen;
3367
3368 case 0x040: /* GPMC_TIMEOUT_CONTROL */
3369 return s->timeout;
3370
3371 case 0x044: /* GPMC_ERR_ADDRESS */
3372 case 0x048: /* GPMC_ERR_TYPE */
3373 return 0;
3374
3375 case 0x050: /* GPMC_CONFIG */
3376 return s->config;
3377
3378 case 0x054: /* GPMC_STATUS */
3379 return 0x001;
3380
3381 case 0x060 ... 0x1d4:
3382 cs = (offset - 0x060) / 0x30;
3383 offset -= cs * 0x30;
3384 f = s->cs_file + cs;
3385 switch (offset - cs * 0x30) {
3386 case 0x60: /* GPMC_CONFIG1 */
3387 return f->config[0];
3388 case 0x64: /* GPMC_CONFIG2 */
3389 return f->config[1];
3390 case 0x68: /* GPMC_CONFIG3 */
3391 return f->config[2];
3392 case 0x6c: /* GPMC_CONFIG4 */
3393 return f->config[3];
3394 case 0x70: /* GPMC_CONFIG5 */
3395 return f->config[4];
3396 case 0x74: /* GPMC_CONFIG6 */
3397 return f->config[5];
3398 case 0x78: /* GPMC_CONFIG7 */
3399 return f->config[6];
3400 case 0x84: /* GPMC_NAND_DATA */
3401 return 0;
3402 }
3403 break;
3404
3405 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
3406 return s->prefconfig[0];
3407 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
3408 return s->prefconfig[1];
3409 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
3410 return s->prefcontrol;
3411 case 0x1f0: /* GPMC_PREFETCH_STATUS */
3412 return (s->preffifo << 24) |
3413 ((s->preffifo >
3414 ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
3415 s->prefcount;
3416
3417 case 0x1f4: /* GPMC_ECC_CONFIG */
3418 return s->ecc_cs;
3419 case 0x1f8: /* GPMC_ECC_CONTROL */
3420 return s->ecc_ptr;
3421 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
3422 return s->ecc_cfg;
3423 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
3424 cs = (offset & 0x1f) >> 2;
3425 /* TODO: check correctness */
3426 return
3427 ((s->ecc[cs].cp & 0x07) << 0) |
3428 ((s->ecc[cs].cp & 0x38) << 13) |
3429 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
3430 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
3431
3432 case 0x230: /* GPMC_TESTMODE_CTRL */
3433 return 0;
3434 case 0x234: /* GPMC_PSA_LSB */
3435 case 0x238: /* GPMC_PSA_MSB */
3436 return 0x00000000;
3437 }
3438
3439 OMAP_BAD_REG(addr);
3440 return 0;
3441 }
3442
3443 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
3444 uint32_t value)
3445 {
3446 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
3447 int offset = addr - s->base;
3448 int cs;
3449 struct omap_gpmc_cs_file_s *f;
3450
3451 switch (offset) {
3452 case 0x000: /* GPMC_REVISION */
3453 case 0x014: /* GPMC_SYSSTATUS */
3454 case 0x054: /* GPMC_STATUS */
3455 case 0x1f0: /* GPMC_PREFETCH_STATUS */
3456 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
3457 case 0x234: /* GPMC_PSA_LSB */
3458 case 0x238: /* GPMC_PSA_MSB */
3459 OMAP_RO_REG(addr);
3460 break;
3461
3462 case 0x010: /* GPMC_SYSCONFIG */
3463 if ((value >> 3) == 0x3)
3464 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3465 __FUNCTION__, value >> 3);
3466 if (value & 2)
3467 omap_gpmc_reset(s);
3468 s->sysconfig = value & 0x19;
3469 break;
3470
3471 case 0x018: /* GPMC_IRQSTATUS */
3472 s->irqen = ~value;
3473 omap_gpmc_int_update(s);
3474 break;
3475
3476 case 0x01c: /* GPMC_IRQENABLE */
3477 s->irqen = value & 0xf03;
3478 omap_gpmc_int_update(s);
3479 break;
3480
3481 case 0x040: /* GPMC_TIMEOUT_CONTROL */
3482 s->timeout = value & 0x1ff1;
3483 break;
3484
3485 case 0x044: /* GPMC_ERR_ADDRESS */
3486 case 0x048: /* GPMC_ERR_TYPE */
3487 break;
3488
3489 case 0x050: /* GPMC_CONFIG */
3490 s->config = value & 0xf13;
3491 break;
3492
3493 case 0x060 ... 0x1d4:
3494 cs = (offset - 0x060) / 0x30;
3495 offset -= cs * 0x30;
3496 f = s->cs_file + cs;
3497 switch (offset) {
3498 case 0x60: /* GPMC_CONFIG1 */
3499 f->config[0] = value & 0xffef3e13;
3500 break;
3501 case 0x64: /* GPMC_CONFIG2 */
3502 f->config[1] = value & 0x001f1f8f;
3503 break;
3504 case 0x68: /* GPMC_CONFIG3 */
3505 f->config[2] = value & 0x001f1f8f;
3506 break;
3507 case 0x6c: /* GPMC_CONFIG4 */
3508 f->config[3] = value & 0x1f8f1f8f;
3509 break;
3510 case 0x70: /* GPMC_CONFIG5 */
3511 f->config[4] = value & 0x0f1f1f1f;
3512 break;
3513 case 0x74: /* GPMC_CONFIG6 */
3514 f->config[5] = value & 0x00000fcf;
3515 break;
3516 case 0x78: /* GPMC_CONFIG7 */
3517 if ((f->config[6] ^ value) & 0xf7f) {
3518 if (f->config[6] & (1 << 6)) /* CSVALID */
3519 omap_gpmc_cs_unmap(f);
3520 if (value & (1 << 6)) /* CSVALID */
3521 omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
3522 (value >> 8 & 0xf)); /* BASEADDR */
3523 }
3524 f->config[6] = value & 0x00000f7f;
3525 break;
3526 case 0x7c: /* GPMC_NAND_COMMAND */
3527 case 0x80: /* GPMC_NAND_ADDRESS */
3528 case 0x84: /* GPMC_NAND_DATA */
3529 break;
3530
3531 default:
3532 goto bad_reg;
3533 }
3534 break;
3535
3536 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
3537 s->prefconfig[0] = value & 0x7f8f7fbf;
3538 /* TODO: update interrupts, fifos, dmas */
3539 break;
3540
3541 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
3542 s->prefconfig[1] = value & 0x3fff;
3543 break;
3544
3545 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
3546 s->prefcontrol = value & 1;
3547 if (s->prefcontrol) {
3548 if (s->prefconfig[0] & 1)
3549 s->preffifo = 0x40;
3550 else
3551 s->preffifo = 0x00;
3552 }
3553 /* TODO: start */
3554 break;
3555
3556 case 0x1f4: /* GPMC_ECC_CONFIG */
3557 s->ecc_cs = 0x8f;
3558 break;
3559 case 0x1f8: /* GPMC_ECC_CONTROL */
3560 if (value & (1 << 8))
3561 for (cs = 0; cs < 9; cs ++)
3562 ecc_reset(&s->ecc[cs]);
3563 s->ecc_ptr = value & 0xf;
3564 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
3565 s->ecc_ptr = 0;
3566 s->ecc_cs &= ~1;
3567 }
3568 break;
3569 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
3570 s->ecc_cfg = value & 0x3fcff1ff;
3571 break;
3572 case 0x230: /* GPMC_TESTMODE_CTRL */
3573 if (value & 7)
3574 fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
3575 break;
3576
3577 default:
3578 bad_reg:
3579 OMAP_BAD_REG(addr);
3580 return;
3581 }
3582 }
3583
3584 static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
3585 omap_badwidth_read32, /* TODO */
3586 omap_badwidth_read32, /* TODO */
3587 omap_gpmc_read,
3588 };
3589
3590 static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
3591 omap_badwidth_write32, /* TODO */
3592 omap_badwidth_write32, /* TODO */
3593 omap_gpmc_write,
3594 };
3595
3596 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
3597 {
3598 int iomemtype;
3599 struct omap_gpmc_s *s = (struct omap_gpmc_s *)
3600 qemu_mallocz(sizeof(struct omap_gpmc_s));
3601
3602 s->base = base;
3603 omap_gpmc_reset(s);
3604
3605 iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
3606 omap_gpmc_writefn, s);
3607 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
3608
3609 return s;
3610 }
3611
3612 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
3613 void (*base_upd)(void *opaque, target_phys_addr_t new),
3614 void (*unmap)(void *opaque), void *opaque)
3615 {
3616 struct omap_gpmc_cs_file_s *f;
3617
3618 if (cs < 0 || cs >= 8) {
3619 fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
3620 exit(-1);
3621 }
3622 f = &s->cs_file[cs];
3623
3624 f->iomemtype = iomemtype;
3625 f->base_update = base_upd;
3626 f->unmap = unmap;
3627 f->opaque = opaque;
3628
3629 if (f->config[6] & (1 << 6)) /* CSVALID */
3630 omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
3631 (f->config[6] >> 8 & 0xf)); /* BASEADDR */
3632 }
3633
3634 /* General chip reset */
3635 static void omap2_mpu_reset(void *opaque)
3636 {
3637 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
3638
3639 omap_inth_reset(mpu->ih[0]);
3640 omap_dma_reset(mpu->dma);
3641 omap_prcm_reset(mpu->prcm);
3642 omap_sysctl_reset(mpu->sysc);
3643 omap_gp_timer_reset(mpu->gptimer[0]);
3644 omap_gp_timer_reset(mpu->gptimer[1]);
3645 omap_gp_timer_reset(mpu->gptimer[2]);
3646 omap_gp_timer_reset(mpu->gptimer[3]);
3647 omap_gp_timer_reset(mpu->gptimer[4]);
3648 omap_gp_timer_reset(mpu->gptimer[5]);
3649 omap_gp_timer_reset(mpu->gptimer[6]);
3650 omap_gp_timer_reset(mpu->gptimer[7]);
3651 omap_gp_timer_reset(mpu->gptimer[8]);
3652 omap_gp_timer_reset(mpu->gptimer[9]);
3653 omap_gp_timer_reset(mpu->gptimer[10]);
3654 omap_gp_timer_reset(mpu->gptimer[11]);
3655 omap_synctimer_reset(&mpu->synctimer);
3656 omap_sdrc_reset(mpu->sdrc);
3657 omap_gpmc_reset(mpu->gpmc);
3658 omap_dss_reset(mpu->dss);
3659 omap_uart_reset(mpu->uart[0]);
3660 omap_uart_reset(mpu->uart[1]);
3661 omap_uart_reset(mpu->uart[2]);
3662 omap_mmc_reset(mpu->mmc);
3663 omap_gpif_reset(mpu->gpif);
3664 omap_mcspi_reset(mpu->mcspi[0]);
3665 omap_mcspi_reset(mpu->mcspi[1]);
3666 omap_i2c_reset(mpu->i2c[0]);
3667 omap_i2c_reset(mpu->i2c[1]);
3668 cpu_reset(mpu->env);
3669 }
3670
3671 static int omap2_validate_addr(struct omap_mpu_state_s *s,
3672 target_phys_addr_t addr)
3673 {
3674 return 1;
3675 }
3676
3677 static const struct dma_irq_map omap2_dma_irq_map[] = {
3678 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
3679 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
3680 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
3681 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
3682 };
3683
3684 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
3685 DisplayState *ds, const char *core)
3686 {
3687 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
3688 qemu_mallocz(sizeof(struct omap_mpu_state_s));
3689 ram_addr_t sram_base, q2_base;
3690 qemu_irq *cpu_irq;
3691 qemu_irq dma_irqs[4];
3692 omap_clk gpio_clks[4];
3693 int sdindex;
3694 int i;
3695
3696 /* Core */
3697 s->mpu_model = omap2420;
3698 s->env = cpu_init(core ?: "arm1136-r2");
3699 if (!s->env) {
3700 fprintf(stderr, "Unable to find CPU definition\n");
3701 exit(1);
3702 }
3703 s->sdram_size = sdram_size;
3704 s->sram_size = OMAP242X_SRAM_SIZE;
3705
3706 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
3707
3708 /* Clocks */
3709 omap_clk_init(s);
3710
3711 /* Memory-mapped stuff */
3712 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
3713 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
3714 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
3715 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
3716
3717 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
3718
3719 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
3720 cpu_irq = arm_pic_init_cpu(s->env);
3721 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
3722 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
3723 omap_findclk(s, "mpu_intc_fclk"),
3724 omap_findclk(s, "mpu_intc_iclk"));
3725
3726 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
3727 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
3728
3729 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
3730 omap_findclk(s, "omapctrl_iclk"), s);
3731
3732 for (i = 0; i < 4; i ++)
3733 dma_irqs[i] =
3734 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
3735 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
3736 omap_findclk(s, "sdma_iclk"),
3737 omap_findclk(s, "sdma_fclk"));
3738 s->port->addr_valid = omap2_validate_addr;
3739
3740 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
3741 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
3742 omap_findclk(s, "uart1_fclk"),
3743 omap_findclk(s, "uart1_iclk"),
3744 s->drq[OMAP24XX_DMA_UART1_TX],
3745 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
3746 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
3747 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
3748 omap_findclk(s, "uart2_fclk"),
3749 omap_findclk(s, "uart2_iclk"),
3750 s->drq[OMAP24XX_DMA_UART2_TX],
3751 s->drq[OMAP24XX_DMA_UART2_RX],
3752 serial_hds[0] ? serial_hds[1] : 0);
3753 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
3754 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
3755 omap_findclk(s, "uart3_fclk"),
3756 omap_findclk(s, "uart3_iclk"),
3757 s->drq[OMAP24XX_DMA_UART3_TX],
3758 s->drq[OMAP24XX_DMA_UART3_RX],
3759 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
3760
3761 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
3762 s->irq[0][OMAP_INT_24XX_GPTIMER1],
3763 omap_findclk(s, "wu_gpt1_clk"),
3764 omap_findclk(s, "wu_l4_iclk"));
3765 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
3766 s->irq[0][OMAP_INT_24XX_GPTIMER2],
3767 omap_findclk(s, "core_gpt2_clk"),
3768 omap_findclk(s, "core_l4_iclk"));
3769 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
3770 s->irq[0][OMAP_INT_24XX_GPTIMER3],
3771 omap_findclk(s, "core_gpt3_clk"),
3772 omap_findclk(s, "core_l4_iclk"));
3773 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
3774 s->irq[0][OMAP_INT_24XX_GPTIMER4],
3775 omap_findclk(s, "core_gpt4_clk"),
3776 omap_findclk(s, "core_l4_iclk"));
3777 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
3778 s->irq[0][OMAP_INT_24XX_GPTIMER5],
3779 omap_findclk(s, "core_gpt5_clk"),
3780 omap_findclk(s, "core_l4_iclk"));
3781 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
3782 s->irq[0][OMAP_INT_24XX_GPTIMER6],
3783 omap_findclk(s, "core_gpt6_clk"),
3784 omap_findclk(s, "core_l4_iclk"));
3785 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
3786 s->irq[0][OMAP_INT_24XX_GPTIMER7],
3787 omap_findclk(s, "core_gpt7_clk"),
3788 omap_findclk(s, "core_l4_iclk"));
3789 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
3790 s->irq[0][OMAP_INT_24XX_GPTIMER8],
3791 omap_findclk(s, "core_gpt8_clk"),
3792 omap_findclk(s, "core_l4_iclk"));
3793 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
3794 s->irq[0][OMAP_INT_24XX_GPTIMER9],
3795 omap_findclk(s, "core_gpt9_clk"),
3796 omap_findclk(s, "core_l4_iclk"));
3797 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
3798 s->irq[0][OMAP_INT_24XX_GPTIMER10],
3799 omap_findclk(s, "core_gpt10_clk"),
3800 omap_findclk(s, "core_l4_iclk"));
3801 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
3802 s->irq[0][OMAP_INT_24XX_GPTIMER11],
3803 omap_findclk(s, "core_gpt11_clk"),
3804 omap_findclk(s, "core_l4_iclk"));
3805 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
3806 s->irq[0][OMAP_INT_24XX_GPTIMER12],
3807 omap_findclk(s, "core_gpt12_clk"),
3808 omap_findclk(s, "core_l4_iclk"));
3809
3810 omap_tap_init(omap_l4ta(s->l4, 2), s);
3811
3812 omap_synctimer_init(omap_l4tao(s->l4, 2), s,
3813 omap_findclk(s, "clk32-kHz"),
3814 omap_findclk(s, "core_l4_iclk"));
3815
3816 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
3817 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
3818 &s->drq[OMAP24XX_DMA_I2C1_TX],
3819 omap_findclk(s, "i2c1.fclk"),
3820 omap_findclk(s, "i2c1.iclk"));
3821 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
3822 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
3823 &s->drq[OMAP24XX_DMA_I2C2_TX],
3824 omap_findclk(s, "i2c2.fclk"),
3825 omap_findclk(s, "i2c2.iclk"));
3826
3827 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
3828 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
3829 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
3830 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
3831 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
3832 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
3833 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
3834
3835 s->sdrc = omap_sdrc_init(0x68009000);
3836 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
3837
3838 sdindex = drive_get_index(IF_SD, 0, 0);
3839 if (sdindex == -1) {
3840 fprintf(stderr, "qemu: missing SecureDigital device\n");
3841 exit(1);
3842 }
3843 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv,
3844 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
3845 &s->drq[OMAP24XX_DMA_MMC1_TX],
3846 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
3847
3848 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
3849 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
3850 &s->drq[OMAP24XX_DMA_SPI1_TX0],
3851 omap_findclk(s, "spi1_fclk"),
3852 omap_findclk(s, "spi1_iclk"));
3853 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
3854 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
3855 &s->drq[OMAP24XX_DMA_SPI2_TX0],
3856 omap_findclk(s, "spi2_fclk"),
3857 omap_findclk(s, "spi2_iclk"));
3858
3859 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds,
3860 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
3861 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
3862 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
3863 omap_findclk(s, "dss_54m_clk"),
3864 omap_findclk(s, "dss_l3_iclk"),
3865 omap_findclk(s, "dss_l4_iclk"));
3866
3867 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
3868 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
3869 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
3870 serial_hds[3] : 0);
3871
3872 /* All register mappings (includin those not currenlty implemented):
3873 * SystemControlMod 48000000 - 48000fff
3874 * SystemControlL4 48001000 - 48001fff
3875 * 32kHz Timer Mod 48004000 - 48004fff
3876 * 32kHz Timer L4 48005000 - 48005fff
3877 * PRCM ModA 48008000 - 480087ff
3878 * PRCM ModB 48008800 - 48008fff
3879 * PRCM L4 48009000 - 48009fff
3880 * TEST-BCM Mod 48012000 - 48012fff
3881 * TEST-BCM L4 48013000 - 48013fff
3882 * TEST-TAP Mod 48014000 - 48014fff
3883 * TEST-TAP L4 48015000 - 48015fff
3884 * GPIO1 Mod 48018000 - 48018fff
3885 * GPIO Top 48019000 - 48019fff
3886 * GPIO2 Mod 4801a000 - 4801afff
3887 * GPIO L4 4801b000 - 4801bfff
3888 * GPIO3 Mod 4801c000 - 4801cfff
3889 * GPIO4 Mod 4801e000 - 4801efff
3890 * WDTIMER1 Mod 48020000 - 48010fff
3891 * WDTIMER Top 48021000 - 48011fff
3892 * WDTIMER2 Mod 48022000 - 48012fff
3893 * WDTIMER L4 48023000 - 48013fff
3894 * WDTIMER3 Mod 48024000 - 48014fff
3895 * WDTIMER3 L4 48025000 - 48015fff
3896 * WDTIMER4 Mod 48026000 - 48016fff
3897 * WDTIMER4 L4 48027000 - 48017fff
3898 * GPTIMER1 Mod 48028000 - 48018fff
3899 * GPTIMER1 L4 48029000 - 48019fff
3900 * GPTIMER2 Mod 4802a000 - 4801afff
3901 * GPTIMER2 L4 4802b000 - 4801bfff
3902 * L4-Config AP 48040000 - 480407ff
3903 * L4-Config IP 48040800 - 48040fff
3904 * L4-Config LA 48041000 - 48041fff
3905 * ARM11ETB Mod 48048000 - 48049fff
3906 * ARM11ETB L4 4804a000 - 4804afff
3907 * DISPLAY Top 48050000 - 480503ff
3908 * DISPLAY DISPC 48050400 - 480507ff
3909 * DISPLAY RFBI 48050800 - 48050bff
3910 * DISPLAY VENC 48050c00 - 48050fff
3911 * DISPLAY L4 48051000 - 48051fff
3912 * CAMERA Top 48052000 - 480523ff
3913 * CAMERA core 48052400 - 480527ff
3914 * CAMERA DMA 48052800 - 48052bff
3915 * CAMERA MMU 48052c00 - 48052fff
3916 * CAMERA L4 48053000 - 48053fff
3917 * SDMA Mod 48056000 - 48056fff
3918 * SDMA L4 48057000 - 48057fff
3919 * SSI Top 48058000 - 48058fff
3920 * SSI GDD 48059000 - 48059fff
3921 * SSI Port1 4805a000 - 4805afff
3922 * SSI Port2 4805b000 - 4805bfff
3923 * SSI L4 4805c000 - 4805cfff
3924 * USB Mod 4805e000 - 480fefff
3925 * USB L4 4805f000 - 480fffff
3926 * WIN_TRACER1 Mod 48060000 - 48060fff
3927 * WIN_TRACER1 L4 48061000 - 48061fff
3928 * WIN_TRACER2 Mod 48062000 - 48062fff
3929 * WIN_TRACER2 L4 48063000 - 48063fff
3930 * WIN_TRACER3 Mod 48064000 - 48064fff
3931 * WIN_TRACER3 L4 48065000 - 48065fff
3932 * WIN_TRACER4 Top 48066000 - 480660ff
3933 * WIN_TRACER4 ETT 48066100 - 480661ff
3934 * WIN_TRACER4 WT 48066200 - 480662ff
3935 * WIN_TRACER4 L4 48067000 - 48067fff
3936 * XTI Mod 48068000 - 48068fff
3937 * XTI L4 48069000 - 48069fff
3938 * UART1 Mod 4806a000 - 4806afff
3939 * UART1 L4 4806b000 - 4806bfff
3940 * UART2 Mod 4806c000 - 4806cfff
3941 * UART2 L4 4806d000 - 4806dfff
3942 * UART3 Mod 4806e000 - 4806efff
3943 * UART3 L4 4806f000 - 4806ffff
3944 * I2C1 Mod 48070000 - 48070fff
3945 * I2C1 L4 48071000 - 48071fff
3946 * I2C2 Mod 48072000 - 48072fff
3947 * I2C2 L4 48073000 - 48073fff
3948 * McBSP1 Mod 48074000 - 48074fff
3949 * McBSP1 L4 48075000 - 48075fff
3950 * McBSP2 Mod 48076000 - 48076fff
3951 * McBSP2 L4 48077000 - 48077fff
3952 * GPTIMER3 Mod 48078000 - 48078fff
3953 * GPTIMER3 L4 48079000 - 48079fff
3954 * GPTIMER4 Mod 4807a000 - 4807afff
3955 * GPTIMER4 L4 4807b000 - 4807bfff
3956 * GPTIMER5 Mod 4807c000 - 4807cfff
3957 * GPTIMER5 L4 4807d000 - 4807dfff
3958 * GPTIMER6 Mod 4807e000 - 4807efff
3959 * GPTIMER6 L4 4807f000 - 4807ffff
3960 * GPTIMER7 Mod 48080000 - 48080fff
3961 * GPTIMER7 L4 48081000 - 48081fff
3962 * GPTIMER8 Mod 48082000 - 48082fff
3963 * GPTIMER8 L4 48083000 - 48083fff
3964 * GPTIMER9 Mod 48084000 - 48084fff
3965 * GPTIMER9 L4 48085000 - 48085fff
3966 * GPTIMER10 Mod 48086000 - 48086fff
3967 * GPTIMER10 L4 48087000 - 48087fff
3968 * GPTIMER11 Mod 48088000 - 48088fff
3969 * GPTIMER11 L4 48089000 - 48089fff
3970 * GPTIMER12 Mod 4808a000 - 4808afff
3971 * GPTIMER12 L4 4808b000 - 4808bfff
3972 * EAC Mod 48090000 - 48090fff
3973 * EAC L4 48091000 - 48091fff
3974 * FAC Mod 48092000 - 48092fff
3975 * FAC L4 48093000 - 48093fff
3976 * MAILBOX Mod 48094000 - 48094fff
3977 * MAILBOX L4 48095000 - 48095fff
3978 * SPI1 Mod 48098000 - 48098fff
3979 * SPI1 L4 48099000 - 48099fff
3980 * SPI2 Mod 4809a000 - 4809afff
3981 * SPI2 L4 4809b000 - 4809bfff
3982 * MMC/SDIO Mod 4809c000 - 4809cfff
3983 * MMC/SDIO L4 4809d000 - 4809dfff
3984 * MS_PRO Mod 4809e000 - 4809efff
3985 * MS_PRO L4 4809f000 - 4809ffff
3986 * RNG Mod 480a0000 - 480a0fff
3987 * RNG L4 480a1000 - 480a1fff
3988 * DES3DES Mod 480a2000 - 480a2fff
3989 * DES3DES L4 480a3000 - 480a3fff
3990 * SHA1MD5 Mod 480a4000 - 480a4fff
3991 * SHA1MD5 L4 480a5000 - 480a5fff
3992 * AES Mod 480a6000 - 480a6fff
3993 * AES L4 480a7000 - 480a7fff
3994 * PKA Mod 480a8000 - 480a9fff
3995 * PKA L4 480aa000 - 480aafff
3996 * MG Mod 480b0000 - 480b0fff
3997 * MG L4 480b1000 - 480b1fff
3998 * HDQ/1-wire Mod 480b2000 - 480b2fff
3999 * HDQ/1-wire L4 480b3000 - 480b3fff
4000 * MPU interrupt 480fe000 - 480fefff
4001 * STI channel base 54000000 - 5400ffff
4002 * IVA RAM 5c000000 - 5c01ffff
4003 * IVA ROM 5c020000 - 5c027fff
4004 * IMG_BUF_A 5c040000 - 5c040fff
4005 * IMG_BUF_B 5c042000 - 5c042fff
4006 * VLCDS 5c048000 - 5c0487ff
4007 * IMX_COEF 5c049000 - 5c04afff
4008 * IMX_CMD 5c051000 - 5c051fff
4009 * VLCDQ 5c053000 - 5c0533ff
4010 * VLCDH 5c054000 - 5c054fff
4011 * SEQ_CMD 5c055000 - 5c055fff
4012 * IMX_REG 5c056000 - 5c0560ff
4013 * VLCD_REG 5c056100 - 5c0561ff
4014 * SEQ_REG 5c056200 - 5c0562ff
4015 * IMG_BUF_REG 5c056300 - 5c0563ff
4016 * SEQIRQ_REG 5c056400 - 5c0564ff
4017 * OCP_REG 5c060000 - 5c060fff
4018 * SYSC_REG 5c070000 - 5c070fff
4019 * MMU_REG 5d000000 - 5d000fff
4020 * sDMA R 68000400 - 680005ff
4021 * sDMA W 68000600 - 680007ff
4022 * Display Control 68000800 - 680009ff
4023 * DSP subsystem 68000a00 - 68000bff
4024 * MPU subsystem 68000c00 - 68000dff
4025 * IVA subsystem 68001000 - 680011ff
4026 * USB 68001200 - 680013ff
4027 * Camera 68001400 - 680015ff
4028 * VLYNQ (firewall) 68001800 - 68001bff
4029 * VLYNQ 68001e00 - 68001fff
4030 * SSI 68002000 - 680021ff
4031 * L4 68002400 - 680025ff
4032 * DSP (firewall) 68002800 - 68002bff
4033 * DSP subsystem 68002e00 - 68002fff
4034 * IVA (firewall) 68003000 - 680033ff
4035 * IVA 68003600 - 680037ff
4036 * GFX 68003a00 - 68003bff
4037 * CMDWR emulation 68003c00 - 68003dff
4038 * SMS 68004000 - 680041ff
4039 * OCM 68004200 - 680043ff
4040 * GPMC 68004400 - 680045ff
4041 * RAM (firewall) 68005000 - 680053ff
4042 * RAM (err login) 68005400 - 680057ff
4043 * ROM (firewall) 68005800 - 68005bff
4044 * ROM (err login) 68005c00 - 68005fff
4045 * GPMC (firewall) 68006000 - 680063ff
4046 * GPMC (err login) 68006400 - 680067ff
4047 * SMS (err login) 68006c00 - 68006fff
4048 * SMS registers 68008000 - 68008fff
4049 * SDRC registers 68009000 - 68009fff
4050 * GPMC registers 6800a000 6800afff
4051 */
4052
4053 qemu_register_reset(omap2_mpu_reset, s);
4054
4055 return s;
4056 }
Qemu copy for testing