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Add basic OMAP2 chip support.
[qemu.git] / hw / omap_dma.c
1 /*
2 * TI OMAP DMA gigacell.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22 #include "qemu-common.h"
23 #include "qemu-timer.h"
24 #include "omap.h"
25 #include "irq.h"
26
27 struct omap_dma_channel_s {
28 /* transfer data */
29 int burst[2];
30 int pack[2];
31 int endian[2];
32 int endian_lock[2];
33 int translate[2];
34 enum omap_dma_port port[2];
35 target_phys_addr_t addr[2];
36 omap_dma_addressing_t mode[2];
37 uint32_t elements;
38 uint16_t frames;
39 int32_t frame_index[2];
40 int16_t element_index[2];
41 int data_type;
42
43 /* transfer type */
44 int transparent_copy;
45 int constant_fill;
46 uint32_t color;
47 int prefetch;
48
49 /* auto init and linked channel data */
50 int end_prog;
51 int repeat;
52 int auto_init;
53 int link_enabled;
54 int link_next_ch;
55
56 /* interruption data */
57 int interrupts;
58 int status;
59 int cstatus;
60
61 /* state data */
62 int active;
63 int enable;
64 int sync;
65 int src_sync;
66 int pending_request;
67 int waiting_end_prog;
68 uint16_t cpc;
69
70 /* sync type */
71 int fs;
72 int bs;
73
74 /* compatibility */
75 int omap_3_1_compatible_disable;
76
77 qemu_irq irq;
78 struct omap_dma_channel_s *sibling;
79
80 struct omap_dma_reg_set_s {
81 target_phys_addr_t src, dest;
82 int frame;
83 int element;
84 int pck_element;
85 int frame_delta[2];
86 int elem_delta[2];
87 int frames;
88 int elements;
89 int pck_elements;
90 } active_set;
91
92 /* unused parameters */
93 int write_mode;
94 int priority;
95 int interleave_disabled;
96 int type;
97 int suspend;
98 int buf_disable;
99 };
100
101 struct omap_dma_s {
102 QEMUTimer *tm;
103 struct omap_mpu_state_s *mpu;
104 target_phys_addr_t base;
105 omap_clk clk;
106 int64_t delay;
107 uint64_t drq;
108 qemu_irq irq[4];
109 void (*intr_update)(struct omap_dma_s *s);
110 enum omap_dma_model model;
111 int omap_3_1_mapping_disabled;
112
113 uint32_t gcr;
114 uint32_t ocp;
115 uint32_t caps[5];
116 uint32_t irqen[4];
117 uint32_t irqstat[4];
118 int run_count;
119
120 int chans;
121 struct omap_dma_channel_s ch[32];
122 struct omap_dma_lcd_channel_s lcd_ch;
123 };
124
125 /* Interrupts */
126 #define TIMEOUT_INTR (1 << 0)
127 #define EVENT_DROP_INTR (1 << 1)
128 #define HALF_FRAME_INTR (1 << 2)
129 #define END_FRAME_INTR (1 << 3)
130 #define LAST_FRAME_INTR (1 << 4)
131 #define END_BLOCK_INTR (1 << 5)
132 #define SYNC (1 << 6)
133 #define END_PKT_INTR (1 << 7)
134 #define TRANS_ERR_INTR (1 << 8)
135 #define MISALIGN_INTR (1 << 11)
136
137 static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
138 {
139 return s->intr_update(s);
140 }
141
142 static void omap_dma_channel_load(struct omap_dma_s *s,
143 struct omap_dma_channel_s *ch)
144 {
145 struct omap_dma_reg_set_s *a = &ch->active_set;
146 int i;
147 int omap_3_1 = !ch->omap_3_1_compatible_disable;
148
149 /*
150 * TODO: verify address ranges and alignment
151 * TODO: port endianness
152 */
153
154 a->src = ch->addr[0];
155 a->dest = ch->addr[1];
156 a->frames = ch->frames;
157 a->elements = ch->elements;
158 a->pck_elements = ch->frame_index[!ch->src_sync];
159 a->frame = 0;
160 a->element = 0;
161 a->pck_element = 0;
162
163 if (unlikely(!ch->elements || !ch->frames)) {
164 printf("%s: bad DMA request\n", __FUNCTION__);
165 return;
166 }
167
168 for (i = 0; i < 2; i ++)
169 switch (ch->mode[i]) {
170 case constant:
171 a->elem_delta[i] = 0;
172 a->frame_delta[i] = 0;
173 break;
174 case post_incremented:
175 a->elem_delta[i] = ch->data_type;
176 a->frame_delta[i] = 0;
177 break;
178 case single_index:
179 a->elem_delta[i] = ch->data_type +
180 ch->element_index[omap_3_1 ? 0 : i] - 1;
181 a->frame_delta[i] = 0;
182 break;
183 case double_index:
184 a->elem_delta[i] = ch->data_type +
185 ch->element_index[omap_3_1 ? 0 : i] - 1;
186 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
187 ch->element_index[omap_3_1 ? 0 : i];
188 break;
189 default:
190 break;
191 }
192 }
193
194 static void omap_dma_activate_channel(struct omap_dma_s *s,
195 struct omap_dma_channel_s *ch)
196 {
197 if (!ch->active) {
198 ch->active = 1;
199 if (ch->sync)
200 ch->status |= SYNC;
201 s->run_count ++;
202 }
203
204 if (s->delay && !qemu_timer_pending(s->tm))
205 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
206 }
207
208 static void omap_dma_deactivate_channel(struct omap_dma_s *s,
209 struct omap_dma_channel_s *ch)
210 {
211 /* Update cpc */
212 ch->cpc = ch->active_set.dest & 0xffff;
213
214 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
215 /* Don't deactivate the channel */
216 ch->pending_request = 0;
217 return;
218 }
219
220 /* Don't deactive the channel if it is synchronized and the DMA request is
221 active */
222 if (ch->sync && ch->enable && (s->drq & (1 << ch->sync)))
223 return;
224
225 if (ch->active) {
226 ch->active = 0;
227 ch->status &= ~SYNC;
228 s->run_count --;
229 }
230
231 if (!s->run_count)
232 qemu_del_timer(s->tm);
233 }
234
235 static void omap_dma_enable_channel(struct omap_dma_s *s,
236 struct omap_dma_channel_s *ch)
237 {
238 if (!ch->enable) {
239 ch->enable = 1;
240 ch->waiting_end_prog = 0;
241 omap_dma_channel_load(s, ch);
242 /* TODO: theoretically if ch->sync && ch->prefetch &&
243 * !s->drq[ch->sync], we should also activate and fetch from source
244 * and then stall until signalled. */
245 if ((!ch->sync) || (s->drq & (1 << ch->sync)))
246 omap_dma_activate_channel(s, ch);
247 }
248 }
249
250 static void omap_dma_disable_channel(struct omap_dma_s *s,
251 struct omap_dma_channel_s *ch)
252 {
253 if (ch->enable) {
254 ch->enable = 0;
255 /* Discard any pending request */
256 ch->pending_request = 0;
257 omap_dma_deactivate_channel(s, ch);
258 }
259 }
260
261 static void omap_dma_channel_end_prog(struct omap_dma_s *s,
262 struct omap_dma_channel_s *ch)
263 {
264 if (ch->waiting_end_prog) {
265 ch->waiting_end_prog = 0;
266 if (!ch->sync || ch->pending_request) {
267 ch->pending_request = 0;
268 omap_dma_activate_channel(s, ch);
269 }
270 }
271 }
272
273 static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
274 {
275 struct omap_dma_channel_s *ch = s->ch;
276
277 /* First three interrupts are shared between two channels each. */
278 if (ch[0].status | ch[6].status)
279 qemu_irq_raise(ch[0].irq);
280 if (ch[1].status | ch[7].status)
281 qemu_irq_raise(ch[1].irq);
282 if (ch[2].status | ch[8].status)
283 qemu_irq_raise(ch[2].irq);
284 if (ch[3].status)
285 qemu_irq_raise(ch[3].irq);
286 if (ch[4].status)
287 qemu_irq_raise(ch[4].irq);
288 if (ch[5].status)
289 qemu_irq_raise(ch[5].irq);
290 }
291
292 static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
293 {
294 struct omap_dma_channel_s *ch = s->ch;
295 int i;
296
297 for (i = s->chans; i; ch ++, i --)
298 if (ch->status)
299 qemu_irq_raise(ch->irq);
300 }
301
302 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
303 {
304 s->omap_3_1_mapping_disabled = 0;
305 s->chans = 9;
306 s->intr_update = omap_dma_interrupts_3_1_update;
307 }
308
309 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
310 {
311 s->omap_3_1_mapping_disabled = 1;
312 s->chans = 16;
313 s->intr_update = omap_dma_interrupts_3_2_update;
314 }
315
316 static void omap_dma_process_request(struct omap_dma_s *s, int request)
317 {
318 int channel;
319 int drop_event = 0;
320 struct omap_dma_channel_s *ch = s->ch;
321
322 for (channel = 0; channel < s->chans; channel ++, ch ++) {
323 if (ch->enable && ch->sync == request) {
324 if (!ch->active)
325 omap_dma_activate_channel(s, ch);
326 else if (!ch->pending_request)
327 ch->pending_request = 1;
328 else {
329 /* Request collision */
330 /* Second request received while processing other request */
331 ch->status |= EVENT_DROP_INTR;
332 drop_event = 1;
333 }
334 }
335 }
336
337 if (drop_event)
338 omap_dma_interrupts_update(s);
339 }
340
341 static void omap_dma_channel_run(struct omap_dma_s *s)
342 {
343 int n = s->chans;
344 uint16_t status;
345 uint8_t value[4];
346 struct omap_dma_port_if_s *src_p, *dest_p;
347 struct omap_dma_reg_set_s *a;
348 struct omap_dma_channel_s *ch;
349
350 for (ch = s->ch; n; n --, ch ++) {
351 if (!ch->active)
352 continue;
353
354 a = &ch->active_set;
355
356 src_p = &s->mpu->port[ch->port[0]];
357 dest_p = &s->mpu->port[ch->port[1]];
358 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
359 (!dest_p->addr_valid(s->mpu, a->dest))) {
360 #if 0
361 /* Bus time-out */
362 if (ch->interrupts & TIMEOUT_INTR)
363 ch->status |= TIMEOUT_INTR;
364 omap_dma_deactivate_channel(s, ch);
365 continue;
366 #endif
367 printf("%s: Bus time-out in DMA%i operation\n",
368 __FUNCTION__, s->chans - n);
369 }
370
371 status = ch->status;
372 while (status == ch->status && ch->active) {
373 /* Transfer a single element */
374 /* FIXME: check the endianness */
375 if (!ch->constant_fill)
376 cpu_physical_memory_read(a->src, value, ch->data_type);
377 else
378 *(uint32_t *) value = ch->color;
379
380 if (!ch->transparent_copy ||
381 *(uint32_t *) value != ch->color)
382 cpu_physical_memory_write(a->dest, value, ch->data_type);
383
384 a->src += a->elem_delta[0];
385 a->dest += a->elem_delta[1];
386 a->element ++;
387
388 /* If the channel is element synchronized, deactivate it */
389 if (ch->sync && !ch->fs && !ch->bs)
390 omap_dma_deactivate_channel(s, ch);
391
392 /* If it is the last frame, set the LAST_FRAME interrupt */
393 if (a->element == 1 && a->frame == a->frames - 1)
394 if (ch->interrupts & LAST_FRAME_INTR)
395 ch->status |= LAST_FRAME_INTR;
396
397 /* If the half of the frame was reached, set the HALF_FRAME
398 interrupt */
399 if (a->element == (a->elements >> 1))
400 if (ch->interrupts & HALF_FRAME_INTR)
401 ch->status |= HALF_FRAME_INTR;
402
403 if (ch->fs && ch->bs) {
404 a->pck_element ++;
405 /* Check if a full packet has beed transferred. */
406 if (a->pck_element == a->pck_elements) {
407 a->pck_element = 0;
408
409 /* Set the END_PKT interrupt */
410 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
411 ch->status |= END_PKT_INTR;
412
413 /* If the channel is packet-synchronized, deactivate it */
414 if (ch->sync)
415 omap_dma_deactivate_channel(s, ch);
416 }
417 }
418
419 if (a->element == a->elements) {
420 /* End of Frame */
421 a->element = 0;
422 a->src += a->frame_delta[0];
423 a->dest += a->frame_delta[1];
424 a->frame ++;
425
426 /* If the channel is frame synchronized, deactivate it */
427 if (ch->sync && ch->fs && !ch->bs)
428 omap_dma_deactivate_channel(s, ch);
429
430 /* If the channel is async, update cpc */
431 if (!ch->sync)
432 ch->cpc = a->dest & 0xffff;
433
434 /* Set the END_FRAME interrupt */
435 if (ch->interrupts & END_FRAME_INTR)
436 ch->status |= END_FRAME_INTR;
437
438 if (a->frame == a->frames) {
439 /* End of Block */
440 /* Disable the channel */
441
442 if (ch->omap_3_1_compatible_disable) {
443 omap_dma_disable_channel(s, ch);
444 if (ch->link_enabled)
445 omap_dma_enable_channel(s,
446 &s->ch[ch->link_next_ch]);
447 } else {
448 if (!ch->auto_init)
449 omap_dma_disable_channel(s, ch);
450 else if (ch->repeat || ch->end_prog)
451 omap_dma_channel_load(s, ch);
452 else {
453 ch->waiting_end_prog = 1;
454 omap_dma_deactivate_channel(s, ch);
455 }
456 }
457
458 if (ch->interrupts & END_BLOCK_INTR)
459 ch->status |= END_BLOCK_INTR;
460 }
461 }
462 }
463 }
464
465 omap_dma_interrupts_update(s);
466 if (s->run_count && s->delay)
467 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
468 }
469
470 void omap_dma_reset(struct omap_dma_s *s)
471 {
472 int i;
473
474 qemu_del_timer(s->tm);
475 if (s->model < omap_dma_4)
476 s->gcr = 0x0004;
477 else
478 s->gcr = 0x00010010;
479 s->ocp = 0x00000000;
480 memset(&s->irqstat, 0, sizeof(s->irqstat));
481 memset(&s->irqen, 0, sizeof(s->irqen));
482 s->drq = 0x00000000;
483 s->run_count = 0;
484 s->lcd_ch.src = emiff;
485 s->lcd_ch.condition = 0;
486 s->lcd_ch.interrupts = 0;
487 s->lcd_ch.dual = 0;
488 if (s->model < omap_dma_4)
489 omap_dma_enable_3_1_mapping(s);
490 for (i = 0; i < s->chans; i ++) {
491 s->ch[i].suspend = 0;
492 s->ch[i].prefetch = 0;
493 s->ch[i].buf_disable = 0;
494 s->ch[i].src_sync = 0;
495 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
496 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
497 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
498 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
499 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
500 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
501 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
502 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
503 s->ch[i].write_mode = 0;
504 s->ch[i].data_type = 0;
505 s->ch[i].transparent_copy = 0;
506 s->ch[i].constant_fill = 0;
507 s->ch[i].color = 0x00000000;
508 s->ch[i].end_prog = 0;
509 s->ch[i].repeat = 0;
510 s->ch[i].auto_init = 0;
511 s->ch[i].link_enabled = 0;
512 if (s->model < omap_dma_4)
513 s->ch[i].interrupts = 0x0003;
514 else
515 s->ch[i].interrupts = 0x0000;
516 s->ch[i].status = 0;
517 s->ch[i].cstatus = 0;
518 s->ch[i].active = 0;
519 s->ch[i].enable = 0;
520 s->ch[i].sync = 0;
521 s->ch[i].pending_request = 0;
522 s->ch[i].waiting_end_prog = 0;
523 s->ch[i].cpc = 0x0000;
524 s->ch[i].fs = 0;
525 s->ch[i].bs = 0;
526 s->ch[i].omap_3_1_compatible_disable = 0;
527 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
528 s->ch[i].priority = 0;
529 s->ch[i].interleave_disabled = 0;
530 s->ch[i].type = 0;
531 }
532 }
533
534 static int omap_dma_ch_reg_read(struct omap_dma_s *s,
535 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
536 {
537 switch (reg) {
538 case 0x00: /* SYS_DMA_CSDP_CH0 */
539 *value = (ch->burst[1] << 14) |
540 (ch->pack[1] << 13) |
541 (ch->port[1] << 9) |
542 (ch->burst[0] << 7) |
543 (ch->pack[0] << 6) |
544 (ch->port[0] << 2) |
545 (ch->data_type >> 1);
546 break;
547
548 case 0x02: /* SYS_DMA_CCR_CH0 */
549 if (s->model <= omap_dma_3_1)
550 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
551 else
552 *value = ch->omap_3_1_compatible_disable << 10;
553 *value |= (ch->mode[1] << 14) |
554 (ch->mode[0] << 12) |
555 (ch->end_prog << 11) |
556 (ch->repeat << 9) |
557 (ch->auto_init << 8) |
558 (ch->enable << 7) |
559 (ch->priority << 6) |
560 (ch->fs << 5) | ch->sync;
561 break;
562
563 case 0x04: /* SYS_DMA_CICR_CH0 */
564 *value = ch->interrupts;
565 break;
566
567 case 0x06: /* SYS_DMA_CSR_CH0 */
568 *value = ch->status;
569 ch->status &= SYNC;
570 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
571 *value |= (ch->sibling->status & 0x3f) << 6;
572 ch->sibling->status &= SYNC;
573 }
574 qemu_irq_lower(ch->irq);
575 break;
576
577 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
578 *value = ch->addr[0] & 0x0000ffff;
579 break;
580
581 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
582 *value = ch->addr[0] >> 16;
583 break;
584
585 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
586 *value = ch->addr[1] & 0x0000ffff;
587 break;
588
589 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
590 *value = ch->addr[1] >> 16;
591 break;
592
593 case 0x10: /* SYS_DMA_CEN_CH0 */
594 *value = ch->elements;
595 break;
596
597 case 0x12: /* SYS_DMA_CFN_CH0 */
598 *value = ch->frames;
599 break;
600
601 case 0x14: /* SYS_DMA_CFI_CH0 */
602 *value = ch->frame_index[0];
603 break;
604
605 case 0x16: /* SYS_DMA_CEI_CH0 */
606 *value = ch->element_index[0];
607 break;
608
609 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
610 if (ch->omap_3_1_compatible_disable)
611 *value = ch->active_set.src & 0xffff; /* CSAC */
612 else
613 *value = ch->cpc;
614 break;
615
616 case 0x1a: /* DMA_CDAC */
617 *value = ch->active_set.dest & 0xffff; /* CDAC */
618 break;
619
620 case 0x1c: /* DMA_CDEI */
621 *value = ch->element_index[1];
622 break;
623
624 case 0x1e: /* DMA_CDFI */
625 *value = ch->frame_index[1];
626 break;
627
628 case 0x20: /* DMA_COLOR_L */
629 *value = ch->color & 0xffff;
630 break;
631
632 case 0x22: /* DMA_COLOR_U */
633 *value = ch->color >> 16;
634 break;
635
636 case 0x24: /* DMA_CCR2 */
637 *value = (ch->bs << 2) |
638 (ch->transparent_copy << 1) |
639 ch->constant_fill;
640 break;
641
642 case 0x28: /* DMA_CLNK_CTRL */
643 *value = (ch->link_enabled << 15) |
644 (ch->link_next_ch & 0xf);
645 break;
646
647 case 0x2a: /* DMA_LCH_CTRL */
648 *value = (ch->interleave_disabled << 15) |
649 ch->type;
650 break;
651
652 default:
653 return 1;
654 }
655 return 0;
656 }
657
658 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
659 struct omap_dma_channel_s *ch, int reg, uint16_t value)
660 {
661 switch (reg) {
662 case 0x00: /* SYS_DMA_CSDP_CH0 */
663 ch->burst[1] = (value & 0xc000) >> 14;
664 ch->pack[1] = (value & 0x2000) >> 13;
665 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
666 ch->burst[0] = (value & 0x0180) >> 7;
667 ch->pack[0] = (value & 0x0040) >> 6;
668 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
669 ch->data_type = 1 << (value & 3);
670 if (ch->port[0] >= __omap_dma_port_last)
671 printf("%s: invalid DMA port %i\n", __FUNCTION__,
672 ch->port[0]);
673 if (ch->port[1] >= __omap_dma_port_last)
674 printf("%s: invalid DMA port %i\n", __FUNCTION__,
675 ch->port[1]);
676 if ((value & 3) == 3)
677 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
678 break;
679
680 case 0x02: /* SYS_DMA_CCR_CH0 */
681 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
682 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
683 ch->end_prog = (value & 0x0800) >> 11;
684 if (s->model >= omap_dma_3_2)
685 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
686 ch->repeat = (value & 0x0200) >> 9;
687 ch->auto_init = (value & 0x0100) >> 8;
688 ch->priority = (value & 0x0040) >> 6;
689 ch->fs = (value & 0x0020) >> 5;
690 ch->sync = value & 0x001f;
691
692 if (value & 0x0080)
693 omap_dma_enable_channel(s, ch);
694 else
695 omap_dma_disable_channel(s, ch);
696
697 if (ch->end_prog)
698 omap_dma_channel_end_prog(s, ch);
699
700 break;
701
702 case 0x04: /* SYS_DMA_CICR_CH0 */
703 ch->interrupts = value & 0x3f;
704 break;
705
706 case 0x06: /* SYS_DMA_CSR_CH0 */
707 OMAP_RO_REG((target_phys_addr_t) reg);
708 break;
709
710 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
711 ch->addr[0] &= 0xffff0000;
712 ch->addr[0] |= value;
713 break;
714
715 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
716 ch->addr[0] &= 0x0000ffff;
717 ch->addr[0] |= (uint32_t) value << 16;
718 break;
719
720 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
721 ch->addr[1] &= 0xffff0000;
722 ch->addr[1] |= value;
723 break;
724
725 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
726 ch->addr[1] &= 0x0000ffff;
727 ch->addr[1] |= (uint32_t) value << 16;
728 break;
729
730 case 0x10: /* SYS_DMA_CEN_CH0 */
731 ch->elements = value;
732 break;
733
734 case 0x12: /* SYS_DMA_CFN_CH0 */
735 ch->frames = value;
736 break;
737
738 case 0x14: /* SYS_DMA_CFI_CH0 */
739 ch->frame_index[0] = (int16_t) value;
740 break;
741
742 case 0x16: /* SYS_DMA_CEI_CH0 */
743 ch->element_index[0] = (int16_t) value;
744 break;
745
746 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
747 OMAP_RO_REG((target_phys_addr_t) reg);
748 break;
749
750 case 0x1c: /* DMA_CDEI */
751 ch->element_index[1] = (int16_t) value;
752 break;
753
754 case 0x1e: /* DMA_CDFI */
755 ch->frame_index[1] = (int16_t) value;
756 break;
757
758 case 0x20: /* DMA_COLOR_L */
759 ch->color &= 0xffff0000;
760 ch->color |= value;
761 break;
762
763 case 0x22: /* DMA_COLOR_U */
764 ch->color &= 0xffff;
765 ch->color |= value << 16;
766 break;
767
768 case 0x24: /* DMA_CCR2 */
769 ch->bs = (value >> 2) & 0x1;
770 ch->transparent_copy = (value >> 1) & 0x1;
771 ch->constant_fill = value & 0x1;
772 break;
773
774 case 0x28: /* DMA_CLNK_CTRL */
775 ch->link_enabled = (value >> 15) & 0x1;
776 if (value & (1 << 14)) { /* Stop_Lnk */
777 ch->link_enabled = 0;
778 omap_dma_disable_channel(s, ch);
779 }
780 ch->link_next_ch = value & 0x1f;
781 break;
782
783 case 0x2a: /* DMA_LCH_CTRL */
784 ch->interleave_disabled = (value >> 15) & 0x1;
785 ch->type = value & 0xf;
786 break;
787
788 default:
789 return 1;
790 }
791 return 0;
792 }
793
794 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
795 uint16_t value)
796 {
797 switch (offset) {
798 case 0xbc0: /* DMA_LCD_CSDP */
799 s->brust_f2 = (value >> 14) & 0x3;
800 s->pack_f2 = (value >> 13) & 0x1;
801 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
802 s->brust_f1 = (value >> 7) & 0x3;
803 s->pack_f1 = (value >> 6) & 0x1;
804 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
805 break;
806
807 case 0xbc2: /* DMA_LCD_CCR */
808 s->mode_f2 = (value >> 14) & 0x3;
809 s->mode_f1 = (value >> 12) & 0x3;
810 s->end_prog = (value >> 11) & 0x1;
811 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
812 s->repeat = (value >> 9) & 0x1;
813 s->auto_init = (value >> 8) & 0x1;
814 s->running = (value >> 7) & 0x1;
815 s->priority = (value >> 6) & 0x1;
816 s->bs = (value >> 4) & 0x1;
817 break;
818
819 case 0xbc4: /* DMA_LCD_CTRL */
820 s->dst = (value >> 8) & 0x1;
821 s->src = ((value >> 6) & 0x3) << 1;
822 s->condition = 0;
823 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
824 s->interrupts = (value >> 1) & 1;
825 s->dual = value & 1;
826 break;
827
828 case 0xbc8: /* TOP_B1_L */
829 s->src_f1_top &= 0xffff0000;
830 s->src_f1_top |= 0x0000ffff & value;
831 break;
832
833 case 0xbca: /* TOP_B1_U */
834 s->src_f1_top &= 0x0000ffff;
835 s->src_f1_top |= value << 16;
836 break;
837
838 case 0xbcc: /* BOT_B1_L */
839 s->src_f1_bottom &= 0xffff0000;
840 s->src_f1_bottom |= 0x0000ffff & value;
841 break;
842
843 case 0xbce: /* BOT_B1_U */
844 s->src_f1_bottom &= 0x0000ffff;
845 s->src_f1_bottom |= (uint32_t) value << 16;
846 break;
847
848 case 0xbd0: /* TOP_B2_L */
849 s->src_f2_top &= 0xffff0000;
850 s->src_f2_top |= 0x0000ffff & value;
851 break;
852
853 case 0xbd2: /* TOP_B2_U */
854 s->src_f2_top &= 0x0000ffff;
855 s->src_f2_top |= (uint32_t) value << 16;
856 break;
857
858 case 0xbd4: /* BOT_B2_L */
859 s->src_f2_bottom &= 0xffff0000;
860 s->src_f2_bottom |= 0x0000ffff & value;
861 break;
862
863 case 0xbd6: /* BOT_B2_U */
864 s->src_f2_bottom &= 0x0000ffff;
865 s->src_f2_bottom |= (uint32_t) value << 16;
866 break;
867
868 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
869 s->element_index_f1 = value;
870 break;
871
872 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
873 s->frame_index_f1 &= 0xffff0000;
874 s->frame_index_f1 |= 0x0000ffff & value;
875 break;
876
877 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
878 s->frame_index_f1 &= 0x0000ffff;
879 s->frame_index_f1 |= (uint32_t) value << 16;
880 break;
881
882 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
883 s->element_index_f2 = value;
884 break;
885
886 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
887 s->frame_index_f2 &= 0xffff0000;
888 s->frame_index_f2 |= 0x0000ffff & value;
889 break;
890
891 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
892 s->frame_index_f2 &= 0x0000ffff;
893 s->frame_index_f2 |= (uint32_t) value << 16;
894 break;
895
896 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
897 s->elements_f1 = value;
898 break;
899
900 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
901 s->frames_f1 = value;
902 break;
903
904 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
905 s->elements_f2 = value;
906 break;
907
908 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
909 s->frames_f2 = value;
910 break;
911
912 case 0xbea: /* DMA_LCD_LCH_CTRL */
913 s->lch_type = value & 0xf;
914 break;
915
916 default:
917 return 1;
918 }
919 return 0;
920 }
921
922 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
923 uint16_t *ret)
924 {
925 switch (offset) {
926 case 0xbc0: /* DMA_LCD_CSDP */
927 *ret = (s->brust_f2 << 14) |
928 (s->pack_f2 << 13) |
929 ((s->data_type_f2 >> 1) << 11) |
930 (s->brust_f1 << 7) |
931 (s->pack_f1 << 6) |
932 ((s->data_type_f1 >> 1) << 0);
933 break;
934
935 case 0xbc2: /* DMA_LCD_CCR */
936 *ret = (s->mode_f2 << 14) |
937 (s->mode_f1 << 12) |
938 (s->end_prog << 11) |
939 (s->omap_3_1_compatible_disable << 10) |
940 (s->repeat << 9) |
941 (s->auto_init << 8) |
942 (s->running << 7) |
943 (s->priority << 6) |
944 (s->bs << 4);
945 break;
946
947 case 0xbc4: /* DMA_LCD_CTRL */
948 qemu_irq_lower(s->irq);
949 *ret = (s->dst << 8) |
950 ((s->src & 0x6) << 5) |
951 (s->condition << 3) |
952 (s->interrupts << 1) |
953 s->dual;
954 break;
955
956 case 0xbc8: /* TOP_B1_L */
957 *ret = s->src_f1_top & 0xffff;
958 break;
959
960 case 0xbca: /* TOP_B1_U */
961 *ret = s->src_f1_top >> 16;
962 break;
963
964 case 0xbcc: /* BOT_B1_L */
965 *ret = s->src_f1_bottom & 0xffff;
966 break;
967
968 case 0xbce: /* BOT_B1_U */
969 *ret = s->src_f1_bottom >> 16;
970 break;
971
972 case 0xbd0: /* TOP_B2_L */
973 *ret = s->src_f2_top & 0xffff;
974 break;
975
976 case 0xbd2: /* TOP_B2_U */
977 *ret = s->src_f2_top >> 16;
978 break;
979
980 case 0xbd4: /* BOT_B2_L */
981 *ret = s->src_f2_bottom & 0xffff;
982 break;
983
984 case 0xbd6: /* BOT_B2_U */
985 *ret = s->src_f2_bottom >> 16;
986 break;
987
988 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
989 *ret = s->element_index_f1;
990 break;
991
992 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
993 *ret = s->frame_index_f1 & 0xffff;
994 break;
995
996 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
997 *ret = s->frame_index_f1 >> 16;
998 break;
999
1000 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1001 *ret = s->element_index_f2;
1002 break;
1003
1004 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1005 *ret = s->frame_index_f2 & 0xffff;
1006 break;
1007
1008 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1009 *ret = s->frame_index_f2 >> 16;
1010 break;
1011
1012 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1013 *ret = s->elements_f1;
1014 break;
1015
1016 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1017 *ret = s->frames_f1;
1018 break;
1019
1020 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1021 *ret = s->elements_f2;
1022 break;
1023
1024 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1025 *ret = s->frames_f2;
1026 break;
1027
1028 case 0xbea: /* DMA_LCD_LCH_CTRL */
1029 *ret = s->lch_type;
1030 break;
1031
1032 default:
1033 return 1;
1034 }
1035 return 0;
1036 }
1037
1038 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1039 uint16_t value)
1040 {
1041 switch (offset) {
1042 case 0x300: /* SYS_DMA_LCD_CTRL */
1043 s->src = (value & 0x40) ? imif : emiff;
1044 s->condition = 0;
1045 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1046 s->interrupts = (value >> 1) & 1;
1047 s->dual = value & 1;
1048 break;
1049
1050 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1051 s->src_f1_top &= 0xffff0000;
1052 s->src_f1_top |= 0x0000ffff & value;
1053 break;
1054
1055 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1056 s->src_f1_top &= 0x0000ffff;
1057 s->src_f1_top |= value << 16;
1058 break;
1059
1060 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1061 s->src_f1_bottom &= 0xffff0000;
1062 s->src_f1_bottom |= 0x0000ffff & value;
1063 break;
1064
1065 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1066 s->src_f1_bottom &= 0x0000ffff;
1067 s->src_f1_bottom |= value << 16;
1068 break;
1069
1070 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1071 s->src_f2_top &= 0xffff0000;
1072 s->src_f2_top |= 0x0000ffff & value;
1073 break;
1074
1075 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1076 s->src_f2_top &= 0x0000ffff;
1077 s->src_f2_top |= value << 16;
1078 break;
1079
1080 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1081 s->src_f2_bottom &= 0xffff0000;
1082 s->src_f2_bottom |= 0x0000ffff & value;
1083 break;
1084
1085 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1086 s->src_f2_bottom &= 0x0000ffff;
1087 s->src_f2_bottom |= value << 16;
1088 break;
1089
1090 default:
1091 return 1;
1092 }
1093 return 0;
1094 }
1095
1096 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1097 uint16_t *ret)
1098 {
1099 int i;
1100
1101 switch (offset) {
1102 case 0x300: /* SYS_DMA_LCD_CTRL */
1103 i = s->condition;
1104 s->condition = 0;
1105 qemu_irq_lower(s->irq);
1106 *ret = ((s->src == imif) << 6) | (i << 3) |
1107 (s->interrupts << 1) | s->dual;
1108 break;
1109
1110 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1111 *ret = s->src_f1_top & 0xffff;
1112 break;
1113
1114 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1115 *ret = s->src_f1_top >> 16;
1116 break;
1117
1118 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1119 *ret = s->src_f1_bottom & 0xffff;
1120 break;
1121
1122 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1123 *ret = s->src_f1_bottom >> 16;
1124 break;
1125
1126 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1127 *ret = s->src_f2_top & 0xffff;
1128 break;
1129
1130 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1131 *ret = s->src_f2_top >> 16;
1132 break;
1133
1134 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1135 *ret = s->src_f2_bottom & 0xffff;
1136 break;
1137
1138 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1139 *ret = s->src_f2_bottom >> 16;
1140 break;
1141
1142 default:
1143 return 1;
1144 }
1145 return 0;
1146 }
1147
1148 static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1149 {
1150 switch (offset) {
1151 case 0x400: /* SYS_DMA_GCR */
1152 s->gcr = value;
1153 break;
1154
1155 case 0x404: /* DMA_GSCR */
1156 if (value & 0x8)
1157 omap_dma_disable_3_1_mapping(s);
1158 else
1159 omap_dma_enable_3_1_mapping(s);
1160 break;
1161
1162 case 0x408: /* DMA_GRST */
1163 if (value & 0x1)
1164 omap_dma_reset(s);
1165 break;
1166
1167 default:
1168 return 1;
1169 }
1170 return 0;
1171 }
1172
1173 static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1174 uint16_t *ret)
1175 {
1176 switch (offset) {
1177 case 0x400: /* SYS_DMA_GCR */
1178 *ret = s->gcr;
1179 break;
1180
1181 case 0x404: /* DMA_GSCR */
1182 *ret = s->omap_3_1_mapping_disabled << 3;
1183 break;
1184
1185 case 0x408: /* DMA_GRST */
1186 *ret = 0;
1187 break;
1188
1189 case 0x442: /* DMA_HW_ID */
1190 case 0x444: /* DMA_PCh2_ID */
1191 case 0x446: /* DMA_PCh0_ID */
1192 case 0x448: /* DMA_PCh1_ID */
1193 case 0x44a: /* DMA_PChG_ID */
1194 case 0x44c: /* DMA_PChD_ID */
1195 *ret = 1;
1196 break;
1197
1198 case 0x44e: /* DMA_CAPS_0_U */
1199 *ret = (s->caps[0] >> 16) & 0xffff;
1200 break;
1201 case 0x450: /* DMA_CAPS_0_L */
1202 *ret = (s->caps[0] >> 0) & 0xffff;
1203 break;
1204
1205 case 0x452: /* DMA_CAPS_1_U */
1206 *ret = (s->caps[1] >> 16) & 0xffff;
1207 break;
1208 case 0x454: /* DMA_CAPS_1_L */
1209 *ret = (s->caps[1] >> 0) & 0xffff;
1210 break;
1211
1212 case 0x456: /* DMA_CAPS_2 */
1213 *ret = s->caps[2];
1214 break;
1215
1216 case 0x458: /* DMA_CAPS_3 */
1217 *ret = s->caps[3];
1218 break;
1219
1220 case 0x45a: /* DMA_CAPS_4 */
1221 *ret = s->caps[4];
1222 break;
1223
1224 case 0x460: /* DMA_PCh2_SR */
1225 case 0x480: /* DMA_PCh0_SR */
1226 case 0x482: /* DMA_PCh1_SR */
1227 case 0x4c0: /* DMA_PChD_SR_0 */
1228 printf("%s: Physical Channel Status Registers not implemented.\n",
1229 __FUNCTION__);
1230 *ret = 0xff;
1231 break;
1232
1233 default:
1234 return 1;
1235 }
1236 return 0;
1237 }
1238
1239 static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
1240 {
1241 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1242 int reg, ch, offset = addr - s->base;
1243 uint16_t ret;
1244
1245 switch (offset) {
1246 case 0x300 ... 0x3fe:
1247 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1248 if (omap_dma_3_1_lcd_read(&s->lcd_ch, offset, &ret))
1249 break;
1250 return ret;
1251 }
1252 /* Fall through. */
1253 case 0x000 ... 0x2fe:
1254 reg = offset & 0x3f;
1255 ch = (offset >> 6) & 0x0f;
1256 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1257 break;
1258 return ret;
1259
1260 case 0x404 ... 0x4fe:
1261 if (s->model <= omap_dma_3_1)
1262 break;
1263 /* Fall through. */
1264 case 0x400:
1265 if (omap_dma_sys_read(s, offset, &ret))
1266 break;
1267 return ret;
1268
1269 case 0xb00 ... 0xbfe:
1270 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1271 if (omap_dma_3_2_lcd_read(&s->lcd_ch, offset, &ret))
1272 break;
1273 return ret;
1274 }
1275 break;
1276 }
1277
1278 OMAP_BAD_REG(addr);
1279 return 0;
1280 }
1281
1282 static void omap_dma_write(void *opaque, target_phys_addr_t addr,
1283 uint32_t value)
1284 {
1285 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1286 int reg, ch, offset = addr - s->base;
1287
1288 switch (offset) {
1289 case 0x300 ... 0x3fe:
1290 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1291 if (omap_dma_3_1_lcd_write(&s->lcd_ch, offset, value))
1292 break;
1293 return;
1294 }
1295 /* Fall through. */
1296 case 0x000 ... 0x2fe:
1297 reg = offset & 0x3f;
1298 ch = (offset >> 6) & 0x0f;
1299 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1300 break;
1301 return;
1302
1303 case 0x404 ... 0x4fe:
1304 if (s->model <= omap_dma_3_1)
1305 break;
1306 case 0x400:
1307 /* Fall through. */
1308 if (omap_dma_sys_write(s, offset, value))
1309 break;
1310 return;
1311
1312 case 0xb00 ... 0xbfe:
1313 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1314 if (omap_dma_3_2_lcd_write(&s->lcd_ch, offset, value))
1315 break;
1316 return;
1317 }
1318 break;
1319 }
1320
1321 OMAP_BAD_REG(addr);
1322 }
1323
1324 static CPUReadMemoryFunc *omap_dma_readfn[] = {
1325 omap_badwidth_read16,
1326 omap_dma_read,
1327 omap_badwidth_read16,
1328 };
1329
1330 static CPUWriteMemoryFunc *omap_dma_writefn[] = {
1331 omap_badwidth_write16,
1332 omap_dma_write,
1333 omap_badwidth_write16,
1334 };
1335
1336 static void omap_dma_request(void *opaque, int drq, int req)
1337 {
1338 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1339 /* The request pins are level triggered in QEMU. */
1340 if (req) {
1341 if (~s->drq & (1 << drq)) {
1342 s->drq |= 1 << drq;
1343 omap_dma_process_request(s, drq);
1344 }
1345 } else
1346 s->drq &= ~(1 << drq);
1347 }
1348
1349 static void omap_dma_clk_update(void *opaque, int line, int on)
1350 {
1351 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1352
1353 if (on) {
1354 /* TODO: make a clever calculation */
1355 s->delay = ticks_per_sec >> 8;
1356 if (s->run_count)
1357 qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
1358 } else {
1359 s->delay = 0;
1360 qemu_del_timer(s->tm);
1361 }
1362 }
1363
1364 static void omap_dma_setcaps(struct omap_dma_s *s)
1365 {
1366 switch (s->model) {
1367 default:
1368 case omap_dma_3_1:
1369 break;
1370 case omap_dma_3_2:
1371 case omap_dma_4:
1372 /* XXX Only available for sDMA */
1373 s->caps[0] =
1374 (1 << 19) | /* Constant Fill Capability */
1375 (1 << 18); /* Transparent BLT Capability */
1376 s->caps[1] =
1377 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1378 s->caps[2] =
1379 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1380 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1381 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1382 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1383 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1384 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1385 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1386 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1387 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1388 s->caps[3] =
1389 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1390 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1391 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1392 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1393 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1394 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1395 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1396 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1397 s->caps[4] =
1398 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1399 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1400 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1401 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1402 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1403 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1404 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1405 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1406 break;
1407 }
1408 }
1409
1410 struct omap_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1411 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1412 enum omap_dma_model model)
1413 {
1414 int iomemtype, num_irqs, memsize, i;
1415 struct omap_dma_s *s = (struct omap_dma_s *)
1416 qemu_mallocz(sizeof(struct omap_dma_s));
1417
1418 if (model <= omap_dma_3_1) {
1419 num_irqs = 6;
1420 memsize = 0x800;
1421 } else {
1422 num_irqs = 16;
1423 memsize = 0xc00;
1424 }
1425 s->base = base;
1426 s->model = model;
1427 s->mpu = mpu;
1428 s->clk = clk;
1429 s->lcd_ch.irq = lcd_irq;
1430 s->lcd_ch.mpu = mpu;
1431 omap_dma_setcaps(s);
1432 while (num_irqs --)
1433 s->ch[num_irqs].irq = irqs[num_irqs];
1434 for (i = 0; i < 3; i ++) {
1435 s->ch[i].sibling = &s->ch[i + 6];
1436 s->ch[i + 6].sibling = &s->ch[i];
1437 }
1438 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
1439 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1440 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1441 omap_dma_reset(s);
1442 omap_dma_clk_update(s, 0, 1);
1443
1444 iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
1445 omap_dma_writefn, s);
1446 cpu_register_physical_memory(s->base, memsize, iomemtype);
1447
1448 return s;
1449 }
1450
1451 static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1452 {
1453 struct omap_dma_channel_s *ch = s->ch;
1454 uint32_t bmp, bit;
1455
1456 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1457 if (ch->status) {
1458 bmp |= bit;
1459 ch->cstatus |= ch->status;
1460 ch->status = 0;
1461 }
1462 if ((s->irqstat[0] |= s->irqen[0] & bmp))
1463 qemu_irq_raise(s->irq[0]);
1464 if ((s->irqstat[1] |= s->irqen[1] & bmp))
1465 qemu_irq_raise(s->irq[1]);
1466 if ((s->irqstat[2] |= s->irqen[2] & bmp))
1467 qemu_irq_raise(s->irq[2]);
1468 if ((s->irqstat[3] |= s->irqen[3] & bmp))
1469 qemu_irq_raise(s->irq[3]);
1470 }
1471
1472 static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
1473 {
1474 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1475 int irqn = 0, chnum, offset = addr - s->base;
1476 struct omap_dma_channel_s *ch;
1477
1478 switch (offset) {
1479 case 0x00: /* DMA4_REVISION */
1480 return 0x40;
1481
1482 case 0x14: /* DMA4_IRQSTATUS_L3 */
1483 irqn ++;
1484 case 0x10: /* DMA4_IRQSTATUS_L2 */
1485 irqn ++;
1486 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1487 irqn ++;
1488 case 0x08: /* DMA4_IRQSTATUS_L0 */
1489 return s->irqstat[irqn];
1490
1491 case 0x24: /* DMA4_IRQENABLE_L3 */
1492 irqn ++;
1493 case 0x20: /* DMA4_IRQENABLE_L2 */
1494 irqn ++;
1495 case 0x1c: /* DMA4_IRQENABLE_L1 */
1496 irqn ++;
1497 case 0x18: /* DMA4_IRQENABLE_L0 */
1498 return s->irqen[irqn];
1499
1500 case 0x28: /* DMA4_SYSSTATUS */
1501 return 1; /* RESETDONE */
1502
1503 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1504 return s->ocp;
1505
1506 case 0x64: /* DMA4_CAPS_0 */
1507 return s->caps[0];
1508 case 0x6c: /* DMA4_CAPS_2 */
1509 return s->caps[2];
1510 case 0x70: /* DMA4_CAPS_3 */
1511 return s->caps[3];
1512 case 0x74: /* DMA4_CAPS_4 */
1513 return s->caps[4];
1514
1515 case 0x78: /* DMA4_GCR */
1516 return s->gcr;
1517
1518 case 0x80 ... 0xfff:
1519 offset -= 0x80;
1520 chnum = offset / 0x60;
1521 ch = s->ch + chnum;
1522 offset -= chnum * 0x60;
1523 break;
1524
1525 default:
1526 OMAP_BAD_REG(addr);
1527 return 0;
1528 }
1529
1530 /* Per-channel registers */
1531 switch (offset) {
1532 case 0x00: /* DMA4_CCR */
1533 return (ch->buf_disable << 25) |
1534 (ch->src_sync << 24) |
1535 (ch->prefetch << 23) |
1536 ((ch->sync & 0x60) << 14) |
1537 (ch->bs << 18) |
1538 (ch->transparent_copy << 17) |
1539 (ch->constant_fill << 16) |
1540 (ch->mode[1] << 14) |
1541 (ch->mode[0] << 12) |
1542 (0 << 10) | (0 << 9) |
1543 (ch->suspend << 8) |
1544 (ch->enable << 7) |
1545 (ch->priority << 6) |
1546 (ch->fs << 5) | (ch->sync & 0x1f);
1547
1548 case 0x04: /* DMA4_CLNK_CTRL */
1549 return (ch->link_enabled << 15) | ch->link_next_ch;
1550
1551 case 0x08: /* DMA4_CICR */
1552 return ch->interrupts;
1553
1554 case 0x0c: /* DMA4_CSR */
1555 return ch->cstatus;
1556
1557 case 0x10: /* DMA4_CSDP */
1558 return (ch->endian[0] << 21) |
1559 (ch->endian_lock[0] << 20) |
1560 (ch->endian[1] << 19) |
1561 (ch->endian_lock[1] << 18) |
1562 (ch->write_mode << 16) |
1563 (ch->burst[1] << 14) |
1564 (ch->pack[1] << 13) |
1565 (ch->translate[1] << 9) |
1566 (ch->burst[0] << 7) |
1567 (ch->pack[0] << 6) |
1568 (ch->translate[0] << 2) |
1569 (ch->data_type >> 1);
1570
1571 case 0x14: /* DMA4_CEN */
1572 return ch->elements;
1573
1574 case 0x18: /* DMA4_CFN */
1575 return ch->frames;
1576
1577 case 0x1c: /* DMA4_CSSA */
1578 return ch->addr[0];
1579
1580 case 0x20: /* DMA4_CDSA */
1581 return ch->addr[1];
1582
1583 case 0x24: /* DMA4_CSEI */
1584 return ch->element_index[0];
1585
1586 case 0x28: /* DMA4_CSFI */
1587 return ch->frame_index[0];
1588
1589 case 0x2c: /* DMA4_CDEI */
1590 return ch->element_index[1];
1591
1592 case 0x30: /* DMA4_CDFI */
1593 return ch->frame_index[1];
1594
1595 case 0x34: /* DMA4_CSAC */
1596 return ch->active_set.src & 0xffff;
1597
1598 case 0x38: /* DMA4_CDAC */
1599 return ch->active_set.dest & 0xffff;
1600
1601 case 0x3c: /* DMA4_CCEN */
1602 return ch->active_set.element;
1603
1604 case 0x40: /* DMA4_CCFN */
1605 return ch->active_set.frame;
1606
1607 case 0x44: /* DMA4_COLOR */
1608 /* XXX only in sDMA */
1609 return ch->color;
1610
1611 default:
1612 OMAP_BAD_REG(addr);
1613 return 0;
1614 }
1615 }
1616
1617 static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
1618 uint32_t value)
1619 {
1620 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1621 int chnum, irqn = 0, offset = addr - s->base;
1622 struct omap_dma_channel_s *ch;
1623
1624 switch (offset) {
1625 case 0x14: /* DMA4_IRQSTATUS_L3 */
1626 irqn ++;
1627 case 0x10: /* DMA4_IRQSTATUS_L2 */
1628 irqn ++;
1629 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1630 irqn ++;
1631 case 0x08: /* DMA4_IRQSTATUS_L0 */
1632 s->irqstat[irqn] &= ~value;
1633 if (!s->irqstat[irqn])
1634 qemu_irq_lower(s->irq[irqn]);
1635 return;
1636
1637 case 0x24: /* DMA4_IRQENABLE_L3 */
1638 irqn ++;
1639 case 0x20: /* DMA4_IRQENABLE_L2 */
1640 irqn ++;
1641 case 0x1c: /* DMA4_IRQENABLE_L1 */
1642 irqn ++;
1643 case 0x18: /* DMA4_IRQENABLE_L0 */
1644 s->irqen[irqn] = value;
1645 return;
1646
1647 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1648 if (value & 2) /* SOFTRESET */
1649 omap_dma_reset(s);
1650 s->ocp = value & 0x3321;
1651 if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
1652 fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
1653 return;
1654
1655 case 0x78: /* DMA4_GCR */
1656 s->gcr = value & 0x00ff00ff;
1657 if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1658 fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
1659 return;
1660
1661 case 0x80 ... 0xfff:
1662 offset -= 0x80;
1663 chnum = offset / 0x60;
1664 ch = s->ch + chnum;
1665 offset -= chnum * 0x60;
1666 break;
1667
1668 case 0x00: /* DMA4_REVISION */
1669 case 0x28: /* DMA4_SYSSTATUS */
1670 case 0x64: /* DMA4_CAPS_0 */
1671 case 0x6c: /* DMA4_CAPS_2 */
1672 case 0x70: /* DMA4_CAPS_3 */
1673 case 0x74: /* DMA4_CAPS_4 */
1674 OMAP_RO_REG(addr);
1675 return;
1676
1677 default:
1678 OMAP_BAD_REG(addr);
1679 return;
1680 }
1681
1682 /* Per-channel registers */
1683 switch (offset) {
1684 case 0x00: /* DMA4_CCR */
1685 ch->buf_disable = (value >> 25) & 1;
1686 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1687 if (ch->buf_disable && !ch->src_sync)
1688 fprintf(stderr, "%s: Buffering disable is not allowed in "
1689 "destination synchronised mode\n", __FUNCTION__);
1690 ch->prefetch = (value >> 23) & 1;
1691 ch->bs = (value >> 18) & 1;
1692 ch->transparent_copy = (value >> 17) & 1;
1693 ch->constant_fill = (value >> 16) & 1;
1694 ch->mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
1695 ch->mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
1696 ch->suspend = (value & 0x0100) >> 8;
1697 ch->priority = (value & 0x0040) >> 6;
1698 ch->fs = (value & 0x0020) >> 5;
1699 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
1700 fprintf(stderr, "%s: For a packet transfer at least one port "
1701 "must be constant-addressed\n", __FUNCTION__);
1702 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1703 /* XXX must be 0x01 for CamDMA */
1704
1705 if (value & 0x0080)
1706 omap_dma_enable_channel(s, ch);
1707 else
1708 omap_dma_disable_channel(s, ch);
1709
1710 break;
1711
1712 case 0x04: /* DMA4_CLNK_CTRL */
1713 ch->link_enabled = (value >> 15) & 0x1;
1714 ch->link_next_ch = value & 0x1f;
1715 break;
1716
1717 case 0x08: /* DMA4_CICR */
1718 ch->interrupts = value & 0x09be;
1719 break;
1720
1721 case 0x0c: /* DMA4_CSR */
1722 ch->cstatus &= ~value;
1723 break;
1724
1725 case 0x10: /* DMA4_CSDP */
1726 ch->endian[0] =(value >> 21) & 1;
1727 ch->endian_lock[0] =(value >> 20) & 1;
1728 ch->endian[1] =(value >> 19) & 1;
1729 ch->endian_lock[1] =(value >> 18) & 1;
1730 if (ch->endian[0] != ch->endian[1])
1731 fprintf(stderr, "%s: DMA endianned conversion enable attempt\n",
1732 __FUNCTION__);
1733 ch->write_mode = (value >> 16) & 3;
1734 ch->burst[1] = (value & 0xc000) >> 14;
1735 ch->pack[1] = (value & 0x2000) >> 13;
1736 ch->translate[1] = (value & 0x1e00) >> 9;
1737 ch->burst[0] = (value & 0x0180) >> 7;
1738 ch->pack[0] = (value & 0x0040) >> 6;
1739 ch->translate[0] = (value & 0x003c) >> 2;
1740 if (ch->translate[0] | ch->translate[1])
1741 fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
1742 __FUNCTION__);
1743 ch->data_type = 1 << (value & 3);
1744 if ((value & 3) == 3)
1745 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
1746 break;
1747
1748 case 0x14: /* DMA4_CEN */
1749 ch->elements = value & 0xffffff;
1750 break;
1751
1752 case 0x18: /* DMA4_CFN */
1753 ch->frames = value & 0xffff;
1754 break;
1755
1756 case 0x1c: /* DMA4_CSSA */
1757 ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
1758 break;
1759
1760 case 0x20: /* DMA4_CDSA */
1761 ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
1762 break;
1763
1764 case 0x24: /* DMA4_CSEI */
1765 ch->element_index[0] = (int16_t) value;
1766 break;
1767
1768 case 0x28: /* DMA4_CSFI */
1769 ch->frame_index[0] = (int32_t) value;
1770 break;
1771
1772 case 0x2c: /* DMA4_CDEI */
1773 ch->element_index[1] = (int16_t) value;
1774 break;
1775
1776 case 0x30: /* DMA4_CDFI */
1777 ch->frame_index[1] = (int32_t) value;
1778 break;
1779
1780 case 0x44: /* DMA4_COLOR */
1781 /* XXX only in sDMA */
1782 ch->color = value;
1783 break;
1784
1785 case 0x34: /* DMA4_CSAC */
1786 case 0x38: /* DMA4_CDAC */
1787 case 0x3c: /* DMA4_CCEN */
1788 case 0x40: /* DMA4_CCFN */
1789 OMAP_RO_REG(addr);
1790 break;
1791
1792 default:
1793 OMAP_BAD_REG(addr);
1794 }
1795 }
1796
1797 static CPUReadMemoryFunc *omap_dma4_readfn[] = {
1798 omap_badwidth_read16,
1799 omap_dma4_read,
1800 omap_dma4_read,
1801 };
1802
1803 static CPUWriteMemoryFunc *omap_dma4_writefn[] = {
1804 omap_badwidth_write16,
1805 omap_dma4_write,
1806 omap_dma4_write,
1807 };
1808
1809 struct omap_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
1810 struct omap_mpu_state_s *mpu, int fifo,
1811 int chans, omap_clk iclk, omap_clk fclk)
1812 {
1813 int iomemtype;
1814 struct omap_dma_s *s = (struct omap_dma_s *)
1815 qemu_mallocz(sizeof(struct omap_dma_s));
1816
1817 s->base = base;
1818 s->model = omap_dma_4;
1819 s->chans = chans;
1820 s->mpu = mpu;
1821 s->clk = fclk;
1822 memcpy(&s->irq, irqs, sizeof(s->irq));
1823 s->intr_update = omap_dma_interrupts_4_update;
1824 omap_dma_setcaps(s);
1825 s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
1826 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1827 mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
1828 omap_dma_reset(s);
1829 omap_dma_clk_update(s, 0, 1);
1830
1831 iomemtype = cpu_register_io_memory(0, omap_dma4_readfn,
1832 omap_dma4_writefn, s);
1833 cpu_register_physical_memory(s->base, 0x1000, iomemtype);
1834
1835 return s;
1836 }
1837
1838 struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct omap_dma_s *s)
1839 {
1840 return &s->lcd_ch;
1841 }
Qemu copy for testing