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1 /*
2 * TI OMAP DMA gigacell.
3 *
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu-common.h"
21 #include "qemu-timer.h"
22 #include "omap.h"
23 #include "irq.h"
24 #include "soc_dma.h"
25
26 struct omap_dma_channel_s {
27 /* transfer data */
28 int burst[2];
29 int pack[2];
30 int endian[2];
31 int endian_lock[2];
32 int translate[2];
33 enum omap_dma_port port[2];
34 a_target_phys_addr addr[2];
35 e_omap_dma_addressing mode[2];
36 uint32_t elements;
37 uint16_t frames;
38 int32_t frame_index[2];
39 int16_t element_index[2];
40 int data_type;
41
42 /* transfer type */
43 int transparent_copy;
44 int constant_fill;
45 uint32_t color;
46 int prefetch;
47
48 /* auto init and linked channel data */
49 int end_prog;
50 int repeat;
51 int auto_init;
52 int link_enabled;
53 int link_next_ch;
54
55 /* interruption data */
56 int interrupts;
57 int status;
58 int cstatus;
59
60 /* state data */
61 int active;
62 int enable;
63 int sync;
64 int src_sync;
65 int pending_request;
66 int waiting_end_prog;
67 uint16_t cpc;
68 int set_update;
69
70 /* sync type */
71 int fs;
72 int bs;
73
74 /* compatibility */
75 int omap_3_1_compatible_disable;
76
77 qemu_irq irq;
78 struct omap_dma_channel_s *sibling;
79
80 struct omap_dma_reg_set_s {
81 a_target_phys_addr src, dest;
82 int frame;
83 int element;
84 int pck_element;
85 int frame_delta[2];
86 int elem_delta[2];
87 int frames;
88 int elements;
89 int pck_elements;
90 } active_set;
91
92 struct soc_dma_ch_s *dma;
93
94 /* unused parameters */
95 int write_mode;
96 int priority;
97 int interleave_disabled;
98 int type;
99 int suspend;
100 int buf_disable;
101 };
102
103 struct omap_dma_s {
104 struct soc_dma_s *dma;
105
106 struct omap_mpu_state_s *mpu;
107 omap_clk clk;
108 qemu_irq irq[4];
109 void (*intr_update)(struct omap_dma_s *s);
110 enum omap_dma_model model;
111 int omap_3_1_mapping_disabled;
112
113 uint32_t gcr;
114 uint32_t ocp;
115 uint32_t caps[5];
116 uint32_t irqen[4];
117 uint32_t irqstat[4];
118
119 int chans;
120 struct omap_dma_channel_s ch[32];
121 struct omap_dma_lcd_channel_s lcd_ch;
122 };
123
124 /* Interrupts */
125 #define TIMEOUT_INTR (1 << 0)
126 #define EVENT_DROP_INTR (1 << 1)
127 #define HALF_FRAME_INTR (1 << 2)
128 #define END_FRAME_INTR (1 << 3)
129 #define LAST_FRAME_INTR (1 << 4)
130 #define END_BLOCK_INTR (1 << 5)
131 #define SYNC (1 << 6)
132 #define END_PKT_INTR (1 << 7)
133 #define TRANS_ERR_INTR (1 << 8)
134 #define MISALIGN_INTR (1 << 11)
135
136 static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
137 {
138 return s->intr_update(s);
139 }
140
141 static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
142 {
143 struct omap_dma_reg_set_s *a = &ch->active_set;
144 int i, normal;
145 int omap_3_1 = !ch->omap_3_1_compatible_disable;
146
147 /*
148 * TODO: verify address ranges and alignment
149 * TODO: port endianness
150 */
151
152 a->src = ch->addr[0];
153 a->dest = ch->addr[1];
154 a->frames = ch->frames;
155 a->elements = ch->elements;
156 a->pck_elements = ch->frame_index[!ch->src_sync];
157 a->frame = 0;
158 a->element = 0;
159 a->pck_element = 0;
160
161 if (unlikely(!ch->elements || !ch->frames)) {
162 printf("%s: bad DMA request\n", __FUNCTION__);
163 return;
164 }
165
166 for (i = 0; i < 2; i ++)
167 switch (ch->mode[i]) {
168 case constant:
169 a->elem_delta[i] = 0;
170 a->frame_delta[i] = 0;
171 break;
172 case post_incremented:
173 a->elem_delta[i] = ch->data_type;
174 a->frame_delta[i] = 0;
175 break;
176 case single_index:
177 a->elem_delta[i] = ch->data_type +
178 ch->element_index[omap_3_1 ? 0 : i] - 1;
179 a->frame_delta[i] = 0;
180 break;
181 case double_index:
182 a->elem_delta[i] = ch->data_type +
183 ch->element_index[omap_3_1 ? 0 : i] - 1;
184 a->frame_delta[i] = ch->frame_index[omap_3_1 ? 0 : i] -
185 ch->element_index[omap_3_1 ? 0 : i];
186 break;
187 default:
188 break;
189 }
190
191 normal = !ch->transparent_copy && !ch->constant_fill &&
192 /* FIFO is big-endian so either (ch->endian[n] == 1) OR
193 * (ch->endian_lock[n] == 1) mean no endianism conversion. */
194 (ch->endian[0] | ch->endian_lock[0]) ==
195 (ch->endian[1] | ch->endian_lock[1]);
196 for (i = 0; i < 2; i ++) {
197 /* TODO: for a->frame_delta[i] > 0 still use the fast path, just
198 * limit min_elems in omap_dma_transfer_setup to the nearest frame
199 * end. */
200 if (!a->elem_delta[i] && normal &&
201 (a->frames == 1 || !a->frame_delta[i]))
202 ch->dma->type[i] = soc_dma_access_const;
203 else if (a->elem_delta[i] == ch->data_type && normal &&
204 (a->frames == 1 || !a->frame_delta[i]))
205 ch->dma->type[i] = soc_dma_access_linear;
206 else
207 ch->dma->type[i] = soc_dma_access_other;
208
209 ch->dma->vaddr[i] = ch->addr[i];
210 }
211 soc_dma_ch_update(ch->dma);
212 }
213
214 static void omap_dma_activate_channel(struct omap_dma_s *s,
215 struct omap_dma_channel_s *ch)
216 {
217 if (!ch->active) {
218 if (ch->set_update) {
219 /* It's not clear when the active set is supposed to be
220 * loaded from registers. We're already loading it when the
221 * channel is enabled, and for some guests this is not enough
222 * but that may be also because of a race condition (no
223 * delays in qemu) in the guest code, which we're just
224 * working around here. */
225 omap_dma_channel_load(ch);
226 ch->set_update = 0;
227 }
228
229 ch->active = 1;
230 soc_dma_set_request(ch->dma, 1);
231 if (ch->sync)
232 ch->status |= SYNC;
233 }
234 }
235
236 static void omap_dma_deactivate_channel(struct omap_dma_s *s,
237 struct omap_dma_channel_s *ch)
238 {
239 /* Update cpc */
240 ch->cpc = ch->active_set.dest & 0xffff;
241
242 if (ch->pending_request && !ch->waiting_end_prog && ch->enable) {
243 /* Don't deactivate the channel */
244 ch->pending_request = 0;
245 return;
246 }
247
248 /* Don't deactive the channel if it is synchronized and the DMA request is
249 active */
250 if (ch->sync && ch->enable && (s->dma->drqbmp & (1 << ch->sync)))
251 return;
252
253 if (ch->active) {
254 ch->active = 0;
255 ch->status &= ~SYNC;
256 soc_dma_set_request(ch->dma, 0);
257 }
258 }
259
260 static void omap_dma_enable_channel(struct omap_dma_s *s,
261 struct omap_dma_channel_s *ch)
262 {
263 if (!ch->enable) {
264 ch->enable = 1;
265 ch->waiting_end_prog = 0;
266 omap_dma_channel_load(ch);
267 /* TODO: theoretically if ch->sync && ch->prefetch &&
268 * !s->dma->drqbmp[ch->sync], we should also activate and fetch
269 * from source and then stall until signalled. */
270 if ((!ch->sync) || (s->dma->drqbmp & (1 << ch->sync)))
271 omap_dma_activate_channel(s, ch);
272 }
273 }
274
275 static void omap_dma_disable_channel(struct omap_dma_s *s,
276 struct omap_dma_channel_s *ch)
277 {
278 if (ch->enable) {
279 ch->enable = 0;
280 /* Discard any pending request */
281 ch->pending_request = 0;
282 omap_dma_deactivate_channel(s, ch);
283 }
284 }
285
286 static void omap_dma_channel_end_prog(struct omap_dma_s *s,
287 struct omap_dma_channel_s *ch)
288 {
289 if (ch->waiting_end_prog) {
290 ch->waiting_end_prog = 0;
291 if (!ch->sync || ch->pending_request) {
292 ch->pending_request = 0;
293 omap_dma_activate_channel(s, ch);
294 }
295 }
296 }
297
298 static void omap_dma_interrupts_3_1_update(struct omap_dma_s *s)
299 {
300 struct omap_dma_channel_s *ch = s->ch;
301
302 /* First three interrupts are shared between two channels each. */
303 if (ch[0].status | ch[6].status)
304 qemu_irq_raise(ch[0].irq);
305 if (ch[1].status | ch[7].status)
306 qemu_irq_raise(ch[1].irq);
307 if (ch[2].status | ch[8].status)
308 qemu_irq_raise(ch[2].irq);
309 if (ch[3].status)
310 qemu_irq_raise(ch[3].irq);
311 if (ch[4].status)
312 qemu_irq_raise(ch[4].irq);
313 if (ch[5].status)
314 qemu_irq_raise(ch[5].irq);
315 }
316
317 static void omap_dma_interrupts_3_2_update(struct omap_dma_s *s)
318 {
319 struct omap_dma_channel_s *ch = s->ch;
320 int i;
321
322 for (i = s->chans; i; ch ++, i --)
323 if (ch->status)
324 qemu_irq_raise(ch->irq);
325 }
326
327 static void omap_dma_enable_3_1_mapping(struct omap_dma_s *s)
328 {
329 s->omap_3_1_mapping_disabled = 0;
330 s->chans = 9;
331 s->intr_update = omap_dma_interrupts_3_1_update;
332 }
333
334 static void omap_dma_disable_3_1_mapping(struct omap_dma_s *s)
335 {
336 s->omap_3_1_mapping_disabled = 1;
337 s->chans = 16;
338 s->intr_update = omap_dma_interrupts_3_2_update;
339 }
340
341 static void omap_dma_process_request(struct omap_dma_s *s, int request)
342 {
343 int channel;
344 int drop_event = 0;
345 struct omap_dma_channel_s *ch = s->ch;
346
347 for (channel = 0; channel < s->chans; channel ++, ch ++) {
348 if (ch->enable && ch->sync == request) {
349 if (!ch->active)
350 omap_dma_activate_channel(s, ch);
351 else if (!ch->pending_request)
352 ch->pending_request = 1;
353 else {
354 /* Request collision */
355 /* Second request received while processing other request */
356 ch->status |= EVENT_DROP_INTR;
357 drop_event = 1;
358 }
359 }
360 }
361
362 if (drop_event)
363 omap_dma_interrupts_update(s);
364 }
365
366 static void omap_dma_transfer_generic(struct soc_dma_ch_s *dma)
367 {
368 uint8_t value[4];
369 struct omap_dma_channel_s *ch = dma->opaque;
370 struct omap_dma_reg_set_s *a = &ch->active_set;
371 int bytes = dma->bytes;
372 #ifdef MULTI_REQ
373 uint16_t status = ch->status;
374 #endif
375
376 do {
377 /* Transfer a single element */
378 /* FIXME: check the endianness */
379 if (!ch->constant_fill)
380 cpu_physical_memory_read(a->src, value, ch->data_type);
381 else
382 *(uint32_t *) value = ch->color;
383
384 if (!ch->transparent_copy || *(uint32_t *) value != ch->color)
385 cpu_physical_memory_write(a->dest, value, ch->data_type);
386
387 a->src += a->elem_delta[0];
388 a->dest += a->elem_delta[1];
389 a->element ++;
390
391 #ifndef MULTI_REQ
392 if (a->element == a->elements) {
393 /* End of Frame */
394 a->element = 0;
395 a->src += a->frame_delta[0];
396 a->dest += a->frame_delta[1];
397 a->frame ++;
398
399 /* If the channel is async, update cpc */
400 if (!ch->sync)
401 ch->cpc = a->dest & 0xffff;
402 }
403 } while ((bytes -= ch->data_type));
404 #else
405 /* If the channel is element synchronized, deactivate it */
406 if (ch->sync && !ch->fs && !ch->bs)
407 omap_dma_deactivate_channel(s, ch);
408
409 /* If it is the last frame, set the LAST_FRAME interrupt */
410 if (a->element == 1 && a->frame == a->frames - 1)
411 if (ch->interrupts & LAST_FRAME_INTR)
412 ch->status |= LAST_FRAME_INTR;
413
414 /* If the half of the frame was reached, set the HALF_FRAME
415 interrupt */
416 if (a->element == (a->elements >> 1))
417 if (ch->interrupts & HALF_FRAME_INTR)
418 ch->status |= HALF_FRAME_INTR;
419
420 if (ch->fs && ch->bs) {
421 a->pck_element ++;
422 /* Check if a full packet has beed transferred. */
423 if (a->pck_element == a->pck_elements) {
424 a->pck_element = 0;
425
426 /* Set the END_PKT interrupt */
427 if ((ch->interrupts & END_PKT_INTR) && !ch->src_sync)
428 ch->status |= END_PKT_INTR;
429
430 /* If the channel is packet-synchronized, deactivate it */
431 if (ch->sync)
432 omap_dma_deactivate_channel(s, ch);
433 }
434 }
435
436 if (a->element == a->elements) {
437 /* End of Frame */
438 a->element = 0;
439 a->src += a->frame_delta[0];
440 a->dest += a->frame_delta[1];
441 a->frame ++;
442
443 /* If the channel is frame synchronized, deactivate it */
444 if (ch->sync && ch->fs && !ch->bs)
445 omap_dma_deactivate_channel(s, ch);
446
447 /* If the channel is async, update cpc */
448 if (!ch->sync)
449 ch->cpc = a->dest & 0xffff;
450
451 /* Set the END_FRAME interrupt */
452 if (ch->interrupts & END_FRAME_INTR)
453 ch->status |= END_FRAME_INTR;
454
455 if (a->frame == a->frames) {
456 /* End of Block */
457 /* Disable the channel */
458
459 if (ch->omap_3_1_compatible_disable) {
460 omap_dma_disable_channel(s, ch);
461 if (ch->link_enabled)
462 omap_dma_enable_channel(s,
463 &s->ch[ch->link_next_ch]);
464 } else {
465 if (!ch->auto_init)
466 omap_dma_disable_channel(s, ch);
467 else if (ch->repeat || ch->end_prog)
468 omap_dma_channel_load(ch);
469 else {
470 ch->waiting_end_prog = 1;
471 omap_dma_deactivate_channel(s, ch);
472 }
473 }
474
475 if (ch->interrupts & END_BLOCK_INTR)
476 ch->status |= END_BLOCK_INTR;
477 }
478 }
479 } while (status == ch->status && ch->active);
480
481 omap_dma_interrupts_update(s);
482 #endif
483 }
484
485 enum {
486 omap_dma_intr_element_sync,
487 omap_dma_intr_last_frame,
488 omap_dma_intr_half_frame,
489 omap_dma_intr_frame,
490 omap_dma_intr_frame_sync,
491 omap_dma_intr_packet,
492 omap_dma_intr_packet_sync,
493 omap_dma_intr_block,
494 __omap_dma_intr_last,
495 };
496
497 static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma)
498 {
499 struct omap_dma_port_if_s *src_p, *dest_p;
500 struct omap_dma_reg_set_s *a;
501 struct omap_dma_channel_s *ch = dma->opaque;
502 struct omap_dma_s *s = dma->dma->opaque;
503 int frames, min_elems, elements[__omap_dma_intr_last];
504
505 a = &ch->active_set;
506
507 src_p = &s->mpu->port[ch->port[0]];
508 dest_p = &s->mpu->port[ch->port[1]];
509 if ((!ch->constant_fill && !src_p->addr_valid(s->mpu, a->src)) ||
510 (!dest_p->addr_valid(s->mpu, a->dest))) {
511 #if 0
512 /* Bus time-out */
513 if (ch->interrupts & TIMEOUT_INTR)
514 ch->status |= TIMEOUT_INTR;
515 omap_dma_deactivate_channel(s, ch);
516 continue;
517 #endif
518 printf("%s: Bus time-out in DMA%i operation\n",
519 __FUNCTION__, dma->num);
520 }
521
522 min_elems = INT_MAX;
523
524 /* Check all the conditions that terminate the transfer starting
525 * with those that can occur the soonest. */
526 #define INTR_CHECK(cond, id, nelements) \
527 if (cond) { \
528 elements[id] = nelements; \
529 if (elements[id] < min_elems) \
530 min_elems = elements[id]; \
531 } else \
532 elements[id] = INT_MAX;
533
534 /* Elements */
535 INTR_CHECK(
536 ch->sync && !ch->fs && !ch->bs,
537 omap_dma_intr_element_sync,
538 1)
539
540 /* Frames */
541 /* TODO: for transfers where entire frames can be read and written
542 * using memcpy() but a->frame_delta is non-zero, try to still do
543 * transfers using soc_dma but limit min_elems to a->elements - ...
544 * See also the TODO in omap_dma_channel_load. */
545 INTR_CHECK(
546 (ch->interrupts & LAST_FRAME_INTR) &&
547 ((a->frame < a->frames - 1) || !a->element),
548 omap_dma_intr_last_frame,
549 (a->frames - a->frame - 2) * a->elements +
550 (a->elements - a->element + 1))
551 INTR_CHECK(
552 ch->interrupts & HALF_FRAME_INTR,
553 omap_dma_intr_half_frame,
554 (a->elements >> 1) +
555 (a->element >= (a->elements >> 1) ? a->elements : 0) -
556 a->element)
557 INTR_CHECK(
558 ch->sync && ch->fs && (ch->interrupts & END_FRAME_INTR),
559 omap_dma_intr_frame,
560 a->elements - a->element)
561 INTR_CHECK(
562 ch->sync && ch->fs && !ch->bs,
563 omap_dma_intr_frame_sync,
564 a->elements - a->element)
565
566 /* Packets */
567 INTR_CHECK(
568 ch->fs && ch->bs &&
569 (ch->interrupts & END_PKT_INTR) && !ch->src_sync,
570 omap_dma_intr_packet,
571 a->pck_elements - a->pck_element)
572 INTR_CHECK(
573 ch->fs && ch->bs && ch->sync,
574 omap_dma_intr_packet_sync,
575 a->pck_elements - a->pck_element)
576
577 /* Blocks */
578 INTR_CHECK(
579 1,
580 omap_dma_intr_block,
581 (a->frames - a->frame - 1) * a->elements +
582 (a->elements - a->element))
583
584 dma->bytes = min_elems * ch->data_type;
585
586 /* Set appropriate interrupts and/or deactivate channels */
587
588 #ifdef MULTI_REQ
589 /* TODO: should all of this only be done if dma->update, and otherwise
590 * inside omap_dma_transfer_generic below - check what's faster. */
591 if (dma->update)
592 #endif
593
594 /* If the channel is element synchronized, deactivate it */
595 if (min_elems == elements[omap_dma_intr_element_sync])
596 omap_dma_deactivate_channel(s, ch);
597
598 /* If it is the last frame, set the LAST_FRAME interrupt */
599 if (min_elems == elements[omap_dma_intr_last_frame])
600 ch->status |= LAST_FRAME_INTR;
601
602 /* If exactly half of the frame was reached, set the HALF_FRAME
603 interrupt */
604 if (min_elems == elements[omap_dma_intr_half_frame])
605 ch->status |= HALF_FRAME_INTR;
606
607 /* If a full packet has been transferred, set the END_PKT interrupt */
608 if (min_elems == elements[omap_dma_intr_packet])
609 ch->status |= END_PKT_INTR;
610
611 /* If the channel is packet-synchronized, deactivate it */
612 if (min_elems == elements[omap_dma_intr_packet_sync])
613 omap_dma_deactivate_channel(s, ch);
614
615 /* If the channel is frame synchronized, deactivate it */
616 if (min_elems == elements[omap_dma_intr_frame_sync])
617 omap_dma_deactivate_channel(s, ch);
618
619 /* Set the END_FRAME interrupt */
620 if (min_elems == elements[omap_dma_intr_frame])
621 ch->status |= END_FRAME_INTR;
622
623 if (min_elems == elements[omap_dma_intr_block]) {
624 /* End of Block */
625 /* Disable the channel */
626
627 if (ch->omap_3_1_compatible_disable) {
628 omap_dma_disable_channel(s, ch);
629 if (ch->link_enabled)
630 omap_dma_enable_channel(s, &s->ch[ch->link_next_ch]);
631 } else {
632 if (!ch->auto_init)
633 omap_dma_disable_channel(s, ch);
634 else if (ch->repeat || ch->end_prog)
635 omap_dma_channel_load(ch);
636 else {
637 ch->waiting_end_prog = 1;
638 omap_dma_deactivate_channel(s, ch);
639 }
640 }
641
642 if (ch->interrupts & END_BLOCK_INTR)
643 ch->status |= END_BLOCK_INTR;
644 }
645
646 /* Update packet number */
647 if (ch->fs && ch->bs) {
648 a->pck_element += min_elems;
649 a->pck_element %= a->pck_elements;
650 }
651
652 /* TODO: check if we really need to update anything here or perhaps we
653 * can skip part of this. */
654 #ifndef MULTI_REQ
655 if (dma->update) {
656 #endif
657 a->element += min_elems;
658
659 frames = a->element / a->elements;
660 a->element = a->element % a->elements;
661 a->frame += frames;
662 a->src += min_elems * a->elem_delta[0] + frames * a->frame_delta[0];
663 a->dest += min_elems * a->elem_delta[1] + frames * a->frame_delta[1];
664
665 /* If the channel is async, update cpc */
666 if (!ch->sync && frames)
667 ch->cpc = a->dest & 0xffff;
668
669 /* TODO: if the destination port is IMIF or EMIFF, set the dirty
670 * bits on it. */
671 #ifndef MULTI_REQ
672 }
673 #endif
674
675 omap_dma_interrupts_update(s);
676 }
677
678 void omap_dma_reset(struct soc_dma_s *dma)
679 {
680 int i;
681 struct omap_dma_s *s = dma->opaque;
682
683 soc_dma_reset(s->dma);
684 if (s->model < omap_dma_4)
685 s->gcr = 0x0004;
686 else
687 s->gcr = 0x00010010;
688 s->ocp = 0x00000000;
689 memset(&s->irqstat, 0, sizeof(s->irqstat));
690 memset(&s->irqen, 0, sizeof(s->irqen));
691 s->lcd_ch.src = emiff;
692 s->lcd_ch.condition = 0;
693 s->lcd_ch.interrupts = 0;
694 s->lcd_ch.dual = 0;
695 if (s->model < omap_dma_4)
696 omap_dma_enable_3_1_mapping(s);
697 for (i = 0; i < s->chans; i ++) {
698 s->ch[i].suspend = 0;
699 s->ch[i].prefetch = 0;
700 s->ch[i].buf_disable = 0;
701 s->ch[i].src_sync = 0;
702 memset(&s->ch[i].burst, 0, sizeof(s->ch[i].burst));
703 memset(&s->ch[i].port, 0, sizeof(s->ch[i].port));
704 memset(&s->ch[i].mode, 0, sizeof(s->ch[i].mode));
705 memset(&s->ch[i].frame_index, 0, sizeof(s->ch[i].frame_index));
706 memset(&s->ch[i].element_index, 0, sizeof(s->ch[i].element_index));
707 memset(&s->ch[i].endian, 0, sizeof(s->ch[i].endian));
708 memset(&s->ch[i].endian_lock, 0, sizeof(s->ch[i].endian_lock));
709 memset(&s->ch[i].translate, 0, sizeof(s->ch[i].translate));
710 s->ch[i].write_mode = 0;
711 s->ch[i].data_type = 0;
712 s->ch[i].transparent_copy = 0;
713 s->ch[i].constant_fill = 0;
714 s->ch[i].color = 0x00000000;
715 s->ch[i].end_prog = 0;
716 s->ch[i].repeat = 0;
717 s->ch[i].auto_init = 0;
718 s->ch[i].link_enabled = 0;
719 if (s->model < omap_dma_4)
720 s->ch[i].interrupts = 0x0003;
721 else
722 s->ch[i].interrupts = 0x0000;
723 s->ch[i].status = 0;
724 s->ch[i].cstatus = 0;
725 s->ch[i].active = 0;
726 s->ch[i].enable = 0;
727 s->ch[i].sync = 0;
728 s->ch[i].pending_request = 0;
729 s->ch[i].waiting_end_prog = 0;
730 s->ch[i].cpc = 0x0000;
731 s->ch[i].fs = 0;
732 s->ch[i].bs = 0;
733 s->ch[i].omap_3_1_compatible_disable = 0;
734 memset(&s->ch[i].active_set, 0, sizeof(s->ch[i].active_set));
735 s->ch[i].priority = 0;
736 s->ch[i].interleave_disabled = 0;
737 s->ch[i].type = 0;
738 }
739 }
740
741 static int omap_dma_ch_reg_read(struct omap_dma_s *s,
742 struct omap_dma_channel_s *ch, int reg, uint16_t *value)
743 {
744 switch (reg) {
745 case 0x00: /* SYS_DMA_CSDP_CH0 */
746 *value = (ch->burst[1] << 14) |
747 (ch->pack[1] << 13) |
748 (ch->port[1] << 9) |
749 (ch->burst[0] << 7) |
750 (ch->pack[0] << 6) |
751 (ch->port[0] << 2) |
752 (ch->data_type >> 1);
753 break;
754
755 case 0x02: /* SYS_DMA_CCR_CH0 */
756 if (s->model <= omap_dma_3_1)
757 *value = 0 << 10; /* FIFO_FLUSH reads as 0 */
758 else
759 *value = ch->omap_3_1_compatible_disable << 10;
760 *value |= (ch->mode[1] << 14) |
761 (ch->mode[0] << 12) |
762 (ch->end_prog << 11) |
763 (ch->repeat << 9) |
764 (ch->auto_init << 8) |
765 (ch->enable << 7) |
766 (ch->priority << 6) |
767 (ch->fs << 5) | ch->sync;
768 break;
769
770 case 0x04: /* SYS_DMA_CICR_CH0 */
771 *value = ch->interrupts;
772 break;
773
774 case 0x06: /* SYS_DMA_CSR_CH0 */
775 *value = ch->status;
776 ch->status &= SYNC;
777 if (!ch->omap_3_1_compatible_disable && ch->sibling) {
778 *value |= (ch->sibling->status & 0x3f) << 6;
779 ch->sibling->status &= SYNC;
780 }
781 qemu_irq_lower(ch->irq);
782 break;
783
784 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
785 *value = ch->addr[0] & 0x0000ffff;
786 break;
787
788 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
789 *value = ch->addr[0] >> 16;
790 break;
791
792 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
793 *value = ch->addr[1] & 0x0000ffff;
794 break;
795
796 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
797 *value = ch->addr[1] >> 16;
798 break;
799
800 case 0x10: /* SYS_DMA_CEN_CH0 */
801 *value = ch->elements;
802 break;
803
804 case 0x12: /* SYS_DMA_CFN_CH0 */
805 *value = ch->frames;
806 break;
807
808 case 0x14: /* SYS_DMA_CFI_CH0 */
809 *value = ch->frame_index[0];
810 break;
811
812 case 0x16: /* SYS_DMA_CEI_CH0 */
813 *value = ch->element_index[0];
814 break;
815
816 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
817 if (ch->omap_3_1_compatible_disable)
818 *value = ch->active_set.src & 0xffff; /* CSAC */
819 else
820 *value = ch->cpc;
821 break;
822
823 case 0x1a: /* DMA_CDAC */
824 *value = ch->active_set.dest & 0xffff; /* CDAC */
825 break;
826
827 case 0x1c: /* DMA_CDEI */
828 *value = ch->element_index[1];
829 break;
830
831 case 0x1e: /* DMA_CDFI */
832 *value = ch->frame_index[1];
833 break;
834
835 case 0x20: /* DMA_COLOR_L */
836 *value = ch->color & 0xffff;
837 break;
838
839 case 0x22: /* DMA_COLOR_U */
840 *value = ch->color >> 16;
841 break;
842
843 case 0x24: /* DMA_CCR2 */
844 *value = (ch->bs << 2) |
845 (ch->transparent_copy << 1) |
846 ch->constant_fill;
847 break;
848
849 case 0x28: /* DMA_CLNK_CTRL */
850 *value = (ch->link_enabled << 15) |
851 (ch->link_next_ch & 0xf);
852 break;
853
854 case 0x2a: /* DMA_LCH_CTRL */
855 *value = (ch->interleave_disabled << 15) |
856 ch->type;
857 break;
858
859 default:
860 return 1;
861 }
862 return 0;
863 }
864
865 static int omap_dma_ch_reg_write(struct omap_dma_s *s,
866 struct omap_dma_channel_s *ch, int reg, uint16_t value)
867 {
868 switch (reg) {
869 case 0x00: /* SYS_DMA_CSDP_CH0 */
870 ch->burst[1] = (value & 0xc000) >> 14;
871 ch->pack[1] = (value & 0x2000) >> 13;
872 ch->port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
873 ch->burst[0] = (value & 0x0180) >> 7;
874 ch->pack[0] = (value & 0x0040) >> 6;
875 ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
876 ch->data_type = 1 << (value & 3);
877 if (ch->port[0] >= __omap_dma_port_last)
878 printf("%s: invalid DMA port %i\n", __FUNCTION__,
879 ch->port[0]);
880 if (ch->port[1] >= __omap_dma_port_last)
881 printf("%s: invalid DMA port %i\n", __FUNCTION__,
882 ch->port[1]);
883 if ((value & 3) == 3)
884 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
885 break;
886
887 case 0x02: /* SYS_DMA_CCR_CH0 */
888 ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14);
889 ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12);
890 ch->end_prog = (value & 0x0800) >> 11;
891 if (s->model >= omap_dma_3_2)
892 ch->omap_3_1_compatible_disable = (value >> 10) & 0x1;
893 ch->repeat = (value & 0x0200) >> 9;
894 ch->auto_init = (value & 0x0100) >> 8;
895 ch->priority = (value & 0x0040) >> 6;
896 ch->fs = (value & 0x0020) >> 5;
897 ch->sync = value & 0x001f;
898
899 if (value & 0x0080)
900 omap_dma_enable_channel(s, ch);
901 else
902 omap_dma_disable_channel(s, ch);
903
904 if (ch->end_prog)
905 omap_dma_channel_end_prog(s, ch);
906
907 break;
908
909 case 0x04: /* SYS_DMA_CICR_CH0 */
910 ch->interrupts = value & 0x3f;
911 break;
912
913 case 0x06: /* SYS_DMA_CSR_CH0 */
914 OMAP_RO_REG((a_target_phys_addr) reg);
915 break;
916
917 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
918 ch->addr[0] &= 0xffff0000;
919 ch->addr[0] |= value;
920 break;
921
922 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
923 ch->addr[0] &= 0x0000ffff;
924 ch->addr[0] |= (uint32_t) value << 16;
925 break;
926
927 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
928 ch->addr[1] &= 0xffff0000;
929 ch->addr[1] |= value;
930 break;
931
932 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
933 ch->addr[1] &= 0x0000ffff;
934 ch->addr[1] |= (uint32_t) value << 16;
935 break;
936
937 case 0x10: /* SYS_DMA_CEN_CH0 */
938 ch->elements = value;
939 break;
940
941 case 0x12: /* SYS_DMA_CFN_CH0 */
942 ch->frames = value;
943 break;
944
945 case 0x14: /* SYS_DMA_CFI_CH0 */
946 ch->frame_index[0] = (int16_t) value;
947 break;
948
949 case 0x16: /* SYS_DMA_CEI_CH0 */
950 ch->element_index[0] = (int16_t) value;
951 break;
952
953 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
954 OMAP_RO_REG((a_target_phys_addr) reg);
955 break;
956
957 case 0x1c: /* DMA_CDEI */
958 ch->element_index[1] = (int16_t) value;
959 break;
960
961 case 0x1e: /* DMA_CDFI */
962 ch->frame_index[1] = (int16_t) value;
963 break;
964
965 case 0x20: /* DMA_COLOR_L */
966 ch->color &= 0xffff0000;
967 ch->color |= value;
968 break;
969
970 case 0x22: /* DMA_COLOR_U */
971 ch->color &= 0xffff;
972 ch->color |= value << 16;
973 break;
974
975 case 0x24: /* DMA_CCR2 */
976 ch->bs = (value >> 2) & 0x1;
977 ch->transparent_copy = (value >> 1) & 0x1;
978 ch->constant_fill = value & 0x1;
979 break;
980
981 case 0x28: /* DMA_CLNK_CTRL */
982 ch->link_enabled = (value >> 15) & 0x1;
983 if (value & (1 << 14)) { /* Stop_Lnk */
984 ch->link_enabled = 0;
985 omap_dma_disable_channel(s, ch);
986 }
987 ch->link_next_ch = value & 0x1f;
988 break;
989
990 case 0x2a: /* DMA_LCH_CTRL */
991 ch->interleave_disabled = (value >> 15) & 0x1;
992 ch->type = value & 0xf;
993 break;
994
995 default:
996 return 1;
997 }
998 return 0;
999 }
1000
1001 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1002 uint16_t value)
1003 {
1004 switch (offset) {
1005 case 0xbc0: /* DMA_LCD_CSDP */
1006 s->brust_f2 = (value >> 14) & 0x3;
1007 s->pack_f2 = (value >> 13) & 0x1;
1008 s->data_type_f2 = (1 << ((value >> 11) & 0x3));
1009 s->brust_f1 = (value >> 7) & 0x3;
1010 s->pack_f1 = (value >> 6) & 0x1;
1011 s->data_type_f1 = (1 << ((value >> 0) & 0x3));
1012 break;
1013
1014 case 0xbc2: /* DMA_LCD_CCR */
1015 s->mode_f2 = (value >> 14) & 0x3;
1016 s->mode_f1 = (value >> 12) & 0x3;
1017 s->end_prog = (value >> 11) & 0x1;
1018 s->omap_3_1_compatible_disable = (value >> 10) & 0x1;
1019 s->repeat = (value >> 9) & 0x1;
1020 s->auto_init = (value >> 8) & 0x1;
1021 s->running = (value >> 7) & 0x1;
1022 s->priority = (value >> 6) & 0x1;
1023 s->bs = (value >> 4) & 0x1;
1024 break;
1025
1026 case 0xbc4: /* DMA_LCD_CTRL */
1027 s->dst = (value >> 8) & 0x1;
1028 s->src = ((value >> 6) & 0x3) << 1;
1029 s->condition = 0;
1030 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1031 s->interrupts = (value >> 1) & 1;
1032 s->dual = value & 1;
1033 break;
1034
1035 case 0xbc8: /* TOP_B1_L */
1036 s->src_f1_top &= 0xffff0000;
1037 s->src_f1_top |= 0x0000ffff & value;
1038 break;
1039
1040 case 0xbca: /* TOP_B1_U */
1041 s->src_f1_top &= 0x0000ffff;
1042 s->src_f1_top |= value << 16;
1043 break;
1044
1045 case 0xbcc: /* BOT_B1_L */
1046 s->src_f1_bottom &= 0xffff0000;
1047 s->src_f1_bottom |= 0x0000ffff & value;
1048 break;
1049
1050 case 0xbce: /* BOT_B1_U */
1051 s->src_f1_bottom &= 0x0000ffff;
1052 s->src_f1_bottom |= (uint32_t) value << 16;
1053 break;
1054
1055 case 0xbd0: /* TOP_B2_L */
1056 s->src_f2_top &= 0xffff0000;
1057 s->src_f2_top |= 0x0000ffff & value;
1058 break;
1059
1060 case 0xbd2: /* TOP_B2_U */
1061 s->src_f2_top &= 0x0000ffff;
1062 s->src_f2_top |= (uint32_t) value << 16;
1063 break;
1064
1065 case 0xbd4: /* BOT_B2_L */
1066 s->src_f2_bottom &= 0xffff0000;
1067 s->src_f2_bottom |= 0x0000ffff & value;
1068 break;
1069
1070 case 0xbd6: /* BOT_B2_U */
1071 s->src_f2_bottom &= 0x0000ffff;
1072 s->src_f2_bottom |= (uint32_t) value << 16;
1073 break;
1074
1075 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1076 s->element_index_f1 = value;
1077 break;
1078
1079 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1080 s->frame_index_f1 &= 0xffff0000;
1081 s->frame_index_f1 |= 0x0000ffff & value;
1082 break;
1083
1084 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1085 s->frame_index_f1 &= 0x0000ffff;
1086 s->frame_index_f1 |= (uint32_t) value << 16;
1087 break;
1088
1089 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1090 s->element_index_f2 = value;
1091 break;
1092
1093 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1094 s->frame_index_f2 &= 0xffff0000;
1095 s->frame_index_f2 |= 0x0000ffff & value;
1096 break;
1097
1098 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1099 s->frame_index_f2 &= 0x0000ffff;
1100 s->frame_index_f2 |= (uint32_t) value << 16;
1101 break;
1102
1103 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1104 s->elements_f1 = value;
1105 break;
1106
1107 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1108 s->frames_f1 = value;
1109 break;
1110
1111 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1112 s->elements_f2 = value;
1113 break;
1114
1115 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1116 s->frames_f2 = value;
1117 break;
1118
1119 case 0xbea: /* DMA_LCD_LCH_CTRL */
1120 s->lch_type = value & 0xf;
1121 break;
1122
1123 default:
1124 return 1;
1125 }
1126 return 0;
1127 }
1128
1129 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1130 uint16_t *ret)
1131 {
1132 switch (offset) {
1133 case 0xbc0: /* DMA_LCD_CSDP */
1134 *ret = (s->brust_f2 << 14) |
1135 (s->pack_f2 << 13) |
1136 ((s->data_type_f2 >> 1) << 11) |
1137 (s->brust_f1 << 7) |
1138 (s->pack_f1 << 6) |
1139 ((s->data_type_f1 >> 1) << 0);
1140 break;
1141
1142 case 0xbc2: /* DMA_LCD_CCR */
1143 *ret = (s->mode_f2 << 14) |
1144 (s->mode_f1 << 12) |
1145 (s->end_prog << 11) |
1146 (s->omap_3_1_compatible_disable << 10) |
1147 (s->repeat << 9) |
1148 (s->auto_init << 8) |
1149 (s->running << 7) |
1150 (s->priority << 6) |
1151 (s->bs << 4);
1152 break;
1153
1154 case 0xbc4: /* DMA_LCD_CTRL */
1155 qemu_irq_lower(s->irq);
1156 *ret = (s->dst << 8) |
1157 ((s->src & 0x6) << 5) |
1158 (s->condition << 3) |
1159 (s->interrupts << 1) |
1160 s->dual;
1161 break;
1162
1163 case 0xbc8: /* TOP_B1_L */
1164 *ret = s->src_f1_top & 0xffff;
1165 break;
1166
1167 case 0xbca: /* TOP_B1_U */
1168 *ret = s->src_f1_top >> 16;
1169 break;
1170
1171 case 0xbcc: /* BOT_B1_L */
1172 *ret = s->src_f1_bottom & 0xffff;
1173 break;
1174
1175 case 0xbce: /* BOT_B1_U */
1176 *ret = s->src_f1_bottom >> 16;
1177 break;
1178
1179 case 0xbd0: /* TOP_B2_L */
1180 *ret = s->src_f2_top & 0xffff;
1181 break;
1182
1183 case 0xbd2: /* TOP_B2_U */
1184 *ret = s->src_f2_top >> 16;
1185 break;
1186
1187 case 0xbd4: /* BOT_B2_L */
1188 *ret = s->src_f2_bottom & 0xffff;
1189 break;
1190
1191 case 0xbd6: /* BOT_B2_U */
1192 *ret = s->src_f2_bottom >> 16;
1193 break;
1194
1195 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
1196 *ret = s->element_index_f1;
1197 break;
1198
1199 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
1200 *ret = s->frame_index_f1 & 0xffff;
1201 break;
1202
1203 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
1204 *ret = s->frame_index_f1 >> 16;
1205 break;
1206
1207 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1208 *ret = s->element_index_f2;
1209 break;
1210
1211 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1212 *ret = s->frame_index_f2 & 0xffff;
1213 break;
1214
1215 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1216 *ret = s->frame_index_f2 >> 16;
1217 break;
1218
1219 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1220 *ret = s->elements_f1;
1221 break;
1222
1223 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1224 *ret = s->frames_f1;
1225 break;
1226
1227 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1228 *ret = s->elements_f2;
1229 break;
1230
1231 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1232 *ret = s->frames_f2;
1233 break;
1234
1235 case 0xbea: /* DMA_LCD_LCH_CTRL */
1236 *ret = s->lch_type;
1237 break;
1238
1239 default:
1240 return 1;
1241 }
1242 return 0;
1243 }
1244
1245 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s *s, int offset,
1246 uint16_t value)
1247 {
1248 switch (offset) {
1249 case 0x300: /* SYS_DMA_LCD_CTRL */
1250 s->src = (value & 0x40) ? imif : emiff;
1251 s->condition = 0;
1252 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1253 s->interrupts = (value >> 1) & 1;
1254 s->dual = value & 1;
1255 break;
1256
1257 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1258 s->src_f1_top &= 0xffff0000;
1259 s->src_f1_top |= 0x0000ffff & value;
1260 break;
1261
1262 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1263 s->src_f1_top &= 0x0000ffff;
1264 s->src_f1_top |= value << 16;
1265 break;
1266
1267 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1268 s->src_f1_bottom &= 0xffff0000;
1269 s->src_f1_bottom |= 0x0000ffff & value;
1270 break;
1271
1272 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1273 s->src_f1_bottom &= 0x0000ffff;
1274 s->src_f1_bottom |= value << 16;
1275 break;
1276
1277 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1278 s->src_f2_top &= 0xffff0000;
1279 s->src_f2_top |= 0x0000ffff & value;
1280 break;
1281
1282 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1283 s->src_f2_top &= 0x0000ffff;
1284 s->src_f2_top |= value << 16;
1285 break;
1286
1287 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1288 s->src_f2_bottom &= 0xffff0000;
1289 s->src_f2_bottom |= 0x0000ffff & value;
1290 break;
1291
1292 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1293 s->src_f2_bottom &= 0x0000ffff;
1294 s->src_f2_bottom |= value << 16;
1295 break;
1296
1297 default:
1298 return 1;
1299 }
1300 return 0;
1301 }
1302
1303 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s *s, int offset,
1304 uint16_t *ret)
1305 {
1306 int i;
1307
1308 switch (offset) {
1309 case 0x300: /* SYS_DMA_LCD_CTRL */
1310 i = s->condition;
1311 s->condition = 0;
1312 qemu_irq_lower(s->irq);
1313 *ret = ((s->src == imif) << 6) | (i << 3) |
1314 (s->interrupts << 1) | s->dual;
1315 break;
1316
1317 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1318 *ret = s->src_f1_top & 0xffff;
1319 break;
1320
1321 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1322 *ret = s->src_f1_top >> 16;
1323 break;
1324
1325 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1326 *ret = s->src_f1_bottom & 0xffff;
1327 break;
1328
1329 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1330 *ret = s->src_f1_bottom >> 16;
1331 break;
1332
1333 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1334 *ret = s->src_f2_top & 0xffff;
1335 break;
1336
1337 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1338 *ret = s->src_f2_top >> 16;
1339 break;
1340
1341 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1342 *ret = s->src_f2_bottom & 0xffff;
1343 break;
1344
1345 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1346 *ret = s->src_f2_bottom >> 16;
1347 break;
1348
1349 default:
1350 return 1;
1351 }
1352 return 0;
1353 }
1354
1355 static int omap_dma_sys_write(struct omap_dma_s *s, int offset, uint16_t value)
1356 {
1357 switch (offset) {
1358 case 0x400: /* SYS_DMA_GCR */
1359 s->gcr = value;
1360 break;
1361
1362 case 0x404: /* DMA_GSCR */
1363 if (value & 0x8)
1364 omap_dma_disable_3_1_mapping(s);
1365 else
1366 omap_dma_enable_3_1_mapping(s);
1367 break;
1368
1369 case 0x408: /* DMA_GRST */
1370 if (value & 0x1)
1371 omap_dma_reset(s->dma);
1372 break;
1373
1374 default:
1375 return 1;
1376 }
1377 return 0;
1378 }
1379
1380 static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
1381 uint16_t *ret)
1382 {
1383 switch (offset) {
1384 case 0x400: /* SYS_DMA_GCR */
1385 *ret = s->gcr;
1386 break;
1387
1388 case 0x404: /* DMA_GSCR */
1389 *ret = s->omap_3_1_mapping_disabled << 3;
1390 break;
1391
1392 case 0x408: /* DMA_GRST */
1393 *ret = 0;
1394 break;
1395
1396 case 0x442: /* DMA_HW_ID */
1397 case 0x444: /* DMA_PCh2_ID */
1398 case 0x446: /* DMA_PCh0_ID */
1399 case 0x448: /* DMA_PCh1_ID */
1400 case 0x44a: /* DMA_PChG_ID */
1401 case 0x44c: /* DMA_PChD_ID */
1402 *ret = 1;
1403 break;
1404
1405 case 0x44e: /* DMA_CAPS_0_U */
1406 *ret = (s->caps[0] >> 16) & 0xffff;
1407 break;
1408 case 0x450: /* DMA_CAPS_0_L */
1409 *ret = (s->caps[0] >> 0) & 0xffff;
1410 break;
1411
1412 case 0x452: /* DMA_CAPS_1_U */
1413 *ret = (s->caps[1] >> 16) & 0xffff;
1414 break;
1415 case 0x454: /* DMA_CAPS_1_L */
1416 *ret = (s->caps[1] >> 0) & 0xffff;
1417 break;
1418
1419 case 0x456: /* DMA_CAPS_2 */
1420 *ret = s->caps[2];
1421 break;
1422
1423 case 0x458: /* DMA_CAPS_3 */
1424 *ret = s->caps[3];
1425 break;
1426
1427 case 0x45a: /* DMA_CAPS_4 */
1428 *ret = s->caps[4];
1429 break;
1430
1431 case 0x460: /* DMA_PCh2_SR */
1432 case 0x480: /* DMA_PCh0_SR */
1433 case 0x482: /* DMA_PCh1_SR */
1434 case 0x4c0: /* DMA_PChD_SR_0 */
1435 printf("%s: Physical Channel Status Registers not implemented.\n",
1436 __FUNCTION__);
1437 *ret = 0xff;
1438 break;
1439
1440 default:
1441 return 1;
1442 }
1443 return 0;
1444 }
1445
1446 static uint32_t omap_dma_read(void *opaque, a_target_phys_addr addr)
1447 {
1448 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1449 int reg, ch;
1450 uint16_t ret;
1451
1452 switch (addr) {
1453 case 0x300 ... 0x3fe:
1454 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1455 if (omap_dma_3_1_lcd_read(&s->lcd_ch, addr, &ret))
1456 break;
1457 return ret;
1458 }
1459 /* Fall through. */
1460 case 0x000 ... 0x2fe:
1461 reg = addr & 0x3f;
1462 ch = (addr >> 6) & 0x0f;
1463 if (omap_dma_ch_reg_read(s, &s->ch[ch], reg, &ret))
1464 break;
1465 return ret;
1466
1467 case 0x404 ... 0x4fe:
1468 if (s->model <= omap_dma_3_1)
1469 break;
1470 /* Fall through. */
1471 case 0x400:
1472 if (omap_dma_sys_read(s, addr, &ret))
1473 break;
1474 return ret;
1475
1476 case 0xb00 ... 0xbfe:
1477 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1478 if (omap_dma_3_2_lcd_read(&s->lcd_ch, addr, &ret))
1479 break;
1480 return ret;
1481 }
1482 break;
1483 }
1484
1485 OMAP_BAD_REG(addr);
1486 return 0;
1487 }
1488
1489 static void omap_dma_write(void *opaque, a_target_phys_addr addr,
1490 uint32_t value)
1491 {
1492 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1493 int reg, ch;
1494
1495 switch (addr) {
1496 case 0x300 ... 0x3fe:
1497 if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
1498 if (omap_dma_3_1_lcd_write(&s->lcd_ch, addr, value))
1499 break;
1500 return;
1501 }
1502 /* Fall through. */
1503 case 0x000 ... 0x2fe:
1504 reg = addr & 0x3f;
1505 ch = (addr >> 6) & 0x0f;
1506 if (omap_dma_ch_reg_write(s, &s->ch[ch], reg, value))
1507 break;
1508 return;
1509
1510 case 0x404 ... 0x4fe:
1511 if (s->model <= omap_dma_3_1)
1512 break;
1513 case 0x400:
1514 /* Fall through. */
1515 if (omap_dma_sys_write(s, addr, value))
1516 break;
1517 return;
1518
1519 case 0xb00 ... 0xbfe:
1520 if (s->model == omap_dma_3_2 && s->omap_3_1_mapping_disabled) {
1521 if (omap_dma_3_2_lcd_write(&s->lcd_ch, addr, value))
1522 break;
1523 return;
1524 }
1525 break;
1526 }
1527
1528 OMAP_BAD_REG(addr);
1529 }
1530
1531 static CPUReadMemoryFunc * const omap_dma_readfn[] = {
1532 omap_badwidth_read16,
1533 omap_dma_read,
1534 omap_badwidth_read16,
1535 };
1536
1537 static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
1538 omap_badwidth_write16,
1539 omap_dma_write,
1540 omap_badwidth_write16,
1541 };
1542
1543 static void omap_dma_request(void *opaque, int drq, int req)
1544 {
1545 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1546 /* The request pins are level triggered in QEMU. */
1547 if (req) {
1548 if (~s->dma->drqbmp & (1 << drq)) {
1549 s->dma->drqbmp |= 1 << drq;
1550 omap_dma_process_request(s, drq);
1551 }
1552 } else
1553 s->dma->drqbmp &= ~(1 << drq);
1554 }
1555
1556 /* XXX: this won't be needed once soc_dma knows about clocks. */
1557 static void omap_dma_clk_update(void *opaque, int line, int on)
1558 {
1559 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1560 int i;
1561
1562 s->dma->freq = omap_clk_getrate(s->clk);
1563
1564 for (i = 0; i < s->chans; i ++)
1565 if (s->ch[i].active)
1566 soc_dma_set_request(s->ch[i].dma, on);
1567 }
1568
1569 static void omap_dma_setcaps(struct omap_dma_s *s)
1570 {
1571 switch (s->model) {
1572 default:
1573 case omap_dma_3_1:
1574 break;
1575 case omap_dma_3_2:
1576 case omap_dma_4:
1577 /* XXX Only available for sDMA */
1578 s->caps[0] =
1579 (1 << 19) | /* Constant Fill Capability */
1580 (1 << 18); /* Transparent BLT Capability */
1581 s->caps[1] =
1582 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1583 s->caps[2] =
1584 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1585 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1586 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1587 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1588 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1589 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1590 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1591 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1592 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1593 s->caps[3] =
1594 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1595 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1596 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1597 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1598 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1599 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1600 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1601 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1602 s->caps[4] =
1603 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1604 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1605 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1606 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1607 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1608 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1609 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1610 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1611 break;
1612 }
1613 }
1614
1615 struct soc_dma_s *omap_dma_init(a_target_phys_addr base, qemu_irq *irqs,
1616 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
1617 enum omap_dma_model model)
1618 {
1619 int iomemtype, num_irqs, memsize, i;
1620 struct omap_dma_s *s = (struct omap_dma_s *)
1621 qemu_mallocz(sizeof(struct omap_dma_s));
1622
1623 if (model <= omap_dma_3_1) {
1624 num_irqs = 6;
1625 memsize = 0x800;
1626 } else {
1627 num_irqs = 16;
1628 memsize = 0xc00;
1629 }
1630 s->model = model;
1631 s->mpu = mpu;
1632 s->clk = clk;
1633 s->lcd_ch.irq = lcd_irq;
1634 s->lcd_ch.mpu = mpu;
1635
1636 s->dma = soc_dma_init((model <= omap_dma_3_1) ? 9 : 16);
1637 s->dma->freq = omap_clk_getrate(clk);
1638 s->dma->transfer_fn = omap_dma_transfer_generic;
1639 s->dma->setup_fn = omap_dma_transfer_setup;
1640 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
1641 s->dma->opaque = s;
1642
1643 while (num_irqs --)
1644 s->ch[num_irqs].irq = irqs[num_irqs];
1645 for (i = 0; i < 3; i ++) {
1646 s->ch[i].sibling = &s->ch[i + 6];
1647 s->ch[i + 6].sibling = &s->ch[i];
1648 }
1649 for (i = (model <= omap_dma_3_1) ? 8 : 15; i >= 0; i --) {
1650 s->ch[i].dma = &s->dma->ch[i];
1651 s->dma->ch[i].opaque = &s->ch[i];
1652 }
1653
1654 omap_dma_setcaps(s);
1655 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
1656 omap_dma_reset(s->dma);
1657 omap_dma_clk_update(s, 0, 1);
1658
1659 iomemtype = cpu_register_io_memory(omap_dma_readfn,
1660 omap_dma_writefn, s);
1661 cpu_register_physical_memory(base, memsize, iomemtype);
1662
1663 mpu->drq = s->dma->drq;
1664
1665 return s->dma;
1666 }
1667
1668 static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
1669 {
1670 struct omap_dma_channel_s *ch = s->ch;
1671 uint32_t bmp, bit;
1672
1673 for (bmp = 0, bit = 1; bit; ch ++, bit <<= 1)
1674 if (ch->status) {
1675 bmp |= bit;
1676 ch->cstatus |= ch->status;
1677 ch->status = 0;
1678 }
1679 if ((s->irqstat[0] |= s->irqen[0] & bmp))
1680 qemu_irq_raise(s->irq[0]);
1681 if ((s->irqstat[1] |= s->irqen[1] & bmp))
1682 qemu_irq_raise(s->irq[1]);
1683 if ((s->irqstat[2] |= s->irqen[2] & bmp))
1684 qemu_irq_raise(s->irq[2]);
1685 if ((s->irqstat[3] |= s->irqen[3] & bmp))
1686 qemu_irq_raise(s->irq[3]);
1687 }
1688
1689 static uint32_t omap_dma4_read(void *opaque, a_target_phys_addr addr)
1690 {
1691 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1692 int irqn = 0, chnum;
1693 struct omap_dma_channel_s *ch;
1694
1695 switch (addr) {
1696 case 0x00: /* DMA4_REVISION */
1697 return 0x40;
1698
1699 case 0x14: /* DMA4_IRQSTATUS_L3 */
1700 irqn ++;
1701 case 0x10: /* DMA4_IRQSTATUS_L2 */
1702 irqn ++;
1703 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1704 irqn ++;
1705 case 0x08: /* DMA4_IRQSTATUS_L0 */
1706 return s->irqstat[irqn];
1707
1708 case 0x24: /* DMA4_IRQENABLE_L3 */
1709 irqn ++;
1710 case 0x20: /* DMA4_IRQENABLE_L2 */
1711 irqn ++;
1712 case 0x1c: /* DMA4_IRQENABLE_L1 */
1713 irqn ++;
1714 case 0x18: /* DMA4_IRQENABLE_L0 */
1715 return s->irqen[irqn];
1716
1717 case 0x28: /* DMA4_SYSSTATUS */
1718 return 1; /* RESETDONE */
1719
1720 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1721 return s->ocp;
1722
1723 case 0x64: /* DMA4_CAPS_0 */
1724 return s->caps[0];
1725 case 0x6c: /* DMA4_CAPS_2 */
1726 return s->caps[2];
1727 case 0x70: /* DMA4_CAPS_3 */
1728 return s->caps[3];
1729 case 0x74: /* DMA4_CAPS_4 */
1730 return s->caps[4];
1731
1732 case 0x78: /* DMA4_GCR */
1733 return s->gcr;
1734
1735 case 0x80 ... 0xfff:
1736 addr -= 0x80;
1737 chnum = addr / 0x60;
1738 ch = s->ch + chnum;
1739 addr -= chnum * 0x60;
1740 break;
1741
1742 default:
1743 OMAP_BAD_REG(addr);
1744 return 0;
1745 }
1746
1747 /* Per-channel registers */
1748 switch (addr) {
1749 case 0x00: /* DMA4_CCR */
1750 return (ch->buf_disable << 25) |
1751 (ch->src_sync << 24) |
1752 (ch->prefetch << 23) |
1753 ((ch->sync & 0x60) << 14) |
1754 (ch->bs << 18) |
1755 (ch->transparent_copy << 17) |
1756 (ch->constant_fill << 16) |
1757 (ch->mode[1] << 14) |
1758 (ch->mode[0] << 12) |
1759 (0 << 10) | (0 << 9) |
1760 (ch->suspend << 8) |
1761 (ch->enable << 7) |
1762 (ch->priority << 6) |
1763 (ch->fs << 5) | (ch->sync & 0x1f);
1764
1765 case 0x04: /* DMA4_CLNK_CTRL */
1766 return (ch->link_enabled << 15) | ch->link_next_ch;
1767
1768 case 0x08: /* DMA4_CICR */
1769 return ch->interrupts;
1770
1771 case 0x0c: /* DMA4_CSR */
1772 return ch->cstatus;
1773
1774 case 0x10: /* DMA4_CSDP */
1775 return (ch->endian[0] << 21) |
1776 (ch->endian_lock[0] << 20) |
1777 (ch->endian[1] << 19) |
1778 (ch->endian_lock[1] << 18) |
1779 (ch->write_mode << 16) |
1780 (ch->burst[1] << 14) |
1781 (ch->pack[1] << 13) |
1782 (ch->translate[1] << 9) |
1783 (ch->burst[0] << 7) |
1784 (ch->pack[0] << 6) |
1785 (ch->translate[0] << 2) |
1786 (ch->data_type >> 1);
1787
1788 case 0x14: /* DMA4_CEN */
1789 return ch->elements;
1790
1791 case 0x18: /* DMA4_CFN */
1792 return ch->frames;
1793
1794 case 0x1c: /* DMA4_CSSA */
1795 return ch->addr[0];
1796
1797 case 0x20: /* DMA4_CDSA */
1798 return ch->addr[1];
1799
1800 case 0x24: /* DMA4_CSEI */
1801 return ch->element_index[0];
1802
1803 case 0x28: /* DMA4_CSFI */
1804 return ch->frame_index[0];
1805
1806 case 0x2c: /* DMA4_CDEI */
1807 return ch->element_index[1];
1808
1809 case 0x30: /* DMA4_CDFI */
1810 return ch->frame_index[1];
1811
1812 case 0x34: /* DMA4_CSAC */
1813 return ch->active_set.src & 0xffff;
1814
1815 case 0x38: /* DMA4_CDAC */
1816 return ch->active_set.dest & 0xffff;
1817
1818 case 0x3c: /* DMA4_CCEN */
1819 return ch->active_set.element;
1820
1821 case 0x40: /* DMA4_CCFN */
1822 return ch->active_set.frame;
1823
1824 case 0x44: /* DMA4_COLOR */
1825 /* XXX only in sDMA */
1826 return ch->color;
1827
1828 default:
1829 OMAP_BAD_REG(addr);
1830 return 0;
1831 }
1832 }
1833
1834 static void omap_dma4_write(void *opaque, a_target_phys_addr addr,
1835 uint32_t value)
1836 {
1837 struct omap_dma_s *s = (struct omap_dma_s *) opaque;
1838 int chnum, irqn = 0;
1839 struct omap_dma_channel_s *ch;
1840
1841 switch (addr) {
1842 case 0x14: /* DMA4_IRQSTATUS_L3 */
1843 irqn ++;
1844 case 0x10: /* DMA4_IRQSTATUS_L2 */
1845 irqn ++;
1846 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1847 irqn ++;
1848 case 0x08: /* DMA4_IRQSTATUS_L0 */
1849 s->irqstat[irqn] &= ~value;
1850 if (!s->irqstat[irqn])
1851 qemu_irq_lower(s->irq[irqn]);
1852 return;
1853
1854 case 0x24: /* DMA4_IRQENABLE_L3 */
1855 irqn ++;
1856 case 0x20: /* DMA4_IRQENABLE_L2 */
1857 irqn ++;
1858 case 0x1c: /* DMA4_IRQENABLE_L1 */
1859 irqn ++;
1860 case 0x18: /* DMA4_IRQENABLE_L0 */
1861 s->irqen[irqn] = value;
1862 return;
1863
1864 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1865 if (value & 2) /* SOFTRESET */
1866 omap_dma_reset(s->dma);
1867 s->ocp = value & 0x3321;
1868 if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */
1869 fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__);
1870 return;
1871
1872 case 0x78: /* DMA4_GCR */
1873 s->gcr = value & 0x00ff00ff;
1874 if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1875 fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__);
1876 return;
1877
1878 case 0x80 ... 0xfff:
1879 addr -= 0x80;
1880 chnum = addr / 0x60;
1881 ch = s->ch + chnum;
1882 addr -= chnum * 0x60;
1883 break;
1884
1885 case 0x00: /* DMA4_REVISION */
1886 case 0x28: /* DMA4_SYSSTATUS */
1887 case 0x64: /* DMA4_CAPS_0 */
1888 case 0x6c: /* DMA4_CAPS_2 */
1889 case 0x70: /* DMA4_CAPS_3 */
1890 case 0x74: /* DMA4_CAPS_4 */
1891 OMAP_RO_REG(addr);
1892 return;
1893
1894 default:
1895 OMAP_BAD_REG(addr);
1896 return;
1897 }
1898
1899 /* Per-channel registers */
1900 switch (addr) {
1901 case 0x00: /* DMA4_CCR */
1902 ch->buf_disable = (value >> 25) & 1;
1903 ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */
1904 if (ch->buf_disable && !ch->src_sync)
1905 fprintf(stderr, "%s: Buffering disable is not allowed in "
1906 "destination synchronised mode\n", __FUNCTION__);
1907 ch->prefetch = (value >> 23) & 1;
1908 ch->bs = (value >> 18) & 1;
1909 ch->transparent_copy = (value >> 17) & 1;
1910 ch->constant_fill = (value >> 16) & 1;
1911 ch->mode[1] = (e_omap_dma_addressing) ((value & 0xc000) >> 14);
1912 ch->mode[0] = (e_omap_dma_addressing) ((value & 0x3000) >> 12);
1913 ch->suspend = (value & 0x0100) >> 8;
1914 ch->priority = (value & 0x0040) >> 6;
1915 ch->fs = (value & 0x0020) >> 5;
1916 if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1])
1917 fprintf(stderr, "%s: For a packet transfer at least one port "
1918 "must be constant-addressed\n", __FUNCTION__);
1919 ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060);
1920 /* XXX must be 0x01 for CamDMA */
1921
1922 if (value & 0x0080)
1923 omap_dma_enable_channel(s, ch);
1924 else
1925 omap_dma_disable_channel(s, ch);
1926
1927 break;
1928
1929 case 0x04: /* DMA4_CLNK_CTRL */
1930 ch->link_enabled = (value >> 15) & 0x1;
1931 ch->link_next_ch = value & 0x1f;
1932 break;
1933
1934 case 0x08: /* DMA4_CICR */
1935 ch->interrupts = value & 0x09be;
1936 break;
1937
1938 case 0x0c: /* DMA4_CSR */
1939 ch->cstatus &= ~value;
1940 break;
1941
1942 case 0x10: /* DMA4_CSDP */
1943 ch->endian[0] =(value >> 21) & 1;
1944 ch->endian_lock[0] =(value >> 20) & 1;
1945 ch->endian[1] =(value >> 19) & 1;
1946 ch->endian_lock[1] =(value >> 18) & 1;
1947 if (ch->endian[0] != ch->endian[1])
1948 fprintf(stderr, "%s: DMA endiannes conversion enable attempt\n",
1949 __FUNCTION__);
1950 ch->write_mode = (value >> 16) & 3;
1951 ch->burst[1] = (value & 0xc000) >> 14;
1952 ch->pack[1] = (value & 0x2000) >> 13;
1953 ch->translate[1] = (value & 0x1e00) >> 9;
1954 ch->burst[0] = (value & 0x0180) >> 7;
1955 ch->pack[0] = (value & 0x0040) >> 6;
1956 ch->translate[0] = (value & 0x003c) >> 2;
1957 if (ch->translate[0] | ch->translate[1])
1958 fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n",
1959 __FUNCTION__);
1960 ch->data_type = 1 << (value & 3);
1961 if ((value & 3) == 3)
1962 printf("%s: bad data_type for DMA channel\n", __FUNCTION__);
1963 break;
1964
1965 case 0x14: /* DMA4_CEN */
1966 ch->set_update = 1;
1967 ch->elements = value & 0xffffff;
1968 break;
1969
1970 case 0x18: /* DMA4_CFN */
1971 ch->frames = value & 0xffff;
1972 ch->set_update = 1;
1973 break;
1974
1975 case 0x1c: /* DMA4_CSSA */
1976 ch->addr[0] = (a_target_phys_addr) (uint32_t) value;
1977 ch->set_update = 1;
1978 break;
1979
1980 case 0x20: /* DMA4_CDSA */
1981 ch->addr[1] = (a_target_phys_addr) (uint32_t) value;
1982 ch->set_update = 1;
1983 break;
1984
1985 case 0x24: /* DMA4_CSEI */
1986 ch->element_index[0] = (int16_t) value;
1987 ch->set_update = 1;
1988 break;
1989
1990 case 0x28: /* DMA4_CSFI */
1991 ch->frame_index[0] = (int32_t) value;
1992 ch->set_update = 1;
1993 break;
1994
1995 case 0x2c: /* DMA4_CDEI */
1996 ch->element_index[1] = (int16_t) value;
1997 ch->set_update = 1;
1998 break;
1999
2000 case 0x30: /* DMA4_CDFI */
2001 ch->frame_index[1] = (int32_t) value;
2002 ch->set_update = 1;
2003 break;
2004
2005 case 0x44: /* DMA4_COLOR */
2006 /* XXX only in sDMA */
2007 ch->color = value;
2008 break;
2009
2010 case 0x34: /* DMA4_CSAC */
2011 case 0x38: /* DMA4_CDAC */
2012 case 0x3c: /* DMA4_CCEN */
2013 case 0x40: /* DMA4_CCFN */
2014 OMAP_RO_REG(addr);
2015 break;
2016
2017 default:
2018 OMAP_BAD_REG(addr);
2019 }
2020 }
2021
2022 static CPUReadMemoryFunc * const omap_dma4_readfn[] = {
2023 omap_badwidth_read16,
2024 omap_dma4_read,
2025 omap_dma4_read,
2026 };
2027
2028 static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
2029 omap_badwidth_write16,
2030 omap_dma4_write,
2031 omap_dma4_write,
2032 };
2033
2034 struct soc_dma_s *omap_dma4_init(a_target_phys_addr base, qemu_irq *irqs,
2035 struct omap_mpu_state_s *mpu, int fifo,
2036 int chans, omap_clk iclk, omap_clk fclk)
2037 {
2038 int iomemtype, i;
2039 struct omap_dma_s *s = (struct omap_dma_s *)
2040 qemu_mallocz(sizeof(struct omap_dma_s));
2041
2042 s->model = omap_dma_4;
2043 s->chans = chans;
2044 s->mpu = mpu;
2045 s->clk = fclk;
2046
2047 s->dma = soc_dma_init(s->chans);
2048 s->dma->freq = omap_clk_getrate(fclk);
2049 s->dma->transfer_fn = omap_dma_transfer_generic;
2050 s->dma->setup_fn = omap_dma_transfer_setup;
2051 s->dma->drq = qemu_allocate_irqs(omap_dma_request, s, 64);
2052 s->dma->opaque = s;
2053 for (i = 0; i < s->chans; i ++) {
2054 s->ch[i].dma = &s->dma->ch[i];
2055 s->dma->ch[i].opaque = &s->ch[i];
2056 }
2057
2058 memcpy(&s->irq, irqs, sizeof(s->irq));
2059 s->intr_update = omap_dma_interrupts_4_update;
2060
2061 omap_dma_setcaps(s);
2062 omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
2063 omap_dma_reset(s->dma);
2064 omap_dma_clk_update(s, 0, !!s->dma->freq);
2065
2066 iomemtype = cpu_register_io_memory(omap_dma4_readfn,
2067 omap_dma4_writefn, s);
2068 cpu_register_physical_memory(base, 0x1000, iomemtype);
2069
2070 mpu->drq = s->dma->drq;
2071
2072 return s->dma;
2073 }
2074
2075 struct omap_dma_lcd_channel_s *omap_dma_get_lcdch(struct soc_dma_s *dma)
2076 {
2077 struct omap_dma_s *s = dma->opaque;
2078
2079 return &s->lcd_ch;
2080 }
Qemu copy for testing