hw/omap_gpmc.c

   1 /*
   2  * TI OMAP general purpose memory controller emulation.
   3  *
   4  * Copyright (C) 2007-2009 Nokia Corporation
   5  * Original code written by Andrzej Zaborowski <andrew@openedhand.com>
   6  * Enhancements for OMAP3 and NAND support written by Juha Riihimäki
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) any later version of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "hw.h"
  22 #include "flash.h"
  23 #include "omap.h"
  24 #include "memory.h"
  25 #include "exec-memory.h"
  26
  27 /* General-Purpose Memory Controller */
  28 struct omap_gpmc_s {
  29     qemu_irq irq;
  30     qemu_irq drq;
  31     MemoryRegion iomem;
  32     int accept_256;
  33
  34     uint8_t revision;
  35     uint8_t sysconfig;
  36     uint16_t irqst;
  37     uint16_t irqen;
  38     uint16_t timeout;
  39     uint16_t config;
  40     struct omap_gpmc_cs_file_s {
  41         uint32_t config[7];
  42         MemoryRegion *iomem;
  43         MemoryRegion container;
  44         MemoryRegion nandiomem;
  45         DeviceState *dev;
  46     } cs_file[8];
  47     int ecc_cs;
  48     int ecc_ptr;
  49     uint32_t ecc_cfg;
  50     ECCState ecc[9];
  51     struct prefetch {
  52         uint32_t config1; /* GPMC_PREFETCH_CONFIG1 */
  53         uint32_t transfercount; /* GPMC_PREFETCH_CONFIG2:TRANSFERCOUNT */
  54         int startengine; /* GPMC_PREFETCH_CONTROL:STARTENGINE */
  55         int fifopointer; /* GPMC_PREFETCH_STATUS:FIFOPOINTER */
  56         int count; /* GPMC_PREFETCH_STATUS:COUNTVALUE */
  57     } prefetch;
  58 };
  59
  60 #define OMAP_GPMC_8BIT 0
  61 #define OMAP_GPMC_16BIT 1
  62 #define OMAP_GPMC_NOR 0
  63 #define OMAP_GPMC_NAND 2
  64
  65 static int omap_gpmc_devtype(struct omap_gpmc_cs_file_s *f)
  66 {
  67     return (f->config[0] >> 10) & 3;
  68 }
  69
  70 static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
  71 {
  72     /* devsize field is really 2 bits but we ignore the high
  73      * bit to ensure consistent behaviour if the guest sets
  74      * it (values 2 and 3 are reserved in the TRM)
  75      */
  76     return (f->config[0] >> 12) & 1;
  77 }
  78
  79 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
  80 {
  81     qemu_set_irq(s->irq, s->irqen & s->irqst);
  82 }
  83
  84 /* Access functions for when a NAND-like device is mapped into memory:
  85  * all addresses in the region behave like accesses to the relevant
  86  * GPMC_NAND_DATA_i register (which is actually implemented to call these)
  87  */
  88 static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
  89                                unsigned size)
  90 {
  91     struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
  92     uint64_t v;
  93     nand_setpins(f->dev, 0, 0, 0, 1, 0);
  94     switch (omap_gpmc_devsize(f)) {
  95     case OMAP_GPMC_8BIT:
  96         v = nand_getio(f->dev);
  97         if (size == 1) {
  98             return v;
  99         }
 100         v |= (nand_getio(f->dev) << 8);
 101         if (size == 2) {
 102             return v;
 103         }
 104         v |= (nand_getio(f->dev) << 16);
 105         v |= (nand_getio(f->dev) << 24);
 106         return v;
 107     case OMAP_GPMC_16BIT:
 108         v = nand_getio(f->dev);
 109         if (size == 1) {
 110             /* 8 bit read from 16 bit device : probably a guest bug */
 111             return v & 0xff;
 112         }
 113         if (size == 2) {
 114             return v;
 115         }
 116         v |= (nand_getio(f->dev) << 16);
 117         return v;
 118     default:
 119         abort();
 120     }
 121 }
 122
 123 static void omap_nand_setio(DeviceState *dev, uint64_t value,
 124                             int nandsize, int size)
 125 {
 126     /* Write the specified value to the NAND device, respecting
 127      * both size of the NAND device and size of the write access.
 128      */
 129     switch (nandsize) {
 130     case OMAP_GPMC_8BIT:
 131         switch (size) {
 132         case 1:
 133             nand_setio(dev, value & 0xff);
 134             break;
 135         case 2:
 136             nand_setio(dev, value & 0xff);
 137             nand_setio(dev, (value >> 8) & 0xff);
 138             break;
 139         case 4:
 140         default:
 141             nand_setio(dev, value & 0xff);
 142             nand_setio(dev, (value >> 8) & 0xff);
 143             nand_setio(dev, (value >> 16) & 0xff);
 144             nand_setio(dev, (value >> 24) & 0xff);
 145             break;
 146         }
 147     case OMAP_GPMC_16BIT:
 148         switch (size) {
 149         case 1:
 150             /* writing to a 16bit device with 8bit access is probably a guest
 151              * bug; pass the value through anyway.
 152              */
 153         case 2:
 154             nand_setio(dev, value & 0xffff);
 155             break;
 156         case 4:
 157         default:
 158             nand_setio(dev, value & 0xffff);
 159             nand_setio(dev, (value >> 16) & 0xffff);
 160             break;
 161         }
 162     }
 163 }
 164
 165 static void omap_nand_write(void *opaque, target_phys_addr_t addr,
 166                             uint64_t value, unsigned size)
 167 {
 168     struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
 169     nand_setpins(f->dev, 0, 0, 0, 1, 0);
 170     omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 171 }
 172
 173 static const MemoryRegionOps omap_nand_ops = {
 174     .read = omap_nand_read,
 175     .write = omap_nand_write,
 176     .endianness = DEVICE_NATIVE_ENDIAN,
 177 };
 178
 179 static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
 180 {
 181     /* Return the MemoryRegion* to map/unmap for this chipselect */
 182     struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
 183     if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
 184         return f->iomem;
 185     }
 186     return &f->nandiomem;
 187 }
 188
 189 static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
 190 {
 191     struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
 192     uint32_t mask = (f->config[6] >> 8) & 0xf;
 193     uint32_t base = f->config[6] & 0x3f;
 194     uint32_t size;
 195
 196     if (!f->iomem && !f->dev) {
 197         return;
 198     }
 199
 200     if (!(f->config[6] & (1 << 6))) {
 201         /* Do nothing unless CSVALID */
 202         return;
 203     }
 204
 205     /* TODO: check for overlapping regions and report access errors */
 206     if (mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf
 207          && !(s->accept_256 && !mask)) {
 208         fprintf(stderr, "%s: invalid chip-select mask address (0x%x)\n",
 209                  __func__, mask);
 210     }
 211
 212     base <<= 24;
 213     size = (0x0fffffff & ~(mask << 24)) + 1;
 214     /* TODO: rather than setting the size of the mapping (which should be
 215      * constant), the mask should cause wrapping of the address space, so
 216      * that the same memory becomes accessible at every <i>size</i> bytes
 217      * starting from <i>base</i>.  */
 218     memory_region_init(&f->container, "omap-gpmc-file", size);
 219     memory_region_add_subregion(&f->container, 0,
 220                                 omap_gpmc_cs_memregion(s, cs));
 221     memory_region_add_subregion(get_system_memory(), base,
 222                                 &f->container);
 223 }
 224
 225 static void omap_gpmc_cs_unmap(struct omap_gpmc_s *s, int cs)
 226 {
 227     struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
 228     if (!(f->config[6] & (1 << 6))) {
 229         /* Do nothing unless CSVALID */
 230         return;
 231     }
 232     if (!f->iomem && !f->dev) {
 233         return;
 234     }
 235     memory_region_del_subregion(get_system_memory(), &f->container);
 236     memory_region_del_subregion(&f->container, omap_gpmc_cs_memregion(s, cs));
 237     memory_region_destroy(&f->container);
 238 }
 239
 240 void omap_gpmc_reset(struct omap_gpmc_s *s)
 241 {
 242     int i;
 243
 244     s->sysconfig = 0;
 245     s->irqst = 0;
 246     s->irqen = 0;
 247     omap_gpmc_int_update(s);
 248     s->timeout = 0;
 249     s->config = 0xa00;
 250     s->prefetch.config1 = 0x00004000;
 251     s->prefetch.transfercount = 0x00000000;
 252     s->prefetch.startengine = 0;
 253     s->prefetch.fifopointer = 0;
 254     s->prefetch.count = 0;
 255     for (i = 0; i < 8; i ++) {
 256         omap_gpmc_cs_unmap(s, i);
 257         s->cs_file[i].config[1] = 0x101001;
 258         s->cs_file[i].config[2] = 0x020201;
 259         s->cs_file[i].config[3] = 0x10031003;
 260         s->cs_file[i].config[4] = 0x10f1111;
 261         s->cs_file[i].config[5] = 0;
 262         s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
 263
 264         s->cs_file[i].config[6] = 0xf00;
 265         /* In theory we could probe attached devices for some CFG1
 266          * bits here, but we just retain them across resets as they
 267          * were set initially by omap_gpmc_attach().
 268          */
 269         if (i == 0) {
 270             s->cs_file[i].config[0] &= 0x00433e00;
 271             s->cs_file[i].config[6] |= 1 << 6; /* CSVALID */
 272             omap_gpmc_cs_map(s, i);
 273         } else {
 274             s->cs_file[i].config[0] &= 0x00403c00;
 275         }
 276     }
 277     s->ecc_cs = 0;
 278     s->ecc_ptr = 0;
 279     s->ecc_cfg = 0x3fcff000;
 280     for (i = 0; i < 9; i ++)
 281         ecc_reset(&s->ecc[i]);
 282 }
 283
 284 static int gpmc_wordaccess_only(target_phys_addr_t addr)
 285 {
 286     /* Return true if the register offset is to a register that
 287      * only permits word width accesses.
 288      * Non-word accesses are only OK for GPMC_NAND_DATA/ADDRESS/COMMAND
 289      * for any chipselect.
 290      */
 291     if (addr >= 0x60 && addr <= 0x1d4) {
 292         int cs = (addr - 0x60) / 0x30;
 293         addr -= cs * 0x30;
 294         if (addr >= 0x7c && addr < 0x88) {
 295             /* GPMC_NAND_COMMAND, GPMC_NAND_ADDRESS, GPMC_NAND_DATA */
 296             return 0;
 297         }
 298     }
 299     return 1;
 300 }
 301
 302 static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
 303                                unsigned size)
 304 {
 305     struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
 306     int cs;
 307     struct omap_gpmc_cs_file_s *f;
 308
 309     if (size != 4 && gpmc_wordaccess_only(addr)) {
 310         return omap_badwidth_read32(opaque, addr);
 311     }
 312
 313     switch (addr) {
 314     case 0x000: /* GPMC_REVISION */
 315         return s->revision;
 316
 317     case 0x010: /* GPMC_SYSCONFIG */
 318         return s->sysconfig;
 319
 320     case 0x014: /* GPMC_SYSSTATUS */
 321         return 1;                                               /* RESETDONE */
 322
 323     case 0x018: /* GPMC_IRQSTATUS */
 324         return s->irqst;
 325
 326     case 0x01c: /* GPMC_IRQENABLE */
 327         return s->irqen;
 328
 329     case 0x040: /* GPMC_TIMEOUT_CONTROL */
 330         return s->timeout;
 331
 332     case 0x044: /* GPMC_ERR_ADDRESS */
 333     case 0x048: /* GPMC_ERR_TYPE */
 334         return 0;
 335
 336     case 0x050: /* GPMC_CONFIG */
 337         return s->config;
 338
 339     case 0x054: /* GPMC_STATUS */
 340         return 0x001;
 341
 342     case 0x060 ... 0x1d4:
 343         cs = (addr - 0x060) / 0x30;
 344         addr -= cs * 0x30;
 345         f = s->cs_file + cs;
 346         switch (addr) {
 347         case 0x60:      /* GPMC_CONFIG1 */
 348             return f->config[0];
 349         case 0x64:      /* GPMC_CONFIG2 */
 350             return f->config[1];
 351         case 0x68:      /* GPMC_CONFIG3 */
 352             return f->config[2];
 353         case 0x6c:      /* GPMC_CONFIG4 */
 354             return f->config[3];
 355         case 0x70:      /* GPMC_CONFIG5 */
 356             return f->config[4];
 357         case 0x74:      /* GPMC_CONFIG6 */
 358             return f->config[5];
 359         case 0x78:      /* GPMC_CONFIG7 */
 360             return f->config[6];
 361         case 0x84 ... 0x87: /* GPMC_NAND_DATA */
 362             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 363                 return omap_nand_read(f, 0, size);
 364             }
 365             return 0;
 366         }
 367         break;
 368
 369     case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
 370         return s->prefetch.config1;
 371     case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
 372         return s->prefetch.transfercount;
 373     case 0x1ec: /* GPMC_PREFETCH_CONTROL */
 374         return s->prefetch.startengine;
 375     case 0x1f0: /* GPMC_PREFETCH_STATUS */
 376         return (s->prefetch.fifopointer << 24) |
 377                 ((s->prefetch.fifopointer >=
 378                   ((s->prefetch.config1 >> 8) & 0x7f) ? 1 : 0) << 16) |
 379                 s->prefetch.count;
 380
 381     case 0x1f4: /* GPMC_ECC_CONFIG */
 382         return s->ecc_cs;
 383     case 0x1f8: /* GPMC_ECC_CONTROL */
 384         return s->ecc_ptr;
 385     case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
 386         return s->ecc_cfg;
 387     case 0x200 ... 0x220:       /* GPMC_ECC_RESULT */
 388         cs = (addr & 0x1f) >> 2;
 389         /* TODO: check correctness */
 390         return
 391                 ((s->ecc[cs].cp    &  0x07) <<  0) |
 392                 ((s->ecc[cs].cp    &  0x38) << 13) |
 393                 ((s->ecc[cs].lp[0] & 0x1ff) <<  3) |
 394                 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
 395
 396     case 0x230: /* GPMC_TESTMODE_CTRL */
 397         return 0;
 398     case 0x234: /* GPMC_PSA_LSB */
 399     case 0x238: /* GPMC_PSA_MSB */
 400         return 0x00000000;
 401     }
 402
 403     OMAP_BAD_REG(addr);
 404     return 0;
 405 }
 406
 407 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
 408                             uint64_t value, unsigned size)
 409 {
 410     struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
 411     int cs;
 412     struct omap_gpmc_cs_file_s *f;
 413
 414     if (size != 4 && gpmc_wordaccess_only(addr)) {
 415         return omap_badwidth_write32(opaque, addr, value);
 416     }
 417
 418     switch (addr) {
 419     case 0x000: /* GPMC_REVISION */
 420     case 0x014: /* GPMC_SYSSTATUS */
 421     case 0x054: /* GPMC_STATUS */
 422     case 0x1f0: /* GPMC_PREFETCH_STATUS */
 423     case 0x200 ... 0x220:       /* GPMC_ECC_RESULT */
 424     case 0x234: /* GPMC_PSA_LSB */
 425     case 0x238: /* GPMC_PSA_MSB */
 426         OMAP_RO_REG(addr);
 427         break;
 428
 429     case 0x010: /* GPMC_SYSCONFIG */
 430         if ((value >> 3) == 0x3)
 431             fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
 432                             __FUNCTION__, value >> 3);
 433         if (value & 2)
 434             omap_gpmc_reset(s);
 435         s->sysconfig = value & 0x19;
 436         break;
 437
 438     case 0x018: /* GPMC_IRQSTATUS */
 439         s->irqen &= ~value;
 440         omap_gpmc_int_update(s);
 441         break;
 442
 443     case 0x01c: /* GPMC_IRQENABLE */
 444         s->irqen = value & 0xf03;
 445         omap_gpmc_int_update(s);
 446         break;
 447
 448     case 0x040: /* GPMC_TIMEOUT_CONTROL */
 449         s->timeout = value & 0x1ff1;
 450         break;
 451
 452     case 0x044: /* GPMC_ERR_ADDRESS */
 453     case 0x048: /* GPMC_ERR_TYPE */
 454         break;
 455
 456     case 0x050: /* GPMC_CONFIG */
 457         s->config = value & 0xf13;
 458         break;
 459
 460     case 0x060 ... 0x1d4:
 461         cs = (addr - 0x060) / 0x30;
 462         addr -= cs * 0x30;
 463         f = s->cs_file + cs;
 464         switch (addr) {
 465         case 0x60:      /* GPMC_CONFIG1 */
 466             f->config[0] = value & 0xffef3e13;
 467             break;
 468         case 0x64:      /* GPMC_CONFIG2 */
 469             f->config[1] = value & 0x001f1f8f;
 470             break;
 471         case 0x68:      /* GPMC_CONFIG3 */
 472             f->config[2] = value & 0x001f1f8f;
 473             break;
 474         case 0x6c:      /* GPMC_CONFIG4 */
 475             f->config[3] = value & 0x1f8f1f8f;
 476             break;
 477         case 0x70:      /* GPMC_CONFIG5 */
 478             f->config[4] = value & 0x0f1f1f1f;
 479             break;
 480         case 0x74:      /* GPMC_CONFIG6 */
 481             f->config[5] = value & 0x00000fcf;
 482             break;
 483         case 0x78:      /* GPMC_CONFIG7 */
 484             if ((f->config[6] ^ value) & 0xf7f) {
 485                 omap_gpmc_cs_unmap(s, cs);
 486                 f->config[6] = value & 0x00000f7f;
 487                 omap_gpmc_cs_map(s, cs);
 488             }
 489             break;
 490         case 0x7c ... 0x7f: /* GPMC_NAND_COMMAND */
 491             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 492                 nand_setpins(f->dev, 1, 0, 0, 1, 0); /* CLE */
 493                 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 494             }
 495             break;
 496         case 0x80 ... 0x83: /* GPMC_NAND_ADDRESS */
 497             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 498                 nand_setpins(f->dev, 0, 1, 0, 1, 0); /* ALE */
 499                 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 500             }
 501             break;
 502         case 0x84 ... 0x87: /* GPMC_NAND_DATA */
 503             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 504                 omap_nand_write(f, 0, value, size);
 505             }
 506             break;
 507         default:
 508             goto bad_reg;
 509         }
 510         break;
 511
 512     case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
 513         s->prefetch.config1 = value & 0x7f8f7fbf;
 514         /* TODO: update interrupts, fifos, dmas */
 515         break;
 516
 517     case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
 518         s->prefetch.transfercount = value & 0x3fff;
 519         break;
 520
 521     case 0x1ec: /* GPMC_PREFETCH_CONTROL */
 522         s->prefetch.startengine = value & 1;
 523         if (s->prefetch.startengine) {
 524             if (s->prefetch.config1 & 1) {
 525                 s->prefetch.fifopointer = 0x40;
 526             } else {
 527                 s->prefetch.fifopointer = 0x00;
 528             }
 529         }
 530         /* TODO: start */
 531         break;
 532
 533     case 0x1f4: /* GPMC_ECC_CONFIG */
 534         s->ecc_cs = 0x8f;
 535         break;
 536     case 0x1f8: /* GPMC_ECC_CONTROL */
 537         if (value & (1 << 8))
 538             for (cs = 0; cs < 9; cs ++)
 539                 ecc_reset(&s->ecc[cs]);
 540         s->ecc_ptr = value & 0xf;
 541         if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
 542             s->ecc_ptr = 0;
 543             s->ecc_cs &= ~1;
 544         }
 545         break;
 546     case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
 547         s->ecc_cfg = value & 0x3fcff1ff;
 548         break;
 549     case 0x230: /* GPMC_TESTMODE_CTRL */
 550         if (value & 7)
 551             fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
 552         break;
 553
 554     default:
 555     bad_reg:
 556         OMAP_BAD_REG(addr);
 557         return;
 558     }
 559 }
 560
 561 static const MemoryRegionOps omap_gpmc_ops = {
 562     .read = omap_gpmc_read,
 563     .write = omap_gpmc_write,
 564     .endianness = DEVICE_NATIVE_ENDIAN,
 565 };
 566
 567 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
 568                                    target_phys_addr_t base,
 569                                    qemu_irq irq, qemu_irq drq)
 570 {
 571     int cs;
 572     struct omap_gpmc_s *s = (struct omap_gpmc_s *)
 573             g_malloc0(sizeof(struct omap_gpmc_s));
 574
 575     memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
 576     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 577
 578     s->irq = irq;
 579     s->drq = drq;
 580     s->accept_256 = cpu_is_omap3630(mpu);
 581     s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
 582     omap_gpmc_reset(s);
 583
 584     /* We have to register a different IO memory handler for each
 585      * chip select region in case a NAND device is mapped there. We
 586      * make the region the worst-case size of 256MB and rely on the
 587      * container memory region in cs_map to chop it down to the actual
 588      * guest-requested size.
 589      */
 590     for (cs = 0; cs < 8; cs++) {
 591         memory_region_init_io(&s->cs_file[cs].nandiomem,
 592                               &omap_nand_ops,
 593                               &s->cs_file[cs],
 594                               "omap-nand",
 595                               256 * 1024 * 1024);
 596     }
 597     return s;
 598 }
 599
 600 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem)
 601 {
 602     struct omap_gpmc_cs_file_s *f;
 603     assert(iomem);
 604
 605     if (cs < 0 || cs >= 8) {
 606         fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
 607         exit(-1);
 608     }
 609     f = &s->cs_file[cs];
 610
 611     omap_gpmc_cs_unmap(s, cs);
 612     f->config[0] &= ~(0xf << 10);
 613     f->iomem = iomem;
 614     omap_gpmc_cs_map(s, cs);
 615 }
 616
 617 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand)
 618 {
 619     struct omap_gpmc_cs_file_s *f;
 620     assert(nand);
 621
 622     if (cs < 0 || cs >= 8) {
 623         fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
 624         exit(-1);
 625     }
 626     f = &s->cs_file[cs];
 627
 628     omap_gpmc_cs_unmap(s, cs);
 629     f->config[0] &= ~(0xf << 10);
 630     f->config[0] |= (OMAP_GPMC_NAND << 10);
 631     f->dev = nand;
 632     if (nand_getbuswidth(f->dev) == 16) {
 633         f->config[0] |= OMAP_GPMC_16BIT << 12;
 634     }
 635     omap_gpmc_cs_map(s, cs);
 636 }