hw/omap_gpmc.c

   1 /*
   2  * TI OMAP general purpose memory controller emulation.
   3  *
   4  * Copyright (C) 2007-2009 Nokia Corporation
   5  * Original code written by Andrzej Zaborowski <andrew@openedhand.com>
   6  * Enhancements for OMAP3 and NAND support written by Juha Riihimäki
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) any later version of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21 #include "hw.h"
  22 #include "flash.h"
  23 #include "omap.h"
  24 #include "memory.h"
  25 #include "exec-memory.h"
  26
  27 /* General-Purpose Memory Controller */
  28 struct omap_gpmc_s {
  29     qemu_irq irq;
  30     MemoryRegion iomem;
  31     int accept_256;
  32
  33     uint8_t revision;
  34     uint8_t sysconfig;
  35     uint16_t irqst;
  36     uint16_t irqen;
  37     uint16_t timeout;
  38     uint16_t config;
  39     struct omap_gpmc_cs_file_s {
  40         uint32_t config[7];
  41         MemoryRegion *iomem;
  42         MemoryRegion container;
  43         MemoryRegion nandiomem;
  44         DeviceState *dev;
  45     } cs_file[8];
  46     int ecc_cs;
  47     int ecc_ptr;
  48     uint32_t ecc_cfg;
  49     ECCState ecc[9];
  50     struct prefetch {
  51         uint32_t config1; /* GPMC_PREFETCH_CONFIG1 */
  52         uint32_t transfercount; /* GPMC_PREFETCH_CONFIG2:TRANSFERCOUNT */
  53         int startengine; /* GPMC_PREFETCH_CONTROL:STARTENGINE */
  54         int fifopointer; /* GPMC_PREFETCH_STATUS:FIFOPOINTER */
  55         int count; /* GPMC_PREFETCH_STATUS:COUNTVALUE */
  56     } prefetch;
  57 };
  58
  59 #define OMAP_GPMC_8BIT 0
  60 #define OMAP_GPMC_16BIT 1
  61 #define OMAP_GPMC_NOR 0
  62 #define OMAP_GPMC_NAND 2
  63
  64 static int omap_gpmc_devtype(struct omap_gpmc_cs_file_s *f)
  65 {
  66     return (f->config[0] >> 10) & 3;
  67 }
  68
  69 static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
  70 {
  71     /* devsize field is really 2 bits but we ignore the high
  72      * bit to ensure consistent behaviour if the guest sets
  73      * it (values 2 and 3 are reserved in the TRM)
  74      */
  75     return (f->config[0] >> 12) & 1;
  76 }
  77
  78 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
  79 {
  80     qemu_set_irq(s->irq, s->irqen & s->irqst);
  81 }
  82
  83 /* Access functions for when a NAND-like device is mapped into memory:
  84  * all addresses in the region behave like accesses to the relevant
  85  * GPMC_NAND_DATA_i register (which is actually implemented to call these)
  86  */
  87 static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
  88                                unsigned size)
  89 {
  90     struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
  91     uint64_t v;
  92     nand_setpins(f->dev, 0, 0, 0, 1, 0);
  93     switch (omap_gpmc_devsize(f)) {
  94     case OMAP_GPMC_8BIT:
  95         v = nand_getio(f->dev);
  96         if (size == 1) {
  97             return v;
  98         }
  99         v |= (nand_getio(f->dev) << 8);
 100         if (size == 2) {
 101             return v;
 102         }
 103         v |= (nand_getio(f->dev) << 16);
 104         v |= (nand_getio(f->dev) << 24);
 105         return v;
 106     case OMAP_GPMC_16BIT:
 107         v = nand_getio(f->dev);
 108         if (size == 1) {
 109             /* 8 bit read from 16 bit device : probably a guest bug */
 110             return v & 0xff;
 111         }
 112         if (size == 2) {
 113             return v;
 114         }
 115         v |= (nand_getio(f->dev) << 16);
 116         return v;
 117     default:
 118         abort();
 119     }
 120 }
 121
 122 static void omap_nand_setio(DeviceState *dev, uint64_t value,
 123                             int nandsize, int size)
 124 {
 125     /* Write the specified value to the NAND device, respecting
 126      * both size of the NAND device and size of the write access.
 127      */
 128     switch (nandsize) {
 129     case OMAP_GPMC_8BIT:
 130         switch (size) {
 131         case 1:
 132             nand_setio(dev, value & 0xff);
 133             break;
 134         case 2:
 135             nand_setio(dev, value & 0xff);
 136             nand_setio(dev, (value >> 8) & 0xff);
 137             break;
 138         case 4:
 139         default:
 140             nand_setio(dev, value & 0xff);
 141             nand_setio(dev, (value >> 8) & 0xff);
 142             nand_setio(dev, (value >> 16) & 0xff);
 143             nand_setio(dev, (value >> 24) & 0xff);
 144             break;
 145         }
 146     case OMAP_GPMC_16BIT:
 147         switch (size) {
 148         case 1:
 149             /* writing to a 16bit device with 8bit access is probably a guest
 150              * bug; pass the value through anyway.
 151              */
 152         case 2:
 153             nand_setio(dev, value & 0xffff);
 154             break;
 155         case 4:
 156         default:
 157             nand_setio(dev, value & 0xffff);
 158             nand_setio(dev, (value >> 16) & 0xffff);
 159             break;
 160         }
 161     }
 162 }
 163
 164 static void omap_nand_write(void *opaque, target_phys_addr_t addr,
 165                             uint64_t value, unsigned size)
 166 {
 167     struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
 168     nand_setpins(f->dev, 0, 0, 0, 1, 0);
 169     omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 170 }
 171
 172 static const MemoryRegionOps omap_nand_ops = {
 173     .read = omap_nand_read,
 174     .write = omap_nand_write,
 175     .endianness = DEVICE_NATIVE_ENDIAN,
 176 };
 177
 178 static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
 179 {
 180     /* Return the MemoryRegion* to map/unmap for this chipselect */
 181     struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
 182     if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
 183         return f->iomem;
 184     }
 185     return &f->nandiomem;
 186 }
 187
 188 static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
 189 {
 190     struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
 191     uint32_t mask = (f->config[6] >> 8) & 0xf;
 192     uint32_t base = f->config[6] & 0x3f;
 193     uint32_t size;
 194
 195     if (!f->iomem && !f->dev) {
 196         return;
 197     }
 198
 199     if (!(f->config[6] & (1 << 6))) {
 200         /* Do nothing unless CSVALID */
 201         return;
 202     }
 203
 204     /* TODO: check for overlapping regions and report access errors */
 205     if (mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf
 206          && !(s->accept_256 && !mask)) {
 207         fprintf(stderr, "%s: invalid chip-select mask address (0x%x)\n",
 208                  __func__, mask);
 209     }
 210
 211     base <<= 24;
 212     size = (0x0fffffff & ~(mask << 24)) + 1;
 213     /* TODO: rather than setting the size of the mapping (which should be
 214      * constant), the mask should cause wrapping of the address space, so
 215      * that the same memory becomes accessible at every <i>size</i> bytes
 216      * starting from <i>base</i>.  */
 217     memory_region_init(&f->container, "omap-gpmc-file", size);
 218     memory_region_add_subregion(&f->container, 0,
 219                                 omap_gpmc_cs_memregion(s, cs));
 220     memory_region_add_subregion(get_system_memory(), base,
 221                                 &f->container);
 222 }
 223
 224 static void omap_gpmc_cs_unmap(struct omap_gpmc_s *s, int cs)
 225 {
 226     struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
 227     if (!(f->config[6] & (1 << 6))) {
 228         /* Do nothing unless CSVALID */
 229         return;
 230     }
 231     if (!f->iomem && !f->dev) {
 232         return;
 233     }
 234     memory_region_del_subregion(get_system_memory(), &f->container);
 235     memory_region_del_subregion(&f->container, omap_gpmc_cs_memregion(s, cs));
 236     memory_region_destroy(&f->container);
 237 }
 238
 239 void omap_gpmc_reset(struct omap_gpmc_s *s)
 240 {
 241     int i;
 242
 243     s->sysconfig = 0;
 244     s->irqst = 0;
 245     s->irqen = 0;
 246     omap_gpmc_int_update(s);
 247     s->timeout = 0;
 248     s->config = 0xa00;
 249     s->prefetch.config1 = 0x00004000;
 250     s->prefetch.transfercount = 0x00000000;
 251     s->prefetch.startengine = 0;
 252     s->prefetch.fifopointer = 0;
 253     s->prefetch.count = 0;
 254     for (i = 0; i < 8; i ++) {
 255         omap_gpmc_cs_unmap(s, i);
 256         s->cs_file[i].config[1] = 0x101001;
 257         s->cs_file[i].config[2] = 0x020201;
 258         s->cs_file[i].config[3] = 0x10031003;
 259         s->cs_file[i].config[4] = 0x10f1111;
 260         s->cs_file[i].config[5] = 0;
 261         s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
 262
 263         s->cs_file[i].config[6] = 0xf00;
 264         /* In theory we could probe attached devices for some CFG1
 265          * bits here, but we just retain them across resets as they
 266          * were set initially by omap_gpmc_attach().
 267          */
 268         if (i == 0) {
 269             s->cs_file[i].config[0] &= 0x00433e00;
 270             s->cs_file[i].config[6] |= 1 << 6; /* CSVALID */
 271             omap_gpmc_cs_map(s, i);
 272         } else {
 273             s->cs_file[i].config[0] &= 0x00403c00;
 274         }
 275     }
 276     s->ecc_cs = 0;
 277     s->ecc_ptr = 0;
 278     s->ecc_cfg = 0x3fcff000;
 279     for (i = 0; i < 9; i ++)
 280         ecc_reset(&s->ecc[i]);
 281 }
 282
 283 static int gpmc_wordaccess_only(target_phys_addr_t addr)
 284 {
 285     /* Return true if the register offset is to a register that
 286      * only permits word width accesses.
 287      * Non-word accesses are only OK for GPMC_NAND_DATA/ADDRESS/COMMAND
 288      * for any chipselect.
 289      */
 290     if (addr >= 0x60 && addr <= 0x1d4) {
 291         int cs = (addr - 0x60) / 0x30;
 292         addr -= cs * 0x30;
 293         if (addr >= 0x7c && addr < 0x88) {
 294             /* GPMC_NAND_COMMAND, GPMC_NAND_ADDRESS, GPMC_NAND_DATA */
 295             return 0;
 296         }
 297     }
 298     return 1;
 299 }
 300
 301 static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
 302                                unsigned size)
 303 {
 304     struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
 305     int cs;
 306     struct omap_gpmc_cs_file_s *f;
 307
 308     if (size != 4 && gpmc_wordaccess_only(addr)) {
 309         return omap_badwidth_read32(opaque, addr);
 310     }
 311
 312     switch (addr) {
 313     case 0x000: /* GPMC_REVISION */
 314         return s->revision;
 315
 316     case 0x010: /* GPMC_SYSCONFIG */
 317         return s->sysconfig;
 318
 319     case 0x014: /* GPMC_SYSSTATUS */
 320         return 1;                                               /* RESETDONE */
 321
 322     case 0x018: /* GPMC_IRQSTATUS */
 323         return s->irqst;
 324
 325     case 0x01c: /* GPMC_IRQENABLE */
 326         return s->irqen;
 327
 328     case 0x040: /* GPMC_TIMEOUT_CONTROL */
 329         return s->timeout;
 330
 331     case 0x044: /* GPMC_ERR_ADDRESS */
 332     case 0x048: /* GPMC_ERR_TYPE */
 333         return 0;
 334
 335     case 0x050: /* GPMC_CONFIG */
 336         return s->config;
 337
 338     case 0x054: /* GPMC_STATUS */
 339         return 0x001;
 340
 341     case 0x060 ... 0x1d4:
 342         cs = (addr - 0x060) / 0x30;
 343         addr -= cs * 0x30;
 344         f = s->cs_file + cs;
 345         switch (addr) {
 346         case 0x60:      /* GPMC_CONFIG1 */
 347             return f->config[0];
 348         case 0x64:      /* GPMC_CONFIG2 */
 349             return f->config[1];
 350         case 0x68:      /* GPMC_CONFIG3 */
 351             return f->config[2];
 352         case 0x6c:      /* GPMC_CONFIG4 */
 353             return f->config[3];
 354         case 0x70:      /* GPMC_CONFIG5 */
 355             return f->config[4];
 356         case 0x74:      /* GPMC_CONFIG6 */
 357             return f->config[5];
 358         case 0x78:      /* GPMC_CONFIG7 */
 359             return f->config[6];
 360         case 0x84 ... 0x87: /* GPMC_NAND_DATA */
 361             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 362                 return omap_nand_read(f, 0, size);
 363             }
 364             return 0;
 365         }
 366         break;
 367
 368     case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
 369         return s->prefetch.config1;
 370     case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
 371         return s->prefetch.transfercount;
 372     case 0x1ec: /* GPMC_PREFETCH_CONTROL */
 373         return s->prefetch.startengine;
 374     case 0x1f0: /* GPMC_PREFETCH_STATUS */
 375         return (s->prefetch.fifopointer << 24) |
 376                 ((s->prefetch.fifopointer >=
 377                   ((s->prefetch.config1 >> 8) & 0x7f) ? 1 : 0) << 16) |
 378                 s->prefetch.count;
 379
 380     case 0x1f4: /* GPMC_ECC_CONFIG */
 381         return s->ecc_cs;
 382     case 0x1f8: /* GPMC_ECC_CONTROL */
 383         return s->ecc_ptr;
 384     case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
 385         return s->ecc_cfg;
 386     case 0x200 ... 0x220:       /* GPMC_ECC_RESULT */
 387         cs = (addr & 0x1f) >> 2;
 388         /* TODO: check correctness */
 389         return
 390                 ((s->ecc[cs].cp    &  0x07) <<  0) |
 391                 ((s->ecc[cs].cp    &  0x38) << 13) |
 392                 ((s->ecc[cs].lp[0] & 0x1ff) <<  3) |
 393                 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
 394
 395     case 0x230: /* GPMC_TESTMODE_CTRL */
 396         return 0;
 397     case 0x234: /* GPMC_PSA_LSB */
 398     case 0x238: /* GPMC_PSA_MSB */
 399         return 0x00000000;
 400     }
 401
 402     OMAP_BAD_REG(addr);
 403     return 0;
 404 }
 405
 406 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
 407                             uint64_t value, unsigned size)
 408 {
 409     struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
 410     int cs;
 411     struct omap_gpmc_cs_file_s *f;
 412
 413     if (size != 4 && gpmc_wordaccess_only(addr)) {
 414         return omap_badwidth_write32(opaque, addr, value);
 415     }
 416
 417     switch (addr) {
 418     case 0x000: /* GPMC_REVISION */
 419     case 0x014: /* GPMC_SYSSTATUS */
 420     case 0x054: /* GPMC_STATUS */
 421     case 0x1f0: /* GPMC_PREFETCH_STATUS */
 422     case 0x200 ... 0x220:       /* GPMC_ECC_RESULT */
 423     case 0x234: /* GPMC_PSA_LSB */
 424     case 0x238: /* GPMC_PSA_MSB */
 425         OMAP_RO_REG(addr);
 426         break;
 427
 428     case 0x010: /* GPMC_SYSCONFIG */
 429         if ((value >> 3) == 0x3)
 430             fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
 431                             __FUNCTION__, value >> 3);
 432         if (value & 2)
 433             omap_gpmc_reset(s);
 434         s->sysconfig = value & 0x19;
 435         break;
 436
 437     case 0x018: /* GPMC_IRQSTATUS */
 438         s->irqen &= ~value;
 439         omap_gpmc_int_update(s);
 440         break;
 441
 442     case 0x01c: /* GPMC_IRQENABLE */
 443         s->irqen = value & 0xf03;
 444         omap_gpmc_int_update(s);
 445         break;
 446
 447     case 0x040: /* GPMC_TIMEOUT_CONTROL */
 448         s->timeout = value & 0x1ff1;
 449         break;
 450
 451     case 0x044: /* GPMC_ERR_ADDRESS */
 452     case 0x048: /* GPMC_ERR_TYPE */
 453         break;
 454
 455     case 0x050: /* GPMC_CONFIG */
 456         s->config = value & 0xf13;
 457         break;
 458
 459     case 0x060 ... 0x1d4:
 460         cs = (addr - 0x060) / 0x30;
 461         addr -= cs * 0x30;
 462         f = s->cs_file + cs;
 463         switch (addr) {
 464         case 0x60:      /* GPMC_CONFIG1 */
 465             f->config[0] = value & 0xffef3e13;
 466             break;
 467         case 0x64:      /* GPMC_CONFIG2 */
 468             f->config[1] = value & 0x001f1f8f;
 469             break;
 470         case 0x68:      /* GPMC_CONFIG3 */
 471             f->config[2] = value & 0x001f1f8f;
 472             break;
 473         case 0x6c:      /* GPMC_CONFIG4 */
 474             f->config[3] = value & 0x1f8f1f8f;
 475             break;
 476         case 0x70:      /* GPMC_CONFIG5 */
 477             f->config[4] = value & 0x0f1f1f1f;
 478             break;
 479         case 0x74:      /* GPMC_CONFIG6 */
 480             f->config[5] = value & 0x00000fcf;
 481             break;
 482         case 0x78:      /* GPMC_CONFIG7 */
 483             if ((f->config[6] ^ value) & 0xf7f) {
 484                 omap_gpmc_cs_unmap(s, cs);
 485                 f->config[6] = value & 0x00000f7f;
 486                 omap_gpmc_cs_map(s, cs);
 487             }
 488             break;
 489         case 0x7c ... 0x7f: /* GPMC_NAND_COMMAND */
 490             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 491                 nand_setpins(f->dev, 1, 0, 0, 1, 0); /* CLE */
 492                 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 493             }
 494             break;
 495         case 0x80 ... 0x83: /* GPMC_NAND_ADDRESS */
 496             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 497                 nand_setpins(f->dev, 0, 1, 0, 1, 0); /* ALE */
 498                 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
 499             }
 500             break;
 501         case 0x84 ... 0x87: /* GPMC_NAND_DATA */
 502             if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
 503                 omap_nand_write(f, 0, value, size);
 504             }
 505             break;
 506         default:
 507             goto bad_reg;
 508         }
 509         break;
 510
 511     case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
 512         s->prefetch.config1 = value & 0x7f8f7fbf;
 513         /* TODO: update interrupts, fifos, dmas */
 514         break;
 515
 516     case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
 517         s->prefetch.transfercount = value & 0x3fff;
 518         break;
 519
 520     case 0x1ec: /* GPMC_PREFETCH_CONTROL */
 521         s->prefetch.startengine = value & 1;
 522         if (s->prefetch.startengine) {
 523             if (s->prefetch.config1 & 1) {
 524                 s->prefetch.fifopointer = 0x40;
 525             } else {
 526                 s->prefetch.fifopointer = 0x00;
 527             }
 528         }
 529         /* TODO: start */
 530         break;
 531
 532     case 0x1f4: /* GPMC_ECC_CONFIG */
 533         s->ecc_cs = 0x8f;
 534         break;
 535     case 0x1f8: /* GPMC_ECC_CONTROL */
 536         if (value & (1 << 8))
 537             for (cs = 0; cs < 9; cs ++)
 538                 ecc_reset(&s->ecc[cs]);
 539         s->ecc_ptr = value & 0xf;
 540         if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
 541             s->ecc_ptr = 0;
 542             s->ecc_cs &= ~1;
 543         }
 544         break;
 545     case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
 546         s->ecc_cfg = value & 0x3fcff1ff;
 547         break;
 548     case 0x230: /* GPMC_TESTMODE_CTRL */
 549         if (value & 7)
 550             fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
 551         break;
 552
 553     default:
 554     bad_reg:
 555         OMAP_BAD_REG(addr);
 556         return;
 557     }
 558 }
 559
 560 static const MemoryRegionOps omap_gpmc_ops = {
 561     .read = omap_gpmc_read,
 562     .write = omap_gpmc_write,
 563     .endianness = DEVICE_NATIVE_ENDIAN,
 564 };
 565
 566 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
 567                                    target_phys_addr_t base, qemu_irq irq)
 568 {
 569     int cs;
 570     struct omap_gpmc_s *s = (struct omap_gpmc_s *)
 571             g_malloc0(sizeof(struct omap_gpmc_s));
 572
 573     memory_region_init_io(&s->iomem, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
 574     memory_region_add_subregion(get_system_memory(), base, &s->iomem);
 575
 576     s->irq = irq;
 577     s->accept_256 = cpu_is_omap3630(mpu);
 578     s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
 579     omap_gpmc_reset(s);
 580
 581     /* We have to register a different IO memory handler for each
 582      * chip select region in case a NAND device is mapped there. We
 583      * make the region the worst-case size of 256MB and rely on the
 584      * container memory region in cs_map to chop it down to the actual
 585      * guest-requested size.
 586      */
 587     for (cs = 0; cs < 8; cs++) {
 588         memory_region_init_io(&s->cs_file[cs].nandiomem,
 589                               &omap_nand_ops,
 590                               &s->cs_file[cs],
 591                               "omap-nand",
 592                               256 * 1024 * 1024);
 593     }
 594     return s;
 595 }
 596
 597 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem)
 598 {
 599     struct omap_gpmc_cs_file_s *f;
 600     assert(iomem);
 601
 602     if (cs < 0 || cs >= 8) {
 603         fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
 604         exit(-1);
 605     }
 606     f = &s->cs_file[cs];
 607
 608     omap_gpmc_cs_unmap(s, cs);
 609     f->config[0] &= ~(0xf << 10);
 610     f->iomem = iomem;
 611     omap_gpmc_cs_map(s, cs);
 612 }
 613
 614 void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand)
 615 {
 616     struct omap_gpmc_cs_file_s *f;
 617     assert(nand);
 618
 619     if (cs < 0 || cs >= 8) {
 620         fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
 621         exit(-1);
 622     }
 623     f = &s->cs_file[cs];
 624
 625     omap_gpmc_cs_unmap(s, cs);
 626     f->config[0] &= ~(0xf << 10);
 627     f->config[0] |= (OMAP_GPMC_NAND << 10);
 628     f->dev = nand;
 629     if (nand_getbuswidth(f->dev) == 16) {
 630         f->config[0] |= OMAP_GPMC_16BIT << 12;
 631     }
 632     omap_gpmc_cs_map(s, cs);
 633 }