4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
41 //#define DEBUG_OPENPIC
44 #define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
46 #define DPRINTF(fmt, ...) do { } while (0)
54 #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
55 #define VID 0x03 /* MPIC version ID */
56 #define VENI 0x00000000 /* Vendor ID */
64 #define OPENPIC_MAX_CPU 2
65 #define OPENPIC_MAX_IRQ 64
66 #define OPENPIC_EXT_IRQ 48
67 #define OPENPIC_MAX_TMR MAX_TMR
68 #define OPENPIC_MAX_IPI MAX_IPI
70 /* Interrupt definitions */
71 #define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
72 #define OPENPIC_IRQ_ERR (OPENPIC_EXT_IRQ + 1) /* Error IRQ */
73 #define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
74 #if OPENPIC_MAX_IPI > 0
75 #define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI IRQ */
76 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * OPENPIC_MAX_IPI)) /* First doorbell IRQ */
78 #define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First doorbell IRQ */
79 #define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First mailbox IRQ */
82 #define OPENPIC_GLB_REG_START 0x0
83 #define OPENPIC_GLB_REG_SIZE 0x10F0
84 #define OPENPIC_TMR_REG_START 0x10F0
85 #define OPENPIC_TMR_REG_SIZE 0x220
86 #define OPENPIC_SRC_REG_START 0x10000
87 #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
88 #define OPENPIC_CPU_REG_START 0x20000
89 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
92 #define MPIC_MAX_CPU 1
93 #define MPIC_MAX_EXT 12
94 #define MPIC_MAX_INT 64
95 #define MPIC_MAX_IRQ MAX_IRQ
97 /* Interrupt definitions */
98 /* IRQs, accessible through the IRQ region */
99 #define MPIC_EXT_IRQ 0x00
100 #define MPIC_INT_IRQ 0x10
101 #define MPIC_MSG_IRQ 0xb0
102 #define MPIC_MSI_IRQ 0xe0
103 /* These are available through separate regions, but
104 for simplicity's sake mapped into the same number space */
105 #define MPIC_TMR_IRQ 0x100
106 #define MPIC_IPI_IRQ 0x104
108 #define MPIC_GLB_REG_START 0x0
109 #define MPIC_GLB_REG_SIZE 0x10F0
110 #define MPIC_TMR_REG_START 0x10F0
111 #define MPIC_TMR_REG_SIZE 0x220
112 #define MPIC_SRC_REG_START 0x10000
113 #define MPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
114 #define MPIC_CPU_REG_START 0x20000
115 #define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
118 * Block Revision Register1 (BRR1): QEMU does not fully emulate
119 * any version on MPIC. So to start with, set the IP version to 0.
121 * NOTE: This is Freescale MPIC specific register. Keep it here till
122 * this code is refactored for different variants of OPENPIC and MPIC.
124 #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */
125 #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
126 #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
136 #define BF_WIDTH(_bits_) \
137 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
139 static inline void set_bit (uint32_t *field
, int bit
)
141 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
144 static inline void reset_bit (uint32_t *field
, int bit
)
146 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
149 static inline int test_bit (uint32_t *field
, int bit
)
151 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
154 static int get_current_cpu(void)
156 return cpu_single_env
->cpu_index
;
159 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
161 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
162 uint32_t val
, int idx
);
171 typedef struct IRQ_queue_t
{
172 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
177 typedef struct IRQ_src_t
{
178 uint32_t ipvp
; /* IRQ vector/priority register */
179 uint32_t ide
; /* IRQ destination register */
182 int pending
; /* TRUE if IRQ is pending */
192 #define IPVP_PRIORITY_MASK (0x1F << 16)
193 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
194 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
195 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
197 typedef struct IRQ_dst_t
{
199 uint32_t pctp
; /* CPU current task priority */
200 uint32_t pcsr
; /* CPU sensitivity register */
202 IRQ_queue_t servicing
;
206 typedef struct openpic_t
{
210 /* Behavior control */
214 MemoryRegion sub_io_mem
[7];
216 /* Global registers */
217 uint32_t frep
; /* Feature reporting register */
218 uint32_t glbc
; /* Global configuration register */
219 uint32_t micr
; /* MPIC interrupt configuration register */
220 uint32_t veni
; /* Vendor identification register */
221 uint32_t pint
; /* Processor initialization register */
222 uint32_t spve
; /* Spurious vector register */
223 uint32_t tifr
; /* Timer frequency reporting register */
224 /* Source registers */
225 IRQ_src_t src
[MAX_IRQ
];
226 /* Local registers per output pin */
227 IRQ_dst_t dst
[MAX_CPU
];
229 /* Timer registers */
231 uint32_t ticc
; /* Global timer current count register */
232 uint32_t tibc
; /* Global timer base count register */
234 /* IRQ out is used when in bypass mode (not implemented) */
239 void (*reset
) (void *);
242 static void openpic_irq_raise(openpic_t
*opp
, int n_CPU
, IRQ_src_t
*src
);
244 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
246 set_bit(q
->queue
, n_IRQ
);
249 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
251 reset_bit(q
->queue
, n_IRQ
);
254 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
256 return test_bit(q
->queue
, n_IRQ
);
259 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
266 for (i
= 0; i
< opp
->max_irq
; i
++) {
267 if (IRQ_testbit(q
, i
)) {
268 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
269 i
, IPVP_PRIORITY(opp
->src
[i
].ipvp
), priority
);
270 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
272 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
277 q
->priority
= priority
;
280 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
290 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
296 dst
= &opp
->dst
[n_CPU
];
297 src
= &opp
->src
[n_IRQ
];
298 priority
= IPVP_PRIORITY(src
->ipvp
);
299 if (priority
<= dst
->pctp
) {
300 /* Too low priority */
301 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
302 __func__
, n_IRQ
, n_CPU
);
305 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
307 DPRINTF("%s: IRQ %d was missed on CPU %d\n",
308 __func__
, n_IRQ
, n_CPU
);
311 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
312 IRQ_setbit(&dst
->raised
, n_IRQ
);
313 if (priority
< dst
->raised
.priority
) {
314 /* An higher priority IRQ is already raised */
315 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n",
316 __func__
, n_IRQ
, dst
->raised
.next
, n_CPU
);
319 IRQ_get_next(opp
, &dst
->raised
);
320 if (IRQ_get_next(opp
, &dst
->servicing
) != -1 &&
321 priority
<= dst
->servicing
.priority
) {
322 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
323 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
324 /* Already servicing a higher priority IRQ */
327 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU
, n_IRQ
);
328 openpic_irq_raise(opp
, n_CPU
, src
);
331 /* update pic state because registers for n_IRQ have changed value */
332 static void openpic_update_irq(openpic_t
*opp
, int n_IRQ
)
337 src
= &opp
->src
[n_IRQ
];
341 DPRINTF("%s: IRQ %d is not pending\n", __func__
, n_IRQ
);
344 if (test_bit(&src
->ipvp
, IPVP_MASK
)) {
345 /* Interrupt source is disabled */
346 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
349 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
350 /* Priority set to zero */
351 DPRINTF("%s: IRQ %d has 0 priority\n", __func__
, n_IRQ
);
354 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
355 /* IRQ already active */
356 DPRINTF("%s: IRQ %d is already active\n", __func__
, n_IRQ
);
359 if (src
->ide
== 0x00000000) {
361 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
365 if (src
->ide
== (1 << src
->last_cpu
)) {
366 /* Only one CPU is allowed to receive this IRQ */
367 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
);
368 } else if (!test_bit(&src
->ipvp
, IPVP_MODE
)) {
369 /* Directed delivery mode */
370 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
371 if (test_bit(&src
->ide
, i
))
372 IRQ_local_pipe(opp
, i
, n_IRQ
);
375 /* Distributed delivery mode */
376 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
377 if (i
== opp
->nb_cpus
)
379 if (test_bit(&src
->ide
, i
)) {
380 IRQ_local_pipe(opp
, i
, n_IRQ
);
388 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
390 openpic_t
*opp
= opaque
;
393 src
= &opp
->src
[n_IRQ
];
394 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
395 n_IRQ
, level
, src
->ipvp
);
396 if (test_bit(&src
->ipvp
, IPVP_SENSE
)) {
397 /* level-sensitive irq */
398 src
->pending
= level
;
400 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
402 /* edge-sensitive irq */
406 openpic_update_irq(opp
, n_IRQ
);
409 static void openpic_reset (void *opaque
)
411 openpic_t
*opp
= (openpic_t
*)opaque
;
414 opp
->glbc
= 0x80000000;
415 /* Initialise controller registers */
416 opp
->frep
= ((OPENPIC_EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
418 opp
->pint
= 0x00000000;
419 opp
->spve
= 0x000000FF;
420 opp
->tifr
= 0x003F7A00;
422 opp
->micr
= 0x00000000;
423 /* Initialise IRQ sources */
424 for (i
= 0; i
< opp
->max_irq
; i
++) {
425 opp
->src
[i
].ipvp
= 0xA0000000;
426 opp
->src
[i
].ide
= 0x00000000;
428 /* Initialise IRQ destinations */
429 for (i
= 0; i
< MAX_CPU
; i
++) {
430 opp
->dst
[i
].pctp
= 0x0000000F;
431 opp
->dst
[i
].pcsr
= 0x00000000;
432 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
433 opp
->dst
[i
].raised
.next
= -1;
434 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
435 opp
->dst
[i
].servicing
.next
= -1;
437 /* Initialise timers */
438 for (i
= 0; i
< MAX_TMR
; i
++) {
439 opp
->timers
[i
].ticc
= 0x00000000;
440 opp
->timers
[i
].tibc
= 0x80000000;
442 /* Go out of RESET state */
443 opp
->glbc
= 0x00000000;
446 static inline uint32_t read_IRQreg_ide(openpic_t
*opp
, int n_IRQ
)
448 return opp
->src
[n_IRQ
].ide
;
451 static inline uint32_t read_IRQreg_ipvp(openpic_t
*opp
, int n_IRQ
)
453 return opp
->src
[n_IRQ
].ipvp
;
456 static inline void write_IRQreg_ide(openpic_t
*opp
, int n_IRQ
, uint32_t val
)
460 tmp
= val
& 0xC0000000;
461 tmp
|= val
& ((1ULL << MAX_CPU
) - 1);
462 opp
->src
[n_IRQ
].ide
= tmp
;
463 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
466 static inline void write_IRQreg_ipvp(openpic_t
*opp
, int n_IRQ
, uint32_t val
)
468 /* NOTE: not fully accurate for special IRQs, but simple and sufficient */
469 /* ACTIVITY bit is read-only */
470 opp
->src
[n_IRQ
].ipvp
= (opp
->src
[n_IRQ
].ipvp
& 0x40000000)
471 | (val
& 0x800F00FF);
472 openpic_update_irq(opp
, n_IRQ
);
473 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ
, val
,
474 opp
->src
[n_IRQ
].ipvp
);
477 static void openpic_gbl_write(void *opaque
, hwaddr addr
, uint64_t val
,
480 openpic_t
*opp
= opaque
;
484 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
488 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
498 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
500 case 0x1000: /* FREP */
502 case 0x1020: /* GLBC */
503 if (val
& 0x80000000 && opp
->reset
)
505 opp
->glbc
= val
& ~0x80000000;
507 case 0x1080: /* VENI */
509 case 0x1090: /* PINT */
510 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
511 if ((val
& (1 << idx
)) && !(opp
->pint
& (1 << idx
))) {
512 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
513 dst
= &opp
->dst
[idx
];
514 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
515 } else if (!(val
& (1 << idx
)) && (opp
->pint
& (1 << idx
))) {
516 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
517 dst
= &opp
->dst
[idx
];
518 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
523 case 0x10A0: /* IPI_IPVP */
529 idx
= (addr
- 0x10A0) >> 4;
530 write_IRQreg_ipvp(opp
, opp
->irq_ipi0
+ idx
, val
);
533 case 0x10E0: /* SPVE */
534 opp
->spve
= val
& 0x000000FF;
536 case 0x10F0: /* TIFR */
544 static uint64_t openpic_gbl_read(void *opaque
, hwaddr addr
, unsigned len
)
546 openpic_t
*opp
= opaque
;
549 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
554 case 0x1000: /* FREP */
557 case 0x1020: /* GLBC */
560 case 0x1080: /* VENI */
563 case 0x1090: /* PINT */
566 case 0x00: /* Block Revision Register1 (BRR1) */
575 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
577 case 0x10A0: /* IPI_IPVP */
583 idx
= (addr
- 0x10A0) >> 4;
584 retval
= read_IRQreg_ipvp(opp
, opp
->irq_ipi0
+ idx
);
587 case 0x10E0: /* SPVE */
590 case 0x10F0: /* TIFR */
596 DPRINTF("%s: => %08x\n", __func__
, retval
);
601 static void openpic_timer_write(void *opaque
, hwaddr addr
, uint64_t val
,
604 openpic_t
*opp
= opaque
;
607 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
612 idx
= (addr
& 0xFFF0) >> 6;
615 case 0x00: /* TICC */
617 case 0x10: /* TIBC */
618 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
619 (val
& 0x80000000) == 0 &&
620 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
621 opp
->timers
[idx
].ticc
&= ~0x80000000;
622 opp
->timers
[idx
].tibc
= val
;
624 case 0x20: /* TIVP */
625 write_IRQreg_ipvp(opp
, opp
->irq_tim0
+ idx
, val
);
627 case 0x30: /* TIDE */
628 write_IRQreg_ide(opp
, opp
->irq_tim0
+ idx
, val
);
633 static uint64_t openpic_timer_read(void *opaque
, hwaddr addr
, unsigned len
)
635 openpic_t
*opp
= opaque
;
639 DPRINTF("%s: addr %08x\n", __func__
, addr
);
645 idx
= (addr
& 0xFFF0) >> 6;
648 case 0x00: /* TICC */
649 retval
= opp
->timers
[idx
].ticc
;
651 case 0x10: /* TIBC */
652 retval
= opp
->timers
[idx
].tibc
;
654 case 0x20: /* TIPV */
655 retval
= read_IRQreg_ipvp(opp
, opp
->irq_tim0
+ idx
);
657 case 0x30: /* TIDE */
658 retval
= read_IRQreg_ide(opp
, opp
->irq_tim0
+ idx
);
661 DPRINTF("%s: => %08x\n", __func__
, retval
);
666 static void openpic_src_write(void *opaque
, hwaddr addr
, uint64_t val
,
669 openpic_t
*opp
= opaque
;
672 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
675 addr
= addr
& 0xFFF0;
678 /* EXDE / IFEDE / IEEDE */
679 write_IRQreg_ide(opp
, idx
, val
);
681 /* EXVP / IFEVP / IEEVP */
682 write_IRQreg_ipvp(opp
, idx
, val
);
686 static uint64_t openpic_src_read(void *opaque
, uint64_t addr
, unsigned len
)
688 openpic_t
*opp
= opaque
;
692 DPRINTF("%s: addr %08x\n", __func__
, addr
);
696 addr
= addr
& 0xFFF0;
699 /* EXDE / IFEDE / IEEDE */
700 retval
= read_IRQreg_ide(opp
, idx
);
702 /* EXVP / IFEVP / IEEVP */
703 retval
= read_IRQreg_ipvp(opp
, idx
);
705 DPRINTF("%s: => %08x\n", __func__
, retval
);
710 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
711 uint32_t val
, int idx
)
713 openpic_t
*opp
= opaque
;
718 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
" <= %08x\n", __func__
, idx
,
722 dst
= &opp
->dst
[idx
];
725 case 0x40: /* IPIDR */
729 idx
= (addr
- 0x40) >> 4;
730 /* we use IDE as mask which CPUs to deliver the IPI to still. */
731 write_IRQreg_ide(opp
, opp
->irq_ipi0
+ idx
,
732 opp
->src
[opp
->irq_ipi0
+ idx
].ide
| val
);
733 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
734 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
736 case 0x80: /* PCTP */
737 dst
->pctp
= val
& 0x0000000F;
739 case 0x90: /* WHOAMI */
740 /* Read-only register */
742 case 0xA0: /* PIAC */
743 /* Read-only register */
745 case 0xB0: /* PEOI */
747 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
748 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
749 dst
->servicing
.next
= -1;
750 /* Set up next servicing IRQ */
751 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
752 /* Check queued interrupts. */
753 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
754 src
= &opp
->src
[n_IRQ
];
757 IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
)) {
758 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
760 openpic_irq_raise(opp
, idx
, src
);
768 static void openpic_cpu_write(void *opaque
, hwaddr addr
, uint64_t val
,
771 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
774 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
777 openpic_t
*opp
= opaque
;
783 DPRINTF("%s: cpu %d addr " TARGET_FMT_plx
"\n", __func__
, idx
, addr
);
787 dst
= &opp
->dst
[idx
];
790 case 0x00: /* Block Revision Register1 (BRR1) */
791 retval
= FSL_BRR1_IPID
| FSL_BRR1_IPMJ
| FSL_BRR1_IPMN
;
793 case 0x80: /* PCTP */
796 case 0x90: /* WHOAMI */
799 case 0xA0: /* PIAC */
800 DPRINTF("Lower OpenPIC INT output\n");
801 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
802 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
803 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
805 /* No more interrupt pending */
806 retval
= IPVP_VECTOR(opp
->spve
);
808 src
= &opp
->src
[n_IRQ
];
809 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
810 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
811 /* - Spurious level-sensitive IRQ
812 * - Priorities has been changed
813 * and the pending IRQ isn't allowed anymore
815 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
816 retval
= IPVP_VECTOR(opp
->spve
);
818 /* IRQ enter servicing state */
819 IRQ_setbit(&dst
->servicing
, n_IRQ
);
820 retval
= IPVP_VECTOR(src
->ipvp
);
822 IRQ_resetbit(&dst
->raised
, n_IRQ
);
823 dst
->raised
.next
= -1;
824 if (!test_bit(&src
->ipvp
, IPVP_SENSE
)) {
825 /* edge-sensitive IRQ */
826 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
830 if ((n_IRQ
>= opp
->irq_ipi0
) && (n_IRQ
< (opp
->irq_ipi0
+ MAX_IPI
))) {
831 src
->ide
&= ~(1 << idx
);
832 if (src
->ide
&& !test_bit(&src
->ipvp
, IPVP_SENSE
)) {
833 /* trigger on CPUs that didn't know about it yet */
834 openpic_set_irq(opp
, n_IRQ
, 1);
835 openpic_set_irq(opp
, n_IRQ
, 0);
836 /* if all CPUs knew about it, set active bit again */
837 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
842 case 0xB0: /* PEOI */
848 DPRINTF("%s: => %08x\n", __func__
, retval
);
853 static uint64_t openpic_cpu_read(void *opaque
, hwaddr addr
, unsigned len
)
855 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
858 static const MemoryRegionOps openpic_glb_ops
= {
859 .write
= openpic_gbl_write
,
860 .read
= openpic_gbl_read
,
861 .endianness
= DEVICE_LITTLE_ENDIAN
,
863 .min_access_size
= 4,
864 .max_access_size
= 4,
868 static const MemoryRegionOps openpic_tmr_ops
= {
869 .write
= openpic_timer_write
,
870 .read
= openpic_timer_read
,
871 .endianness
= DEVICE_LITTLE_ENDIAN
,
873 .min_access_size
= 4,
874 .max_access_size
= 4,
878 static const MemoryRegionOps openpic_cpu_ops
= {
879 .write
= openpic_cpu_write
,
880 .read
= openpic_cpu_read
,
881 .endianness
= DEVICE_LITTLE_ENDIAN
,
883 .min_access_size
= 4,
884 .max_access_size
= 4,
888 static const MemoryRegionOps openpic_src_ops
= {
889 .write
= openpic_src_write
,
890 .read
= openpic_src_read
,
891 .endianness
= DEVICE_LITTLE_ENDIAN
,
893 .min_access_size
= 4,
894 .max_access_size
= 4,
898 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
902 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
903 qemu_put_be32s(f
, &q
->queue
[i
]);
905 qemu_put_sbe32s(f
, &q
->next
);
906 qemu_put_sbe32s(f
, &q
->priority
);
909 static void openpic_save(QEMUFile
* f
, void *opaque
)
911 openpic_t
*opp
= (openpic_t
*)opaque
;
914 qemu_put_be32s(f
, &opp
->frep
);
915 qemu_put_be32s(f
, &opp
->glbc
);
916 qemu_put_be32s(f
, &opp
->micr
);
917 qemu_put_be32s(f
, &opp
->veni
);
918 qemu_put_be32s(f
, &opp
->pint
);
919 qemu_put_be32s(f
, &opp
->spve
);
920 qemu_put_be32s(f
, &opp
->tifr
);
922 for (i
= 0; i
< opp
->max_irq
; i
++) {
923 qemu_put_be32s(f
, &opp
->src
[i
].ipvp
);
924 qemu_put_be32s(f
, &opp
->src
[i
].ide
);
925 qemu_put_sbe32s(f
, &opp
->src
[i
].type
);
926 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
927 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
930 qemu_put_sbe32s(f
, &opp
->nb_cpus
);
932 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
933 qemu_put_be32s(f
, &opp
->dst
[i
].tfrr
);
934 qemu_put_be32s(f
, &opp
->dst
[i
].pctp
);
935 qemu_put_be32s(f
, &opp
->dst
[i
].pcsr
);
936 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
937 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
940 for (i
= 0; i
< MAX_TMR
; i
++) {
941 qemu_put_be32s(f
, &opp
->timers
[i
].ticc
);
942 qemu_put_be32s(f
, &opp
->timers
[i
].tibc
);
945 pci_device_save(&opp
->pci_dev
, f
);
948 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQ_queue_t
*q
)
952 for (i
= 0; i
< BF_WIDTH(MAX_IRQ
); i
++)
953 qemu_get_be32s(f
, &q
->queue
[i
]);
955 qemu_get_sbe32s(f
, &q
->next
);
956 qemu_get_sbe32s(f
, &q
->priority
);
959 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
961 openpic_t
*opp
= (openpic_t
*)opaque
;
967 qemu_get_be32s(f
, &opp
->frep
);
968 qemu_get_be32s(f
, &opp
->glbc
);
969 qemu_get_be32s(f
, &opp
->micr
);
970 qemu_get_be32s(f
, &opp
->veni
);
971 qemu_get_be32s(f
, &opp
->pint
);
972 qemu_get_be32s(f
, &opp
->spve
);
973 qemu_get_be32s(f
, &opp
->tifr
);
975 for (i
= 0; i
< opp
->max_irq
; i
++) {
976 qemu_get_be32s(f
, &opp
->src
[i
].ipvp
);
977 qemu_get_be32s(f
, &opp
->src
[i
].ide
);
978 qemu_get_sbe32s(f
, &opp
->src
[i
].type
);
979 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
980 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
983 qemu_get_sbe32s(f
, &opp
->nb_cpus
);
985 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
986 qemu_get_be32s(f
, &opp
->dst
[i
].tfrr
);
987 qemu_get_be32s(f
, &opp
->dst
[i
].pctp
);
988 qemu_get_be32s(f
, &opp
->dst
[i
].pcsr
);
989 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
990 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
993 for (i
= 0; i
< MAX_TMR
; i
++) {
994 qemu_get_be32s(f
, &opp
->timers
[i
].ticc
);
995 qemu_get_be32s(f
, &opp
->timers
[i
].tibc
);
998 return pci_device_load(&opp
->pci_dev
, f
);
1001 static void openpic_irq_raise(openpic_t
*opp
, int n_CPU
, IRQ_src_t
*src
)
1003 int n_ci
= IDR_CI0
- n_CPU
;
1005 if ((opp
->flags
& OPENPIC_FLAG_IDE_CRIT
) && test_bit(&src
->ide
, n_ci
)) {
1006 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_CINT
]);
1008 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
1012 qemu_irq
*openpic_init (MemoryRegion
**pmem
, int nb_cpus
,
1013 qemu_irq
**irqs
, qemu_irq irq_out
)
1019 MemoryRegionOps
const *ops
;
1023 {"glb", &openpic_glb_ops
, OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1024 {"tmr", &openpic_tmr_ops
, OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1025 {"src", &openpic_src_ops
, OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1026 {"cpu", &openpic_cpu_ops
, OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1029 /* XXX: for now, only one CPU is supported */
1032 opp
= g_malloc0(sizeof(openpic_t
));
1034 memory_region_init(&opp
->mem
, "openpic", 0x40000);
1036 for (i
= 0; i
< ARRAY_SIZE(list
); i
++) {
1038 memory_region_init_io(&opp
->sub_io_mem
[i
], list
[i
].ops
, opp
,
1039 list
[i
].name
, list
[i
].size
);
1041 memory_region_add_subregion(&opp
->mem
, list
[i
].start_addr
,
1042 &opp
->sub_io_mem
[i
]);
1045 // isu_base &= 0xFFFC0000;
1046 opp
->nb_cpus
= nb_cpus
;
1047 opp
->max_irq
= OPENPIC_MAX_IRQ
;
1048 opp
->irq_ipi0
= OPENPIC_IRQ_IPI0
;
1049 opp
->irq_tim0
= OPENPIC_IRQ_TIM0
;
1051 for (i
= 0; i
< OPENPIC_EXT_IRQ
; i
++) {
1052 opp
->src
[i
].type
= IRQ_EXTERNAL
;
1054 for (; i
< OPENPIC_IRQ_TIM0
; i
++) {
1055 opp
->src
[i
].type
= IRQ_SPECIAL
;
1057 m
= OPENPIC_IRQ_IPI0
;
1058 for (; i
< m
; i
++) {
1059 opp
->src
[i
].type
= IRQ_TIMER
;
1061 for (; i
< OPENPIC_MAX_IRQ
; i
++) {
1062 opp
->src
[i
].type
= IRQ_INTERNAL
;
1064 for (i
= 0; i
< nb_cpus
; i
++)
1065 opp
->dst
[i
].irqs
= irqs
[i
];
1066 opp
->irq_out
= irq_out
;
1068 register_savevm(&opp
->pci_dev
.qdev
, "openpic", 0, 2,
1069 openpic_save
, openpic_load
, opp
);
1070 qemu_register_reset(openpic_reset
, opp
);
1072 opp
->reset
= openpic_reset
;
1077 return qemu_allocate_irqs(openpic_set_irq
, opp
, opp
->max_irq
);
1080 static void mpic_reset (void *opaque
)
1082 openpic_t
*mpp
= (openpic_t
*)opaque
;
1085 mpp
->glbc
= 0x80000000;
1086 /* Initialise controller registers */
1087 mpp
->frep
= 0x004f0002 | ((mpp
->nb_cpus
- 1) << 8);
1089 mpp
->pint
= 0x00000000;
1090 mpp
->spve
= 0x0000FFFF;
1091 /* Initialise IRQ sources */
1092 for (i
= 0; i
< mpp
->max_irq
; i
++) {
1093 mpp
->src
[i
].ipvp
= 0x80800000;
1094 mpp
->src
[i
].ide
= 0x00000001;
1096 /* Set IDE for IPIs to 0 so we don't get spurious interrupts */
1097 for (i
= mpp
->irq_ipi0
; i
< (mpp
->irq_ipi0
+ MAX_IPI
); i
++) {
1098 mpp
->src
[i
].ide
= 0;
1100 /* Initialise IRQ destinations */
1101 for (i
= 0; i
< MAX_CPU
; i
++) {
1102 mpp
->dst
[i
].pctp
= 0x0000000F;
1103 mpp
->dst
[i
].tfrr
= 0x00000000;
1104 memset(&mpp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
1105 mpp
->dst
[i
].raised
.next
= -1;
1106 memset(&mpp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
1107 mpp
->dst
[i
].servicing
.next
= -1;
1109 /* Initialise timers */
1110 for (i
= 0; i
< MAX_TMR
; i
++) {
1111 mpp
->timers
[i
].ticc
= 0x00000000;
1112 mpp
->timers
[i
].tibc
= 0x80000000;
1114 /* Go out of RESET state */
1115 mpp
->glbc
= 0x00000000;
1118 static void mpic_timer_write(void *opaque
, hwaddr addr
, uint64_t val
,
1121 openpic_t
*mpp
= opaque
;
1124 DPRINTF("%s: addr " TARGET_FMT_plx
" <= %08x\n", __func__
, addr
, val
);
1128 idx
= (addr
>> 6) & 0x3;
1129 switch (addr
& 0x30) {
1130 case 0x00: /* gtccr */
1132 case 0x10: /* gtbcr */
1133 if ((mpp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
1134 (val
& 0x80000000) == 0 &&
1135 (mpp
->timers
[idx
].tibc
& 0x80000000) != 0)
1136 mpp
->timers
[idx
].ticc
&= ~0x80000000;
1137 mpp
->timers
[idx
].tibc
= val
;
1139 case 0x20: /* GTIVPR */
1140 write_IRQreg_ipvp(mpp
, MPIC_TMR_IRQ
+ idx
, val
);
1142 case 0x30: /* GTIDR & TFRR */
1143 if ((addr
& 0xF0) == 0xF0)
1144 mpp
->dst
[cpu
].tfrr
= val
;
1146 write_IRQreg_ide(mpp
, MPIC_TMR_IRQ
+ idx
, val
);
1151 static uint64_t mpic_timer_read(void *opaque
, hwaddr addr
, unsigned len
)
1153 openpic_t
*mpp
= opaque
;
1157 DPRINTF("%s: addr " TARGET_FMT_plx
"\n", __func__
, addr
);
1158 retval
= 0xFFFFFFFF;
1162 idx
= (addr
>> 6) & 0x3;
1163 switch (addr
& 0x30) {
1164 case 0x00: /* gtccr */
1165 retval
= mpp
->timers
[idx
].ticc
;
1167 case 0x10: /* gtbcr */
1168 retval
= mpp
->timers
[idx
].tibc
;
1170 case 0x20: /* TIPV */
1171 retval
= read_IRQreg_ipvp(mpp
, MPIC_TMR_IRQ
+ idx
);
1173 case 0x30: /* TIDR */
1174 if ((addr
&0xF0) == 0XF0)
1175 retval
= mpp
->dst
[cpu
].tfrr
;
1177 retval
= read_IRQreg_ide(mpp
, MPIC_TMR_IRQ
+ idx
);
1180 DPRINTF("%s: => %08x\n", __func__
, retval
);
1185 static const MemoryRegionOps mpic_glb_ops
= {
1186 .write
= openpic_gbl_write
,
1187 .read
= openpic_gbl_read
,
1188 .endianness
= DEVICE_BIG_ENDIAN
,
1190 .min_access_size
= 4,
1191 .max_access_size
= 4,
1195 static const MemoryRegionOps mpic_tmr_ops
= {
1196 .write
= mpic_timer_write
,
1197 .read
= mpic_timer_read
,
1198 .endianness
= DEVICE_BIG_ENDIAN
,
1200 .min_access_size
= 4,
1201 .max_access_size
= 4,
1205 static const MemoryRegionOps mpic_cpu_ops
= {
1206 .write
= openpic_cpu_write
,
1207 .read
= openpic_cpu_read
,
1208 .endianness
= DEVICE_BIG_ENDIAN
,
1210 .min_access_size
= 4,
1211 .max_access_size
= 4,
1215 static const MemoryRegionOps mpic_irq_ops
= {
1216 .write
= openpic_src_write
,
1217 .read
= openpic_src_read
,
1218 .endianness
= DEVICE_BIG_ENDIAN
,
1220 .min_access_size
= 4,
1221 .max_access_size
= 4,
1225 qemu_irq
*mpic_init (MemoryRegion
*address_space
, hwaddr base
,
1226 int nb_cpus
, qemu_irq
**irqs
, qemu_irq irq_out
)
1232 MemoryRegionOps
const *ops
;
1236 {"glb", &mpic_glb_ops
, MPIC_GLB_REG_START
, MPIC_GLB_REG_SIZE
},
1237 {"tmr", &mpic_tmr_ops
, MPIC_TMR_REG_START
, MPIC_TMR_REG_SIZE
},
1238 {"src", &mpic_irq_ops
, MPIC_SRC_REG_START
, MPIC_SRC_REG_SIZE
},
1239 {"cpu", &mpic_cpu_ops
, MPIC_CPU_REG_START
, MPIC_CPU_REG_SIZE
},
1242 mpp
= g_malloc0(sizeof(openpic_t
));
1244 memory_region_init(&mpp
->mem
, "mpic", 0x40000);
1245 memory_region_add_subregion(address_space
, base
, &mpp
->mem
);
1247 for (i
= 0; i
< sizeof(list
)/sizeof(list
[0]); i
++) {
1249 memory_region_init_io(&mpp
->sub_io_mem
[i
], list
[i
].ops
, mpp
,
1250 list
[i
].name
, list
[i
].size
);
1252 memory_region_add_subregion(&mpp
->mem
, list
[i
].start_addr
,
1253 &mpp
->sub_io_mem
[i
]);
1256 mpp
->nb_cpus
= nb_cpus
;
1257 mpp
->max_irq
= MPIC_MAX_IRQ
;
1258 mpp
->irq_ipi0
= MPIC_IPI_IRQ
;
1259 mpp
->irq_tim0
= MPIC_TMR_IRQ
;
1261 for (i
= 0; i
< nb_cpus
; i
++)
1262 mpp
->dst
[i
].irqs
= irqs
[i
];
1263 mpp
->irq_out
= irq_out
;
1265 /* Enable critical interrupt support */
1266 mpp
->flags
|= OPENPIC_FLAG_IDE_CRIT
;
1267 mpp
->reset
= mpic_reset
;
1269 register_savevm(NULL
, "mpic", 0, 2, openpic_save
, openpic_load
, mpp
);
1270 qemu_register_reset(mpic_reset
, mpp
);
1272 return qemu_allocate_irqs(openpic_set_irq
, mpp
, mpp
->max_irq
);