4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
42 #include "qemu/bitops.h"
45 //#define DEBUG_OPENPIC
48 static const int debug_openpic
= 1;
50 static const int debug_openpic
= 0;
53 #define DPRINTF(fmt, ...) do { \
54 if (debug_openpic) { \
55 printf(fmt , ## __VA_ARGS__); \
64 #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
65 #define VID 0x03 /* MPIC version ID */
67 /* OpenPIC capability flags */
68 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
70 /* OpenPIC address map */
71 #define OPENPIC_GLB_REG_START 0x0
72 #define OPENPIC_GLB_REG_SIZE 0x10F0
73 #define OPENPIC_TMR_REG_START 0x10F0
74 #define OPENPIC_TMR_REG_SIZE 0x220
75 #define OPENPIC_MSI_REG_START 0x1600
76 #define OPENPIC_MSI_REG_SIZE 0x200
77 #define OPENPIC_SRC_REG_START 0x10000
78 #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
79 #define OPENPIC_CPU_REG_START 0x20000
80 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
83 #define RAVEN_MAX_CPU 2
84 #define RAVEN_MAX_EXT 48
85 #define RAVEN_MAX_IRQ 64
86 #define RAVEN_MAX_TMR MAX_TMR
87 #define RAVEN_MAX_IPI MAX_IPI
89 /* Interrupt definitions */
90 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
91 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
92 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
93 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
94 /* First doorbell IRQ */
95 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
98 #define FSL_MPIC_20_MAX_CPU 1
99 #define FSL_MPIC_20_MAX_EXT 12
100 #define FSL_MPIC_20_MAX_INT 64
101 #define FSL_MPIC_20_MAX_IRQ MAX_IRQ
103 /* Interrupt definitions */
104 /* IRQs, accessible through the IRQ region */
105 #define FSL_MPIC_20_EXT_IRQ 0x00
106 #define FSL_MPIC_20_INT_IRQ 0x10
107 #define FSL_MPIC_20_MSG_IRQ 0xb0
108 #define FSL_MPIC_20_MSI_IRQ 0xe0
109 /* These are available through separate regions, but
110 for simplicity's sake mapped into the same number space */
111 #define FSL_MPIC_20_TMR_IRQ 0x100
112 #define FSL_MPIC_20_IPI_IRQ 0x104
115 * Block Revision Register1 (BRR1): QEMU does not fully emulate
116 * any version on MPIC. So to start with, set the IP version to 0.
118 * NOTE: This is Freescale MPIC specific register. Keep it here till
119 * this code is refactored for different variants of OPENPIC and MPIC.
121 #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */
122 #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
123 #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
125 #define FRR_NIRQ_SHIFT 16
126 #define FRR_NCPU_SHIFT 8
127 #define FRR_VID_SHIFT 0
129 #define VID_REVISION_1_2 2
130 #define VID_REVISION_1_3 3
132 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
134 #define GCR_RESET 0x80000000
135 #define GCR_MODE_PASS 0x00000000
136 #define GCR_MODE_MIXED 0x20000000
137 #define GCR_MODE_PROXY 0x60000000
139 #define TBCR_CI 0x80000000 /* count inhibit */
140 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
142 #define IDR_EP_SHIFT 31
143 #define IDR_EP_MASK (1 << IDR_EP_SHIFT)
144 #define IDR_CI0_SHIFT 30
145 #define IDR_CI1_SHIFT 29
146 #define IDR_P1_SHIFT 1
147 #define IDR_P0_SHIFT 0
149 #define MSIIR_OFFSET 0x140
150 #define MSIIR_SRS_SHIFT 29
151 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
152 #define MSIIR_IBS_SHIFT 24
153 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
155 static int get_current_cpu(void)
157 CPUState
*cpu_single_cpu
;
159 if (!cpu_single_env
) {
163 cpu_single_cpu
= ENV_GET_CPU(cpu_single_env
);
164 return cpu_single_cpu
->cpu_index
;
167 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
169 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
170 uint32_t val
, int idx
);
172 typedef enum IRQType
{
174 IRQ_TYPE_FSLINT
, /* FSL internal interrupt -- level only */
175 IRQ_TYPE_FSLSPECIAL
, /* FSL timer/IPI interrupt, edge, no polarity */
178 typedef struct IRQQueue
{
179 /* Round up to the nearest 64 IRQs so that the queue length
180 * won't change when moving between 32 and 64 bit hosts.
182 unsigned long queue
[BITS_TO_LONGS((MAX_IRQ
+ 63) & ~63)];
187 typedef struct IRQSource
{
188 uint32_t ivpr
; /* IRQ vector/priority register */
189 uint32_t idr
; /* IRQ destination register */
190 uint32_t destmask
; /* bitmap of CPU destinations */
192 int output
; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
193 int pending
; /* TRUE if IRQ is pending */
195 bool level
:1; /* level-triggered */
196 bool nomask
:1; /* critical interrupts ignore mask on some FSL MPICs */
199 #define IVPR_MASK_SHIFT 31
200 #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT)
201 #define IVPR_ACTIVITY_SHIFT 30
202 #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT)
203 #define IVPR_MODE_SHIFT 29
204 #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT)
205 #define IVPR_POLARITY_SHIFT 23
206 #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT)
207 #define IVPR_SENSE_SHIFT 22
208 #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT)
210 #define IVPR_PRIORITY_MASK (0xF << 16)
211 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
212 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
214 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
215 #define IDR_EP 0x80000000 /* external pin */
216 #define IDR_CI 0x40000000 /* critical interrupt */
218 typedef struct IRQDest
{
219 int32_t ctpr
; /* CPU current task priority */
224 /* Count of IRQ sources asserting on non-INT outputs */
225 uint32_t outputs_active
[OPENPIC_OUTPUT_NB
];
228 typedef struct OpenPICState
{
232 /* Behavior control */
237 uint32_t vir
; /* Vendor identification register */
238 uint32_t vector_mask
;
243 uint32_t mpic_mode_mask
;
246 MemoryRegion sub_io_mem
[5];
248 /* Global registers */
249 uint32_t frr
; /* Feature reporting register */
250 uint32_t gcr
; /* Global configuration register */
251 uint32_t pir
; /* Processor initialization register */
252 uint32_t spve
; /* Spurious vector register */
253 uint32_t tfrr
; /* Timer frequency reporting register */
254 /* Source registers */
255 IRQSource src
[MAX_IRQ
];
256 /* Local registers per output pin */
257 IRQDest dst
[MAX_CPU
];
259 /* Timer registers */
261 uint32_t tccr
; /* Global timer current count register */
262 uint32_t tbcr
; /* Global timer base count register */
264 /* Shared MSI registers */
266 uint32_t msir
; /* Shared Message Signaled Interrupt Register */
274 static inline void IRQ_setbit(IRQQueue
*q
, int n_IRQ
)
276 set_bit(n_IRQ
, q
->queue
);
279 static inline void IRQ_resetbit(IRQQueue
*q
, int n_IRQ
)
281 clear_bit(n_IRQ
, q
->queue
);
284 static inline int IRQ_testbit(IRQQueue
*q
, int n_IRQ
)
286 return test_bit(n_IRQ
, q
->queue
);
289 static void IRQ_check(OpenPICState
*opp
, IRQQueue
*q
)
296 irq
= find_next_bit(q
->queue
, opp
->max_irq
, irq
+ 1);
297 if (irq
== opp
->max_irq
) {
301 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
302 irq
, IVPR_PRIORITY(opp
->src
[irq
].ivpr
), priority
);
304 if (IVPR_PRIORITY(opp
->src
[irq
].ivpr
) > priority
) {
306 priority
= IVPR_PRIORITY(opp
->src
[irq
].ivpr
);
311 q
->priority
= priority
;
314 static int IRQ_get_next(OpenPICState
*opp
, IRQQueue
*q
)
322 static void IRQ_local_pipe(OpenPICState
*opp
, int n_CPU
, int n_IRQ
,
323 bool active
, bool was_active
)
329 dst
= &opp
->dst
[n_CPU
];
330 src
= &opp
->src
[n_IRQ
];
332 DPRINTF("%s: IRQ %d active %d was %d\n",
333 __func__
, n_IRQ
, active
, was_active
);
335 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
336 DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
337 __func__
, src
->output
, n_IRQ
, active
, was_active
,
338 dst
->outputs_active
[src
->output
]);
340 /* On Freescale MPIC, critical interrupts ignore priority,
341 * IACK, EOI, etc. Before MPIC v4.1 they also ignore
345 if (!was_active
&& dst
->outputs_active
[src
->output
]++ == 0) {
346 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
347 __func__
, src
->output
, n_CPU
, n_IRQ
);
348 qemu_irq_raise(dst
->irqs
[src
->output
]);
351 if (was_active
&& --dst
->outputs_active
[src
->output
] == 0) {
352 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
353 __func__
, src
->output
, n_CPU
, n_IRQ
);
354 qemu_irq_lower(dst
->irqs
[src
->output
]);
361 priority
= IVPR_PRIORITY(src
->ivpr
);
363 /* Even if the interrupt doesn't have enough priority,
364 * it is still raised, in case ctpr is lowered later.
367 IRQ_setbit(&dst
->raised
, n_IRQ
);
369 IRQ_resetbit(&dst
->raised
, n_IRQ
);
372 IRQ_check(opp
, &dst
->raised
);
374 if (active
&& priority
<= dst
->ctpr
) {
375 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
376 __func__
, n_IRQ
, priority
, dst
->ctpr
, n_CPU
);
381 if (IRQ_get_next(opp
, &dst
->servicing
) >= 0 &&
382 priority
<= dst
->servicing
.priority
) {
383 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
384 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
386 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
387 __func__
, n_CPU
, n_IRQ
, dst
->raised
.next
);
388 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
391 IRQ_get_next(opp
, &dst
->servicing
);
392 if (dst
->raised
.priority
> dst
->ctpr
&&
393 dst
->raised
.priority
> dst
->servicing
.priority
) {
394 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
395 __func__
, n_IRQ
, dst
->raised
.next
, dst
->raised
.priority
,
396 dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
397 /* IRQ line stays asserted */
399 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
400 __func__
, n_IRQ
, dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
401 qemu_irq_lower(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
406 /* update pic state because registers for n_IRQ have changed value */
407 static void openpic_update_irq(OpenPICState
*opp
, int n_IRQ
)
410 bool active
, was_active
;
413 src
= &opp
->src
[n_IRQ
];
414 active
= src
->pending
;
416 if ((src
->ivpr
& IVPR_MASK_MASK
) && !src
->nomask
) {
417 /* Interrupt source is disabled */
418 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
422 was_active
= !!(src
->ivpr
& IVPR_ACTIVITY_MASK
);
425 * We don't have a similar check for already-active because
426 * ctpr may have changed and we need to withdraw the interrupt.
428 if (!active
&& !was_active
) {
429 DPRINTF("%s: IRQ %d is already inactive\n", __func__
, n_IRQ
);
434 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
436 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
439 if (src
->destmask
== 0) {
441 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
445 if (src
->destmask
== (1 << src
->last_cpu
)) {
446 /* Only one CPU is allowed to receive this IRQ */
447 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
, active
, was_active
);
448 } else if (!(src
->ivpr
& IVPR_MODE_MASK
)) {
449 /* Directed delivery mode */
450 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
451 if (src
->destmask
& (1 << i
)) {
452 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
456 /* Distributed delivery mode */
457 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
458 if (i
== opp
->nb_cpus
) {
461 if (src
->destmask
& (1 << i
)) {
462 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
470 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
472 OpenPICState
*opp
= opaque
;
475 if (n_IRQ
>= MAX_IRQ
) {
476 fprintf(stderr
, "%s: IRQ %d out of range\n", __func__
, n_IRQ
);
480 src
= &opp
->src
[n_IRQ
];
481 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
482 n_IRQ
, level
, src
->ivpr
);
484 /* level-sensitive irq */
485 src
->pending
= level
;
486 openpic_update_irq(opp
, n_IRQ
);
488 /* edge-sensitive irq */
491 openpic_update_irq(opp
, n_IRQ
);
494 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
495 /* Edge-triggered interrupts shouldn't be used
496 * with non-INT delivery, but just in case,
497 * try to make it do something sane rather than
498 * cause an interrupt storm. This is close to
499 * what you'd probably see happen in real hardware.
502 openpic_update_irq(opp
, n_IRQ
);
507 static void openpic_reset(DeviceState
*d
)
509 OpenPICState
*opp
= FROM_SYSBUS(typeof(*opp
), SYS_BUS_DEVICE(d
));
512 opp
->gcr
= GCR_RESET
;
513 /* Initialise controller registers */
514 opp
->frr
= ((opp
->nb_irqs
- 1) << FRR_NIRQ_SHIFT
) |
515 ((opp
->nb_cpus
- 1) << FRR_NCPU_SHIFT
) |
516 (opp
->vid
<< FRR_VID_SHIFT
);
519 opp
->spve
= -1 & opp
->vector_mask
;
520 opp
->tfrr
= opp
->tfrr_reset
;
521 /* Initialise IRQ sources */
522 for (i
= 0; i
< opp
->max_irq
; i
++) {
523 opp
->src
[i
].ivpr
= opp
->ivpr_reset
;
524 opp
->src
[i
].idr
= opp
->idr_reset
;
526 switch (opp
->src
[i
].type
) {
527 case IRQ_TYPE_NORMAL
:
528 opp
->src
[i
].level
= !!(opp
->ivpr_reset
& IVPR_SENSE_MASK
);
531 case IRQ_TYPE_FSLINT
:
532 opp
->src
[i
].ivpr
|= IVPR_POLARITY_MASK
;
535 case IRQ_TYPE_FSLSPECIAL
:
539 /* Initialise IRQ destinations */
540 for (i
= 0; i
< MAX_CPU
; i
++) {
541 opp
->dst
[i
].ctpr
= 15;
542 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQQueue
));
543 opp
->dst
[i
].raised
.next
= -1;
544 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQQueue
));
545 opp
->dst
[i
].servicing
.next
= -1;
547 /* Initialise timers */
548 for (i
= 0; i
< MAX_TMR
; i
++) {
549 opp
->timers
[i
].tccr
= 0;
550 opp
->timers
[i
].tbcr
= TBCR_CI
;
552 /* Go out of RESET state */
556 static inline uint32_t read_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
)
558 return opp
->src
[n_IRQ
].idr
;
561 static inline uint32_t read_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
)
563 return opp
->src
[n_IRQ
].ivpr
;
566 static inline void write_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
568 IRQSource
*src
= &opp
->src
[n_IRQ
];
569 uint32_t normal_mask
= (1UL << opp
->nb_cpus
) - 1;
570 uint32_t crit_mask
= 0;
571 uint32_t mask
= normal_mask
;
572 int crit_shift
= IDR_EP_SHIFT
- opp
->nb_cpus
;
575 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
576 crit_mask
= mask
<< crit_shift
;
577 mask
|= crit_mask
| IDR_EP
;
580 src
->idr
= val
& mask
;
581 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ
, src
->idr
);
583 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
584 if (src
->idr
& crit_mask
) {
585 if (src
->idr
& normal_mask
) {
586 DPRINTF("%s: IRQ configured for multiple output types, using "
587 "critical\n", __func__
);
590 src
->output
= OPENPIC_OUTPUT_CINT
;
594 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
595 int n_ci
= IDR_CI0_SHIFT
- i
;
597 if (src
->idr
& (1UL << n_ci
)) {
598 src
->destmask
|= 1UL << i
;
602 src
->output
= OPENPIC_OUTPUT_INT
;
604 src
->destmask
= src
->idr
& normal_mask
;
607 src
->destmask
= src
->idr
;
611 static inline void write_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
615 /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
616 * the polarity bit is read-only on internal interrupts.
618 mask
= IVPR_MASK_MASK
| IVPR_PRIORITY_MASK
| IVPR_SENSE_MASK
|
619 IVPR_POLARITY_MASK
| opp
->vector_mask
;
621 /* ACTIVITY bit is read-only */
622 opp
->src
[n_IRQ
].ivpr
=
623 (opp
->src
[n_IRQ
].ivpr
& IVPR_ACTIVITY_MASK
) | (val
& mask
);
625 /* For FSL internal interrupts, The sense bit is reserved and zero,
626 * and the interrupt is always level-triggered. Timers and IPIs
627 * have no sense or polarity bits, and are edge-triggered.
629 switch (opp
->src
[n_IRQ
].type
) {
630 case IRQ_TYPE_NORMAL
:
631 opp
->src
[n_IRQ
].level
= !!(opp
->src
[n_IRQ
].ivpr
& IVPR_SENSE_MASK
);
634 case IRQ_TYPE_FSLINT
:
635 opp
->src
[n_IRQ
].ivpr
&= ~IVPR_SENSE_MASK
;
638 case IRQ_TYPE_FSLSPECIAL
:
639 opp
->src
[n_IRQ
].ivpr
&= ~(IVPR_POLARITY_MASK
| IVPR_SENSE_MASK
);
643 openpic_update_irq(opp
, n_IRQ
);
644 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ
, val
,
645 opp
->src
[n_IRQ
].ivpr
);
648 static void openpic_gcr_write(OpenPICState
*opp
, uint64_t val
)
650 bool mpic_proxy
= false;
652 if (val
& GCR_RESET
) {
653 openpic_reset(&opp
->busdev
.qdev
);
657 opp
->gcr
&= ~opp
->mpic_mode_mask
;
658 opp
->gcr
|= val
& opp
->mpic_mode_mask
;
660 /* Set external proxy mode */
661 if ((val
& opp
->mpic_mode_mask
) == GCR_MODE_PROXY
) {
665 ppce500_set_mpic_proxy(mpic_proxy
);
668 static void openpic_gbl_write(void *opaque
, hwaddr addr
, uint64_t val
,
671 OpenPICState
*opp
= opaque
;
675 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
676 __func__
, addr
, val
);
681 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
691 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
693 case 0x1000: /* FRR */
695 case 0x1020: /* GCR */
696 openpic_gcr_write(opp
, val
);
698 case 0x1080: /* VIR */
700 case 0x1090: /* PIR */
701 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
702 if ((val
& (1 << idx
)) && !(opp
->pir
& (1 << idx
))) {
703 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
704 dst
= &opp
->dst
[idx
];
705 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
706 } else if (!(val
& (1 << idx
)) && (opp
->pir
& (1 << idx
))) {
707 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
708 dst
= &opp
->dst
[idx
];
709 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
714 case 0x10A0: /* IPI_IVPR */
720 idx
= (addr
- 0x10A0) >> 4;
721 write_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
, val
);
724 case 0x10E0: /* SPVE */
725 opp
->spve
= val
& opp
->vector_mask
;
732 static uint64_t openpic_gbl_read(void *opaque
, hwaddr addr
, unsigned len
)
734 OpenPICState
*opp
= opaque
;
737 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
743 case 0x1000: /* FRR */
746 case 0x1020: /* GCR */
749 case 0x1080: /* VIR */
752 case 0x1090: /* PIR */
755 case 0x00: /* Block Revision Register1 (BRR1) */
766 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
768 case 0x10A0: /* IPI_IVPR */
774 idx
= (addr
- 0x10A0) >> 4;
775 retval
= read_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
);
778 case 0x10E0: /* SPVE */
784 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
789 static void openpic_tmr_write(void *opaque
, hwaddr addr
, uint64_t val
,
792 OpenPICState
*opp
= opaque
;
797 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
798 __func__
, addr
, val
);
803 if (addr
== 0x10f0) {
809 idx
= (addr
>> 6) & 0x3;
812 switch (addr
& 0x30) {
813 case 0x00: /* TCCR */
815 case 0x10: /* TBCR */
816 if ((opp
->timers
[idx
].tccr
& TCCR_TOG
) != 0 &&
817 (val
& TBCR_CI
) == 0 &&
818 (opp
->timers
[idx
].tbcr
& TBCR_CI
) != 0) {
819 opp
->timers
[idx
].tccr
&= ~TCCR_TOG
;
821 opp
->timers
[idx
].tbcr
= val
;
823 case 0x20: /* TVPR */
824 write_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
, val
);
827 write_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
, val
);
832 static uint64_t openpic_tmr_read(void *opaque
, hwaddr addr
, unsigned len
)
834 OpenPICState
*opp
= opaque
;
835 uint32_t retval
= -1;
838 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
842 idx
= (addr
>> 6) & 0x3;
848 switch (addr
& 0x30) {
849 case 0x00: /* TCCR */
850 retval
= opp
->timers
[idx
].tccr
;
852 case 0x10: /* TBCR */
853 retval
= opp
->timers
[idx
].tbcr
;
855 case 0x20: /* TIPV */
856 retval
= read_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
);
858 case 0x30: /* TIDE (TIDR) */
859 retval
= read_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
);
864 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
869 static void openpic_src_write(void *opaque
, hwaddr addr
, uint64_t val
,
872 OpenPICState
*opp
= opaque
;
875 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
876 __func__
, addr
, val
);
880 addr
= addr
& 0xFFF0;
883 /* EXDE / IFEDE / IEEDE */
884 write_IRQreg_idr(opp
, idx
, val
);
886 /* EXVP / IFEVP / IEEVP */
887 write_IRQreg_ivpr(opp
, idx
, val
);
891 static uint64_t openpic_src_read(void *opaque
, uint64_t addr
, unsigned len
)
893 OpenPICState
*opp
= opaque
;
897 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
902 addr
= addr
& 0xFFF0;
905 /* EXDE / IFEDE / IEEDE */
906 retval
= read_IRQreg_idr(opp
, idx
);
908 /* EXVP / IFEVP / IEEVP */
909 retval
= read_IRQreg_ivpr(opp
, idx
);
911 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
916 static void openpic_msi_write(void *opaque
, hwaddr addr
, uint64_t val
,
919 OpenPICState
*opp
= opaque
;
920 int idx
= opp
->irq_msi
;
923 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= 0x%08" PRIx64
"\n",
924 __func__
, addr
, val
);
931 srs
= val
>> MSIIR_SRS_SHIFT
;
933 ibs
= (val
& MSIIR_IBS_MASK
) >> MSIIR_IBS_SHIFT
;
934 opp
->msi
[srs
].msir
|= 1 << ibs
;
935 openpic_set_irq(opp
, idx
, 1);
938 /* most registers are read-only, thus ignored */
943 static uint64_t openpic_msi_read(void *opaque
, hwaddr addr
, unsigned size
)
945 OpenPICState
*opp
= opaque
;
949 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
964 case 0x70: /* MSIRs */
965 r
= opp
->msi
[srs
].msir
;
967 opp
->msi
[srs
].msir
= 0;
968 openpic_set_irq(opp
, opp
->irq_msi
+ srs
, 0);
970 case 0x120: /* MSISR */
971 for (i
= 0; i
< MAX_MSI
; i
++) {
972 r
|= (opp
->msi
[i
].msir
? 1 : 0) << i
;
980 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
981 uint32_t val
, int idx
)
983 OpenPICState
*opp
= opaque
;
988 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
" <= 0x%08x\n", __func__
, idx
,
998 dst
= &opp
->dst
[idx
];
1001 case 0x40: /* IPIDR */
1005 idx
= (addr
- 0x40) >> 4;
1006 /* we use IDE as mask which CPUs to deliver the IPI to still. */
1007 opp
->src
[opp
->irq_ipi0
+ idx
].destmask
|= val
;
1008 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
1009 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
1011 case 0x80: /* CTPR */
1012 dst
->ctpr
= val
& 0x0000000F;
1014 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1015 __func__
, idx
, dst
->ctpr
, dst
->raised
.priority
,
1016 dst
->servicing
.priority
);
1018 if (dst
->raised
.priority
<= dst
->ctpr
) {
1019 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1021 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1022 } else if (dst
->raised
.priority
> dst
->servicing
.priority
) {
1023 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1024 __func__
, idx
, dst
->raised
.next
);
1025 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1029 case 0x90: /* WHOAMI */
1030 /* Read-only register */
1032 case 0xA0: /* IACK */
1033 /* Read-only register */
1035 case 0xB0: /* EOI */
1037 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1040 DPRINTF("%s: EOI with no interrupt in service\n", __func__
);
1044 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
1045 /* Set up next servicing IRQ */
1046 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1047 /* Check queued interrupts. */
1048 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
1049 src
= &opp
->src
[n_IRQ
];
1052 IVPR_PRIORITY(src
->ivpr
) > dst
->servicing
.priority
)) {
1053 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1055 qemu_irq_raise(opp
->dst
[idx
].irqs
[OPENPIC_OUTPUT_INT
]);
1063 static void openpic_cpu_write(void *opaque
, hwaddr addr
, uint64_t val
,
1066 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
1070 static uint32_t openpic_iack(OpenPICState
*opp
, IRQDest
*dst
, int cpu
)
1075 DPRINTF("Lower OpenPIC INT output\n");
1076 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1078 irq
= IRQ_get_next(opp
, &dst
->raised
);
1079 DPRINTF("IACK: irq=%d\n", irq
);
1082 /* No more interrupt pending */
1086 src
= &opp
->src
[irq
];
1087 if (!(src
->ivpr
& IVPR_ACTIVITY_MASK
) ||
1088 !(IVPR_PRIORITY(src
->ivpr
) > dst
->ctpr
)) {
1089 fprintf(stderr
, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1090 __func__
, irq
, dst
->ctpr
, src
->ivpr
);
1091 openpic_update_irq(opp
, irq
);
1094 /* IRQ enter servicing state */
1095 IRQ_setbit(&dst
->servicing
, irq
);
1096 retval
= IVPR_VECTOR(opp
, src
->ivpr
);
1100 /* edge-sensitive IRQ */
1101 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
1103 IRQ_resetbit(&dst
->raised
, irq
);
1106 if ((irq
>= opp
->irq_ipi0
) && (irq
< (opp
->irq_ipi0
+ MAX_IPI
))) {
1107 src
->destmask
&= ~(1 << cpu
);
1108 if (src
->destmask
&& !src
->level
) {
1109 /* trigger on CPUs that didn't know about it yet */
1110 openpic_set_irq(opp
, irq
, 1);
1111 openpic_set_irq(opp
, irq
, 0);
1112 /* if all CPUs knew about it, set active bit again */
1113 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
1120 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
1123 OpenPICState
*opp
= opaque
;
1127 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
"\n", __func__
, idx
, addr
);
1128 retval
= 0xFFFFFFFF;
1137 dst
= &opp
->dst
[idx
];
1140 case 0x80: /* CTPR */
1143 case 0x90: /* WHOAMI */
1146 case 0xA0: /* IACK */
1147 retval
= openpic_iack(opp
, dst
, idx
);
1149 case 0xB0: /* EOI */
1155 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
1160 static uint64_t openpic_cpu_read(void *opaque
, hwaddr addr
, unsigned len
)
1162 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
1165 static const MemoryRegionOps openpic_glb_ops_le
= {
1166 .write
= openpic_gbl_write
,
1167 .read
= openpic_gbl_read
,
1168 .endianness
= DEVICE_LITTLE_ENDIAN
,
1170 .min_access_size
= 4,
1171 .max_access_size
= 4,
1175 static const MemoryRegionOps openpic_glb_ops_be
= {
1176 .write
= openpic_gbl_write
,
1177 .read
= openpic_gbl_read
,
1178 .endianness
= DEVICE_BIG_ENDIAN
,
1180 .min_access_size
= 4,
1181 .max_access_size
= 4,
1185 static const MemoryRegionOps openpic_tmr_ops_le
= {
1186 .write
= openpic_tmr_write
,
1187 .read
= openpic_tmr_read
,
1188 .endianness
= DEVICE_LITTLE_ENDIAN
,
1190 .min_access_size
= 4,
1191 .max_access_size
= 4,
1195 static const MemoryRegionOps openpic_tmr_ops_be
= {
1196 .write
= openpic_tmr_write
,
1197 .read
= openpic_tmr_read
,
1198 .endianness
= DEVICE_BIG_ENDIAN
,
1200 .min_access_size
= 4,
1201 .max_access_size
= 4,
1205 static const MemoryRegionOps openpic_cpu_ops_le
= {
1206 .write
= openpic_cpu_write
,
1207 .read
= openpic_cpu_read
,
1208 .endianness
= DEVICE_LITTLE_ENDIAN
,
1210 .min_access_size
= 4,
1211 .max_access_size
= 4,
1215 static const MemoryRegionOps openpic_cpu_ops_be
= {
1216 .write
= openpic_cpu_write
,
1217 .read
= openpic_cpu_read
,
1218 .endianness
= DEVICE_BIG_ENDIAN
,
1220 .min_access_size
= 4,
1221 .max_access_size
= 4,
1225 static const MemoryRegionOps openpic_src_ops_le
= {
1226 .write
= openpic_src_write
,
1227 .read
= openpic_src_read
,
1228 .endianness
= DEVICE_LITTLE_ENDIAN
,
1230 .min_access_size
= 4,
1231 .max_access_size
= 4,
1235 static const MemoryRegionOps openpic_src_ops_be
= {
1236 .write
= openpic_src_write
,
1237 .read
= openpic_src_read
,
1238 .endianness
= DEVICE_BIG_ENDIAN
,
1240 .min_access_size
= 4,
1241 .max_access_size
= 4,
1245 static const MemoryRegionOps openpic_msi_ops_le
= {
1246 .read
= openpic_msi_read
,
1247 .write
= openpic_msi_write
,
1248 .endianness
= DEVICE_LITTLE_ENDIAN
,
1250 .min_access_size
= 4,
1251 .max_access_size
= 4,
1255 static const MemoryRegionOps openpic_msi_ops_be
= {
1256 .read
= openpic_msi_read
,
1257 .write
= openpic_msi_write
,
1258 .endianness
= DEVICE_BIG_ENDIAN
,
1260 .min_access_size
= 4,
1261 .max_access_size
= 4,
1265 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQQueue
*q
)
1269 for (i
= 0; i
< ARRAY_SIZE(q
->queue
); i
++) {
1270 /* Always put the lower half of a 64-bit long first, in case we
1271 * restore on a 32-bit host. The least significant bits correspond
1272 * to lower IRQ numbers in the bitmap.
1274 qemu_put_be32(f
, (uint32_t)q
->queue
[i
]);
1275 #if LONG_MAX > 0x7FFFFFFF
1276 qemu_put_be32(f
, (uint32_t)(q
->queue
[i
] >> 32));
1280 qemu_put_sbe32s(f
, &q
->next
);
1281 qemu_put_sbe32s(f
, &q
->priority
);
1284 static void openpic_save(QEMUFile
* f
, void *opaque
)
1286 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1289 qemu_put_be32s(f
, &opp
->gcr
);
1290 qemu_put_be32s(f
, &opp
->vir
);
1291 qemu_put_be32s(f
, &opp
->pir
);
1292 qemu_put_be32s(f
, &opp
->spve
);
1293 qemu_put_be32s(f
, &opp
->tfrr
);
1295 qemu_put_be32s(f
, &opp
->nb_cpus
);
1297 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1298 qemu_put_sbe32s(f
, &opp
->dst
[i
].ctpr
);
1299 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1300 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1301 qemu_put_buffer(f
, (uint8_t *)&opp
->dst
[i
].outputs_active
,
1302 sizeof(opp
->dst
[i
].outputs_active
));
1305 for (i
= 0; i
< MAX_TMR
; i
++) {
1306 qemu_put_be32s(f
, &opp
->timers
[i
].tccr
);
1307 qemu_put_be32s(f
, &opp
->timers
[i
].tbcr
);
1310 for (i
= 0; i
< opp
->max_irq
; i
++) {
1311 qemu_put_be32s(f
, &opp
->src
[i
].ivpr
);
1312 qemu_put_be32s(f
, &opp
->src
[i
].idr
);
1313 qemu_get_be32s(f
, &opp
->src
[i
].destmask
);
1314 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1315 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
1319 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQQueue
*q
)
1323 for (i
= 0; i
< ARRAY_SIZE(q
->queue
); i
++) {
1326 val
= qemu_get_be32(f
);
1327 #if LONG_MAX > 0x7FFFFFFF
1329 val
|= qemu_get_be32(f
);
1335 qemu_get_sbe32s(f
, &q
->next
);
1336 qemu_get_sbe32s(f
, &q
->priority
);
1339 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1341 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1344 if (version_id
!= 1) {
1348 qemu_get_be32s(f
, &opp
->gcr
);
1349 qemu_get_be32s(f
, &opp
->vir
);
1350 qemu_get_be32s(f
, &opp
->pir
);
1351 qemu_get_be32s(f
, &opp
->spve
);
1352 qemu_get_be32s(f
, &opp
->tfrr
);
1354 qemu_get_be32s(f
, &opp
->nb_cpus
);
1356 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1357 qemu_get_sbe32s(f
, &opp
->dst
[i
].ctpr
);
1358 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1359 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1360 qemu_get_buffer(f
, (uint8_t *)&opp
->dst
[i
].outputs_active
,
1361 sizeof(opp
->dst
[i
].outputs_active
));
1364 for (i
= 0; i
< MAX_TMR
; i
++) {
1365 qemu_get_be32s(f
, &opp
->timers
[i
].tccr
);
1366 qemu_get_be32s(f
, &opp
->timers
[i
].tbcr
);
1369 for (i
= 0; i
< opp
->max_irq
; i
++) {
1372 val
= qemu_get_be32(f
);
1373 write_IRQreg_idr(opp
, i
, val
);
1374 val
= qemu_get_be32(f
);
1375 write_IRQreg_ivpr(opp
, i
, val
);
1377 qemu_get_be32s(f
, &opp
->src
[i
].ivpr
);
1378 qemu_get_be32s(f
, &opp
->src
[i
].idr
);
1379 qemu_get_be32s(f
, &opp
->src
[i
].destmask
);
1380 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1381 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
1387 typedef struct MemReg
{
1389 MemoryRegionOps
const *ops
;
1395 static int openpic_init(SysBusDevice
*dev
)
1397 OpenPICState
*opp
= FROM_SYSBUS(typeof (*opp
), dev
);
1399 MemReg list_le
[] = {
1400 {"glb", &openpic_glb_ops_le
, true,
1401 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1402 {"tmr", &openpic_tmr_ops_le
, true,
1403 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1404 {"msi", &openpic_msi_ops_le
, true,
1405 OPENPIC_MSI_REG_START
, OPENPIC_MSI_REG_SIZE
},
1406 {"src", &openpic_src_ops_le
, true,
1407 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1408 {"cpu", &openpic_cpu_ops_le
, true,
1409 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1411 MemReg list_be
[] = {
1412 {"glb", &openpic_glb_ops_be
, true,
1413 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1414 {"tmr", &openpic_tmr_ops_be
, true,
1415 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1416 {"msi", &openpic_msi_ops_be
, true,
1417 OPENPIC_MSI_REG_START
, OPENPIC_MSI_REG_SIZE
},
1418 {"src", &openpic_src_ops_be
, true,
1419 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1420 {"cpu", &openpic_cpu_ops_be
, true,
1421 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1425 switch (opp
->model
) {
1426 case OPENPIC_MODEL_FSL_MPIC_20
:
1428 opp
->flags
|= OPENPIC_FLAG_IDR_CRIT
;
1430 opp
->vid
= VID_REVISION_1_2
;
1431 opp
->vir
= VIR_GENERIC
;
1432 opp
->vector_mask
= 0xFFFF;
1433 opp
->tfrr_reset
= 0;
1434 opp
->ivpr_reset
= IVPR_MASK_MASK
;
1435 opp
->idr_reset
= 1 << 0;
1436 opp
->max_irq
= FSL_MPIC_20_MAX_IRQ
;
1437 opp
->irq_ipi0
= FSL_MPIC_20_IPI_IRQ
;
1438 opp
->irq_tim0
= FSL_MPIC_20_TMR_IRQ
;
1439 opp
->irq_msi
= FSL_MPIC_20_MSI_IRQ
;
1440 opp
->brr1
= FSL_BRR1_IPID
| FSL_BRR1_IPMJ
| FSL_BRR1_IPMN
;
1441 /* XXX really only available as of MPIC 4.0 */
1442 opp
->mpic_mode_mask
= GCR_MODE_PROXY
;
1444 msi_supported
= true;
1447 for (i
= 0; i
< FSL_MPIC_20_MAX_EXT
; i
++) {
1448 opp
->src
[i
].level
= false;
1451 /* Internal interrupts, including message and MSI */
1452 for (i
= 16; i
< MAX_SRC
; i
++) {
1453 opp
->src
[i
].type
= IRQ_TYPE_FSLINT
;
1454 opp
->src
[i
].level
= true;
1457 /* timers and IPIs */
1458 for (i
= MAX_SRC
; i
< MAX_IRQ
; i
++) {
1459 opp
->src
[i
].type
= IRQ_TYPE_FSLSPECIAL
;
1460 opp
->src
[i
].level
= false;
1465 case OPENPIC_MODEL_RAVEN
:
1466 opp
->nb_irqs
= RAVEN_MAX_EXT
;
1467 opp
->vid
= VID_REVISION_1_3
;
1468 opp
->vir
= VIR_GENERIC
;
1469 opp
->vector_mask
= 0xFF;
1470 opp
->tfrr_reset
= 4160000;
1471 opp
->ivpr_reset
= IVPR_MASK_MASK
| IVPR_MODE_MASK
;
1473 opp
->max_irq
= RAVEN_MAX_IRQ
;
1474 opp
->irq_ipi0
= RAVEN_IPI_IRQ
;
1475 opp
->irq_tim0
= RAVEN_TMR_IRQ
;
1477 opp
->mpic_mode_mask
= GCR_MODE_MIXED
;
1479 /* Don't map MSI region */
1480 list
[2].map
= false;
1482 /* Only UP supported today */
1483 if (opp
->nb_cpus
!= 1) {
1489 memory_region_init(&opp
->mem
, "openpic", 0x40000);
1491 for (i
= 0; i
< ARRAY_SIZE(list_le
); i
++) {
1496 memory_region_init_io(&opp
->sub_io_mem
[i
], list
[i
].ops
, opp
,
1497 list
[i
].name
, list
[i
].size
);
1499 memory_region_add_subregion(&opp
->mem
, list
[i
].start_addr
,
1500 &opp
->sub_io_mem
[i
]);
1503 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1504 opp
->dst
[i
].irqs
= g_new(qemu_irq
, OPENPIC_OUTPUT_NB
);
1505 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
1506 sysbus_init_irq(dev
, &opp
->dst
[i
].irqs
[j
]);
1510 register_savevm(&opp
->busdev
.qdev
, "openpic", 0, 2,
1511 openpic_save
, openpic_load
, opp
);
1513 sysbus_init_mmio(dev
, &opp
->mem
);
1514 qdev_init_gpio_in(&dev
->qdev
, openpic_set_irq
, opp
->max_irq
);
1519 static Property openpic_properties
[] = {
1520 DEFINE_PROP_UINT32("model", OpenPICState
, model
, OPENPIC_MODEL_FSL_MPIC_20
),
1521 DEFINE_PROP_UINT32("nb_cpus", OpenPICState
, nb_cpus
, 1),
1522 DEFINE_PROP_END_OF_LIST(),
1525 static void openpic_class_init(ObjectClass
*klass
, void *data
)
1527 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1528 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1530 k
->init
= openpic_init
;
1531 dc
->props
= openpic_properties
;
1532 dc
->reset
= openpic_reset
;
1535 static const TypeInfo openpic_info
= {
1537 .parent
= TYPE_SYS_BUS_DEVICE
,
1538 .instance_size
= sizeof(OpenPICState
),
1539 .class_init
= openpic_class_init
,
1542 static void openpic_register_types(void)
1544 type_register_static(&openpic_info
);
1547 type_init(openpic_register_types
)