4 * Copyright (c) 2004 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * Based on OpenPic implementations:
28 * - Intel GW80314 I/O companion chip developer's manual
29 * - Motorola MPC8245 & MPC8540 user manuals.
30 * - Motorola MCP750 (aka Raven) programmer manual.
31 * - Motorola Harrier programmer manuel
33 * Serial interrupts, as implemented in Raven chipset are not supported yet.
42 #include "qemu/bitops.h"
44 //#define DEBUG_OPENPIC
47 static const int debug_openpic
= 1;
49 static const int debug_openpic
= 0;
52 #define DPRINTF(fmt, ...) do { \
53 if (debug_openpic) { \
54 printf(fmt , ## __VA_ARGS__); \
63 #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
64 #define VID 0x03 /* MPIC version ID */
66 /* OpenPIC capability flags */
67 #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
69 /* OpenPIC address map */
70 #define OPENPIC_GLB_REG_START 0x0
71 #define OPENPIC_GLB_REG_SIZE 0x10F0
72 #define OPENPIC_TMR_REG_START 0x10F0
73 #define OPENPIC_TMR_REG_SIZE 0x220
74 #define OPENPIC_MSI_REG_START 0x1600
75 #define OPENPIC_MSI_REG_SIZE 0x200
76 #define OPENPIC_SRC_REG_START 0x10000
77 #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
78 #define OPENPIC_CPU_REG_START 0x20000
79 #define OPENPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
82 #define RAVEN_MAX_CPU 2
83 #define RAVEN_MAX_EXT 48
84 #define RAVEN_MAX_IRQ 64
85 #define RAVEN_MAX_TMR MAX_TMR
86 #define RAVEN_MAX_IPI MAX_IPI
88 /* Interrupt definitions */
89 #define RAVEN_FE_IRQ (RAVEN_MAX_EXT) /* Internal functional IRQ */
90 #define RAVEN_ERR_IRQ (RAVEN_MAX_EXT + 1) /* Error IRQ */
91 #define RAVEN_TMR_IRQ (RAVEN_MAX_EXT + 2) /* First timer IRQ */
92 #define RAVEN_IPI_IRQ (RAVEN_TMR_IRQ + RAVEN_MAX_TMR) /* First IPI IRQ */
93 /* First doorbell IRQ */
94 #define RAVEN_DBL_IRQ (RAVEN_IPI_IRQ + (RAVEN_MAX_CPU * RAVEN_MAX_IPI))
97 #define FSL_MPIC_20_MAX_CPU 1
98 #define FSL_MPIC_20_MAX_EXT 12
99 #define FSL_MPIC_20_MAX_INT 64
100 #define FSL_MPIC_20_MAX_IRQ MAX_IRQ
102 /* Interrupt definitions */
103 /* IRQs, accessible through the IRQ region */
104 #define FSL_MPIC_20_EXT_IRQ 0x00
105 #define FSL_MPIC_20_INT_IRQ 0x10
106 #define FSL_MPIC_20_MSG_IRQ 0xb0
107 #define FSL_MPIC_20_MSI_IRQ 0xe0
108 /* These are available through separate regions, but
109 for simplicity's sake mapped into the same number space */
110 #define FSL_MPIC_20_TMR_IRQ 0x100
111 #define FSL_MPIC_20_IPI_IRQ 0x104
114 * Block Revision Register1 (BRR1): QEMU does not fully emulate
115 * any version on MPIC. So to start with, set the IP version to 0.
117 * NOTE: This is Freescale MPIC specific register. Keep it here till
118 * this code is refactored for different variants of OPENPIC and MPIC.
120 #define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */
121 #define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
122 #define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
124 #define FRR_NIRQ_SHIFT 16
125 #define FRR_NCPU_SHIFT 8
126 #define FRR_VID_SHIFT 0
128 #define VID_REVISION_1_2 2
129 #define VID_REVISION_1_3 3
131 #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
133 #define GCR_RESET 0x80000000
134 #define GCR_MODE_PASS 0x00000000
135 #define GCR_MODE_MIXED 0x20000000
136 #define GCR_MODE_PROXY 0x60000000
138 #define TBCR_CI 0x80000000 /* count inhibit */
139 #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
141 #define IDR_EP_SHIFT 31
142 #define IDR_EP_MASK (1 << IDR_EP_SHIFT)
143 #define IDR_CI0_SHIFT 30
144 #define IDR_CI1_SHIFT 29
145 #define IDR_P1_SHIFT 1
146 #define IDR_P0_SHIFT 0
148 #define MSIIR_OFFSET 0x140
149 #define MSIIR_SRS_SHIFT 29
150 #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
151 #define MSIIR_IBS_SHIFT 24
152 #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
154 static int get_current_cpu(void)
156 CPUState
*cpu_single_cpu
;
158 if (!cpu_single_env
) {
162 cpu_single_cpu
= ENV_GET_CPU(cpu_single_env
);
163 return cpu_single_cpu
->cpu_index
;
166 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
168 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
169 uint32_t val
, int idx
);
171 typedef enum IRQType
{
173 IRQ_TYPE_FSLINT
, /* FSL internal interrupt -- level only */
174 IRQ_TYPE_FSLSPECIAL
, /* FSL timer/IPI interrupt, edge, no polarity */
177 typedef struct IRQQueue
{
178 /* Round up to the nearest 64 IRQs so that the queue length
179 * won't change when moving between 32 and 64 bit hosts.
181 unsigned long queue
[BITS_TO_LONGS((MAX_IRQ
+ 63) & ~63)];
186 typedef struct IRQSource
{
187 uint32_t ivpr
; /* IRQ vector/priority register */
188 uint32_t idr
; /* IRQ destination register */
189 uint32_t destmask
; /* bitmap of CPU destinations */
191 int output
; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
192 int pending
; /* TRUE if IRQ is pending */
194 bool level
:1; /* level-triggered */
195 bool nomask
:1; /* critical interrupts ignore mask on some FSL MPICs */
198 #define IVPR_MASK_SHIFT 31
199 #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT)
200 #define IVPR_ACTIVITY_SHIFT 30
201 #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT)
202 #define IVPR_MODE_SHIFT 29
203 #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT)
204 #define IVPR_POLARITY_SHIFT 23
205 #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT)
206 #define IVPR_SENSE_SHIFT 22
207 #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT)
209 #define IVPR_PRIORITY_MASK (0xF << 16)
210 #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
211 #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
213 /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
214 #define IDR_EP 0x80000000 /* external pin */
215 #define IDR_CI 0x40000000 /* critical interrupt */
217 typedef struct IRQDest
{
218 int32_t ctpr
; /* CPU current task priority */
223 /* Count of IRQ sources asserting on non-INT outputs */
224 uint32_t outputs_active
[OPENPIC_OUTPUT_NB
];
227 typedef struct OpenPICState
{
231 /* Behavior control */
236 uint32_t vir
; /* Vendor identification register */
237 uint32_t vector_mask
;
242 uint32_t mpic_mode_mask
;
245 MemoryRegion sub_io_mem
[5];
247 /* Global registers */
248 uint32_t frr
; /* Feature reporting register */
249 uint32_t gcr
; /* Global configuration register */
250 uint32_t pir
; /* Processor initialization register */
251 uint32_t spve
; /* Spurious vector register */
252 uint32_t tfrr
; /* Timer frequency reporting register */
253 /* Source registers */
254 IRQSource src
[MAX_IRQ
];
255 /* Local registers per output pin */
256 IRQDest dst
[MAX_CPU
];
258 /* Timer registers */
260 uint32_t tccr
; /* Global timer current count register */
261 uint32_t tbcr
; /* Global timer base count register */
263 /* Shared MSI registers */
265 uint32_t msir
; /* Shared Message Signaled Interrupt Register */
273 static inline void IRQ_setbit(IRQQueue
*q
, int n_IRQ
)
275 set_bit(n_IRQ
, q
->queue
);
278 static inline void IRQ_resetbit(IRQQueue
*q
, int n_IRQ
)
280 clear_bit(n_IRQ
, q
->queue
);
283 static inline int IRQ_testbit(IRQQueue
*q
, int n_IRQ
)
285 return test_bit(n_IRQ
, q
->queue
);
288 static void IRQ_check(OpenPICState
*opp
, IRQQueue
*q
)
295 irq
= find_next_bit(q
->queue
, opp
->max_irq
, irq
+ 1);
296 if (irq
== opp
->max_irq
) {
300 DPRINTF("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
301 irq
, IVPR_PRIORITY(opp
->src
[irq
].ivpr
), priority
);
303 if (IVPR_PRIORITY(opp
->src
[irq
].ivpr
) > priority
) {
305 priority
= IVPR_PRIORITY(opp
->src
[irq
].ivpr
);
310 q
->priority
= priority
;
313 static int IRQ_get_next(OpenPICState
*opp
, IRQQueue
*q
)
321 static void IRQ_local_pipe(OpenPICState
*opp
, int n_CPU
, int n_IRQ
,
322 bool active
, bool was_active
)
328 dst
= &opp
->dst
[n_CPU
];
329 src
= &opp
->src
[n_IRQ
];
331 DPRINTF("%s: IRQ %d active %d was %d\n",
332 __func__
, n_IRQ
, active
, was_active
);
334 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
335 DPRINTF("%s: output %d irq %d active %d was %d count %d\n",
336 __func__
, src
->output
, n_IRQ
, active
, was_active
,
337 dst
->outputs_active
[src
->output
]);
339 /* On Freescale MPIC, critical interrupts ignore priority,
340 * IACK, EOI, etc. Before MPIC v4.1 they also ignore
344 if (!was_active
&& dst
->outputs_active
[src
->output
]++ == 0) {
345 DPRINTF("%s: Raise OpenPIC output %d cpu %d irq %d\n",
346 __func__
, src
->output
, n_CPU
, n_IRQ
);
347 qemu_irq_raise(dst
->irqs
[src
->output
]);
350 if (was_active
&& --dst
->outputs_active
[src
->output
] == 0) {
351 DPRINTF("%s: Lower OpenPIC output %d cpu %d irq %d\n",
352 __func__
, src
->output
, n_CPU
, n_IRQ
);
353 qemu_irq_lower(dst
->irqs
[src
->output
]);
360 priority
= IVPR_PRIORITY(src
->ivpr
);
362 /* Even if the interrupt doesn't have enough priority,
363 * it is still raised, in case ctpr is lowered later.
366 IRQ_setbit(&dst
->raised
, n_IRQ
);
368 IRQ_resetbit(&dst
->raised
, n_IRQ
);
371 IRQ_check(opp
, &dst
->raised
);
373 if (active
&& priority
<= dst
->ctpr
) {
374 DPRINTF("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
375 __func__
, n_IRQ
, priority
, dst
->ctpr
, n_CPU
);
380 if (IRQ_get_next(opp
, &dst
->servicing
) >= 0 &&
381 priority
<= dst
->servicing
.priority
) {
382 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
383 __func__
, n_IRQ
, dst
->servicing
.next
, n_CPU
);
385 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
386 __func__
, n_CPU
, n_IRQ
, dst
->raised
.next
);
387 qemu_irq_raise(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
390 IRQ_get_next(opp
, &dst
->servicing
);
391 if (dst
->raised
.priority
> dst
->ctpr
&&
392 dst
->raised
.priority
> dst
->servicing
.priority
) {
393 DPRINTF("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
394 __func__
, n_IRQ
, dst
->raised
.next
, dst
->raised
.priority
,
395 dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
396 /* IRQ line stays asserted */
398 DPRINTF("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
399 __func__
, n_IRQ
, dst
->ctpr
, dst
->servicing
.priority
, n_CPU
);
400 qemu_irq_lower(opp
->dst
[n_CPU
].irqs
[OPENPIC_OUTPUT_INT
]);
405 /* update pic state because registers for n_IRQ have changed value */
406 static void openpic_update_irq(OpenPICState
*opp
, int n_IRQ
)
409 bool active
, was_active
;
412 src
= &opp
->src
[n_IRQ
];
413 active
= src
->pending
;
415 if ((src
->ivpr
& IVPR_MASK_MASK
) && !src
->nomask
) {
416 /* Interrupt source is disabled */
417 DPRINTF("%s: IRQ %d is disabled\n", __func__
, n_IRQ
);
421 was_active
= !!(src
->ivpr
& IVPR_ACTIVITY_MASK
);
424 * We don't have a similar check for already-active because
425 * ctpr may have changed and we need to withdraw the interrupt.
427 if (!active
&& !was_active
) {
428 DPRINTF("%s: IRQ %d is already inactive\n", __func__
, n_IRQ
);
433 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
435 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
440 DPRINTF("%s: IRQ %d has no target\n", __func__
, n_IRQ
);
444 if (src
->idr
== (1 << src
->last_cpu
)) {
445 /* Only one CPU is allowed to receive this IRQ */
446 IRQ_local_pipe(opp
, src
->last_cpu
, n_IRQ
, active
, was_active
);
447 } else if (!(src
->ivpr
& IVPR_MODE_MASK
)) {
448 /* Directed delivery mode */
449 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
450 if (src
->destmask
& (1 << i
)) {
451 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
455 /* Distributed delivery mode */
456 for (i
= src
->last_cpu
+ 1; i
!= src
->last_cpu
; i
++) {
457 if (i
== opp
->nb_cpus
) {
460 if (src
->destmask
& (1 << i
)) {
461 IRQ_local_pipe(opp
, i
, n_IRQ
, active
, was_active
);
469 static void openpic_set_irq(void *opaque
, int n_IRQ
, int level
)
471 OpenPICState
*opp
= opaque
;
474 if (n_IRQ
>= MAX_IRQ
) {
475 fprintf(stderr
, "%s: IRQ %d out of range\n", __func__
, n_IRQ
);
479 src
= &opp
->src
[n_IRQ
];
480 DPRINTF("openpic: set irq %d = %d ivpr=0x%08x\n",
481 n_IRQ
, level
, src
->ivpr
);
483 /* level-sensitive irq */
484 src
->pending
= level
;
485 openpic_update_irq(opp
, n_IRQ
);
487 /* edge-sensitive irq */
490 openpic_update_irq(opp
, n_IRQ
);
493 if (src
->output
!= OPENPIC_OUTPUT_INT
) {
494 /* Edge-triggered interrupts shouldn't be used
495 * with non-INT delivery, but just in case,
496 * try to make it do something sane rather than
497 * cause an interrupt storm. This is close to
498 * what you'd probably see happen in real hardware.
501 openpic_update_irq(opp
, n_IRQ
);
506 static void openpic_reset(DeviceState
*d
)
508 OpenPICState
*opp
= FROM_SYSBUS(typeof (*opp
), sysbus_from_qdev(d
));
511 opp
->gcr
= GCR_RESET
;
512 /* Initialise controller registers */
513 opp
->frr
= ((opp
->nb_irqs
- 1) << FRR_NIRQ_SHIFT
) |
514 ((opp
->nb_cpus
- 1) << FRR_NCPU_SHIFT
) |
515 (opp
->vid
<< FRR_VID_SHIFT
);
518 opp
->spve
= -1 & opp
->vector_mask
;
519 opp
->tfrr
= opp
->tfrr_reset
;
520 /* Initialise IRQ sources */
521 for (i
= 0; i
< opp
->max_irq
; i
++) {
522 opp
->src
[i
].ivpr
= opp
->ivpr_reset
;
523 opp
->src
[i
].idr
= opp
->idr_reset
;
525 switch (opp
->src
[i
].type
) {
526 case IRQ_TYPE_NORMAL
:
527 opp
->src
[i
].level
= !!(opp
->ivpr_reset
& IVPR_SENSE_MASK
);
530 case IRQ_TYPE_FSLINT
:
531 opp
->src
[i
].ivpr
|= IVPR_POLARITY_MASK
;
534 case IRQ_TYPE_FSLSPECIAL
:
538 /* Initialise IRQ destinations */
539 for (i
= 0; i
< MAX_CPU
; i
++) {
540 opp
->dst
[i
].ctpr
= 15;
541 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQQueue
));
542 opp
->dst
[i
].raised
.next
= -1;
543 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQQueue
));
544 opp
->dst
[i
].servicing
.next
= -1;
546 /* Initialise timers */
547 for (i
= 0; i
< MAX_TMR
; i
++) {
548 opp
->timers
[i
].tccr
= 0;
549 opp
->timers
[i
].tbcr
= TBCR_CI
;
551 /* Go out of RESET state */
555 static inline uint32_t read_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
)
557 return opp
->src
[n_IRQ
].idr
;
560 static inline uint32_t read_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
)
562 return opp
->src
[n_IRQ
].ivpr
;
565 static inline void write_IRQreg_idr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
567 IRQSource
*src
= &opp
->src
[n_IRQ
];
568 uint32_t normal_mask
= (1UL << opp
->nb_cpus
) - 1;
569 uint32_t crit_mask
= 0;
570 uint32_t mask
= normal_mask
;
571 int crit_shift
= IDR_EP_SHIFT
- opp
->nb_cpus
;
574 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
575 crit_mask
= mask
<< crit_shift
;
576 mask
|= crit_mask
| IDR_EP
;
579 src
->idr
= val
& mask
;
580 DPRINTF("Set IDR %d to 0x%08x\n", n_IRQ
, src
->idr
);
582 if (opp
->flags
& OPENPIC_FLAG_IDR_CRIT
) {
583 if (src
->idr
& crit_mask
) {
584 if (src
->idr
& normal_mask
) {
585 DPRINTF("%s: IRQ configured for multiple output types, using "
586 "critical\n", __func__
);
589 src
->output
= OPENPIC_OUTPUT_CINT
;
593 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
594 int n_ci
= IDR_CI0_SHIFT
- i
;
596 if (src
->idr
& (1UL << n_ci
)) {
597 src
->destmask
|= 1UL << i
;
601 src
->output
= OPENPIC_OUTPUT_INT
;
603 src
->destmask
= src
->idr
& normal_mask
;
606 src
->destmask
= src
->idr
;
610 static inline void write_IRQreg_ivpr(OpenPICState
*opp
, int n_IRQ
, uint32_t val
)
614 /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
615 * the polarity bit is read-only on internal interrupts.
617 mask
= IVPR_MASK_MASK
| IVPR_PRIORITY_MASK
| IVPR_SENSE_MASK
|
618 IVPR_POLARITY_MASK
| opp
->vector_mask
;
620 /* ACTIVITY bit is read-only */
621 opp
->src
[n_IRQ
].ivpr
=
622 (opp
->src
[n_IRQ
].ivpr
& IVPR_ACTIVITY_MASK
) | (val
& mask
);
624 /* For FSL internal interrupts, The sense bit is reserved and zero,
625 * and the interrupt is always level-triggered. Timers and IPIs
626 * have no sense or polarity bits, and are edge-triggered.
628 switch (opp
->src
[n_IRQ
].type
) {
629 case IRQ_TYPE_NORMAL
:
630 opp
->src
[n_IRQ
].level
= !!(opp
->src
[n_IRQ
].ivpr
& IVPR_SENSE_MASK
);
633 case IRQ_TYPE_FSLINT
:
634 opp
->src
[n_IRQ
].ivpr
&= ~IVPR_SENSE_MASK
;
637 case IRQ_TYPE_FSLSPECIAL
:
638 opp
->src
[n_IRQ
].ivpr
&= ~(IVPR_POLARITY_MASK
| IVPR_SENSE_MASK
);
642 openpic_update_irq(opp
, n_IRQ
);
643 DPRINTF("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ
, val
,
644 opp
->src
[n_IRQ
].ivpr
);
647 static void openpic_gbl_write(void *opaque
, hwaddr addr
, uint64_t val
,
650 OpenPICState
*opp
= opaque
;
654 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
655 __func__
, addr
, val
);
660 case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
670 openpic_cpu_write_internal(opp
, addr
, val
, get_current_cpu());
672 case 0x1000: /* FRR */
674 case 0x1020: /* GCR */
675 if (val
& GCR_RESET
) {
676 openpic_reset(&opp
->busdev
.qdev
);
677 } else if (opp
->mpic_mode_mask
) {
681 opp
->gcr
&= ~opp
->mpic_mode_mask
;
682 opp
->gcr
|= val
& opp
->mpic_mode_mask
;
684 /* Set external proxy mode */
685 if ((val
& opp
->mpic_mode_mask
) == GCR_MODE_PROXY
) {
688 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
689 env
->mpic_proxy
= mpic_proxy
;
693 case 0x1080: /* VIR */
695 case 0x1090: /* PIR */
696 for (idx
= 0; idx
< opp
->nb_cpus
; idx
++) {
697 if ((val
& (1 << idx
)) && !(opp
->pir
& (1 << idx
))) {
698 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx
);
699 dst
= &opp
->dst
[idx
];
700 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
701 } else if (!(val
& (1 << idx
)) && (opp
->pir
& (1 << idx
))) {
702 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx
);
703 dst
= &opp
->dst
[idx
];
704 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_RESET
]);
709 case 0x10A0: /* IPI_IVPR */
715 idx
= (addr
- 0x10A0) >> 4;
716 write_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
, val
);
719 case 0x10E0: /* SPVE */
720 opp
->spve
= val
& opp
->vector_mask
;
727 static uint64_t openpic_gbl_read(void *opaque
, hwaddr addr
, unsigned len
)
729 OpenPICState
*opp
= opaque
;
732 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
738 case 0x1000: /* FRR */
741 case 0x1020: /* GCR */
744 case 0x1080: /* VIR */
747 case 0x1090: /* PIR */
750 case 0x00: /* Block Revision Register1 (BRR1) */
761 retval
= openpic_cpu_read_internal(opp
, addr
, get_current_cpu());
763 case 0x10A0: /* IPI_IVPR */
769 idx
= (addr
- 0x10A0) >> 4;
770 retval
= read_IRQreg_ivpr(opp
, opp
->irq_ipi0
+ idx
);
773 case 0x10E0: /* SPVE */
779 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
784 static void openpic_tmr_write(void *opaque
, hwaddr addr
, uint64_t val
,
787 OpenPICState
*opp
= opaque
;
790 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
791 __func__
, addr
, val
);
795 idx
= (addr
>> 6) & 0x3;
803 switch (addr
& 0x30) {
804 case 0x00: /* TCCR */
806 case 0x10: /* TBCR */
807 if ((opp
->timers
[idx
].tccr
& TCCR_TOG
) != 0 &&
808 (val
& TBCR_CI
) == 0 &&
809 (opp
->timers
[idx
].tbcr
& TBCR_CI
) != 0) {
810 opp
->timers
[idx
].tccr
&= ~TCCR_TOG
;
812 opp
->timers
[idx
].tbcr
= val
;
814 case 0x20: /* TVPR */
815 write_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
, val
);
818 write_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
, val
);
823 static uint64_t openpic_tmr_read(void *opaque
, hwaddr addr
, unsigned len
)
825 OpenPICState
*opp
= opaque
;
826 uint32_t retval
= -1;
829 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
833 idx
= (addr
>> 6) & 0x3;
839 switch (addr
& 0x30) {
840 case 0x00: /* TCCR */
841 retval
= opp
->timers
[idx
].tccr
;
843 case 0x10: /* TBCR */
844 retval
= opp
->timers
[idx
].tbcr
;
846 case 0x20: /* TIPV */
847 retval
= read_IRQreg_ivpr(opp
, opp
->irq_tim0
+ idx
);
849 case 0x30: /* TIDE (TIDR) */
850 retval
= read_IRQreg_idr(opp
, opp
->irq_tim0
+ idx
);
855 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
860 static void openpic_src_write(void *opaque
, hwaddr addr
, uint64_t val
,
863 OpenPICState
*opp
= opaque
;
866 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= %08" PRIx64
"\n",
867 __func__
, addr
, val
);
871 addr
= addr
& 0xFFF0;
874 /* EXDE / IFEDE / IEEDE */
875 write_IRQreg_idr(opp
, idx
, val
);
877 /* EXVP / IFEVP / IEEVP */
878 write_IRQreg_ivpr(opp
, idx
, val
);
882 static uint64_t openpic_src_read(void *opaque
, uint64_t addr
, unsigned len
)
884 OpenPICState
*opp
= opaque
;
888 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
893 addr
= addr
& 0xFFF0;
896 /* EXDE / IFEDE / IEEDE */
897 retval
= read_IRQreg_idr(opp
, idx
);
899 /* EXVP / IFEVP / IEEVP */
900 retval
= read_IRQreg_ivpr(opp
, idx
);
902 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
907 static void openpic_msi_write(void *opaque
, hwaddr addr
, uint64_t val
,
910 OpenPICState
*opp
= opaque
;
911 int idx
= opp
->irq_msi
;
914 DPRINTF("%s: addr %#" HWADDR_PRIx
" <= 0x%08" PRIx64
"\n",
915 __func__
, addr
, val
);
922 srs
= val
>> MSIIR_SRS_SHIFT
;
924 ibs
= (val
& MSIIR_IBS_MASK
) >> MSIIR_IBS_SHIFT
;
925 opp
->msi
[srs
].msir
|= 1 << ibs
;
926 openpic_set_irq(opp
, idx
, 1);
929 /* most registers are read-only, thus ignored */
934 static uint64_t openpic_msi_read(void *opaque
, hwaddr addr
, unsigned size
)
936 OpenPICState
*opp
= opaque
;
940 DPRINTF("%s: addr %#" HWADDR_PRIx
"\n", __func__
, addr
);
955 case 0x70: /* MSIRs */
956 r
= opp
->msi
[srs
].msir
;
958 opp
->msi
[srs
].msir
= 0;
959 openpic_set_irq(opp
, opp
->irq_msi
+ srs
, 0);
961 case 0x120: /* MSISR */
962 for (i
= 0; i
< MAX_MSI
; i
++) {
963 r
|= (opp
->msi
[i
].msir
? 1 : 0) << i
;
971 static void openpic_cpu_write_internal(void *opaque
, hwaddr addr
,
972 uint32_t val
, int idx
)
974 OpenPICState
*opp
= opaque
;
979 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
" <= 0x%08x\n", __func__
, idx
,
989 dst
= &opp
->dst
[idx
];
992 case 0x40: /* IPIDR */
996 idx
= (addr
- 0x40) >> 4;
997 /* we use IDE as mask which CPUs to deliver the IPI to still. */
998 write_IRQreg_idr(opp
, opp
->irq_ipi0
+ idx
,
999 opp
->src
[opp
->irq_ipi0
+ idx
].idr
| val
);
1000 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 1);
1001 openpic_set_irq(opp
, opp
->irq_ipi0
+ idx
, 0);
1003 case 0x80: /* CTPR */
1004 dst
->ctpr
= val
& 0x0000000F;
1006 DPRINTF("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
1007 __func__
, idx
, dst
->ctpr
, dst
->raised
.priority
,
1008 dst
->servicing
.priority
);
1010 if (dst
->raised
.priority
<= dst
->ctpr
) {
1011 DPRINTF("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
1013 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1014 } else if (dst
->raised
.priority
> dst
->servicing
.priority
) {
1015 DPRINTF("%s: Raise OpenPIC INT output cpu %d irq %d\n",
1016 __func__
, idx
, dst
->raised
.next
);
1017 qemu_irq_raise(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1021 case 0x90: /* WHOAMI */
1022 /* Read-only register */
1024 case 0xA0: /* IACK */
1025 /* Read-only register */
1027 case 0xB0: /* EOI */
1029 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1032 DPRINTF("%s: EOI with no interrupt in service\n", __func__
);
1036 IRQ_resetbit(&dst
->servicing
, s_IRQ
);
1037 /* Set up next servicing IRQ */
1038 s_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
1039 /* Check queued interrupts. */
1040 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
1041 src
= &opp
->src
[n_IRQ
];
1044 IVPR_PRIORITY(src
->ivpr
) > dst
->servicing
.priority
)) {
1045 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n",
1047 qemu_irq_raise(opp
->dst
[idx
].irqs
[OPENPIC_OUTPUT_INT
]);
1055 static void openpic_cpu_write(void *opaque
, hwaddr addr
, uint64_t val
,
1058 openpic_cpu_write_internal(opaque
, addr
, val
, (addr
& 0x1f000) >> 12);
1062 static uint32_t openpic_iack(OpenPICState
*opp
, IRQDest
*dst
, int cpu
)
1067 DPRINTF("Lower OpenPIC INT output\n");
1068 qemu_irq_lower(dst
->irqs
[OPENPIC_OUTPUT_INT
]);
1070 irq
= IRQ_get_next(opp
, &dst
->raised
);
1071 DPRINTF("IACK: irq=%d\n", irq
);
1074 /* No more interrupt pending */
1078 src
= &opp
->src
[irq
];
1079 if (!(src
->ivpr
& IVPR_ACTIVITY_MASK
) ||
1080 !(IVPR_PRIORITY(src
->ivpr
) > dst
->ctpr
)) {
1081 fprintf(stderr
, "%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
1082 __func__
, irq
, dst
->ctpr
, src
->ivpr
);
1083 openpic_update_irq(opp
, irq
);
1086 /* IRQ enter servicing state */
1087 IRQ_setbit(&dst
->servicing
, irq
);
1088 retval
= IVPR_VECTOR(opp
, src
->ivpr
);
1092 /* edge-sensitive IRQ */
1093 src
->ivpr
&= ~IVPR_ACTIVITY_MASK
;
1095 IRQ_resetbit(&dst
->raised
, irq
);
1098 if ((irq
>= opp
->irq_ipi0
) && (irq
< (opp
->irq_ipi0
+ MAX_IPI
))) {
1099 src
->idr
&= ~(1 << cpu
);
1100 if (src
->idr
&& !src
->level
) {
1101 /* trigger on CPUs that didn't know about it yet */
1102 openpic_set_irq(opp
, irq
, 1);
1103 openpic_set_irq(opp
, irq
, 0);
1104 /* if all CPUs knew about it, set active bit again */
1105 src
->ivpr
|= IVPR_ACTIVITY_MASK
;
1112 static uint32_t openpic_cpu_read_internal(void *opaque
, hwaddr addr
,
1115 OpenPICState
*opp
= opaque
;
1119 DPRINTF("%s: cpu %d addr %#" HWADDR_PRIx
"\n", __func__
, idx
, addr
);
1120 retval
= 0xFFFFFFFF;
1129 dst
= &opp
->dst
[idx
];
1132 case 0x80: /* CTPR */
1135 case 0x90: /* WHOAMI */
1138 case 0xA0: /* IACK */
1139 retval
= openpic_iack(opp
, dst
, idx
);
1141 case 0xB0: /* EOI */
1147 DPRINTF("%s: => 0x%08x\n", __func__
, retval
);
1152 static uint64_t openpic_cpu_read(void *opaque
, hwaddr addr
, unsigned len
)
1154 return openpic_cpu_read_internal(opaque
, addr
, (addr
& 0x1f000) >> 12);
1157 static const MemoryRegionOps openpic_glb_ops_le
= {
1158 .write
= openpic_gbl_write
,
1159 .read
= openpic_gbl_read
,
1160 .endianness
= DEVICE_LITTLE_ENDIAN
,
1162 .min_access_size
= 4,
1163 .max_access_size
= 4,
1167 static const MemoryRegionOps openpic_glb_ops_be
= {
1168 .write
= openpic_gbl_write
,
1169 .read
= openpic_gbl_read
,
1170 .endianness
= DEVICE_BIG_ENDIAN
,
1172 .min_access_size
= 4,
1173 .max_access_size
= 4,
1177 static const MemoryRegionOps openpic_tmr_ops_le
= {
1178 .write
= openpic_tmr_write
,
1179 .read
= openpic_tmr_read
,
1180 .endianness
= DEVICE_LITTLE_ENDIAN
,
1182 .min_access_size
= 4,
1183 .max_access_size
= 4,
1187 static const MemoryRegionOps openpic_tmr_ops_be
= {
1188 .write
= openpic_tmr_write
,
1189 .read
= openpic_tmr_read
,
1190 .endianness
= DEVICE_BIG_ENDIAN
,
1192 .min_access_size
= 4,
1193 .max_access_size
= 4,
1197 static const MemoryRegionOps openpic_cpu_ops_le
= {
1198 .write
= openpic_cpu_write
,
1199 .read
= openpic_cpu_read
,
1200 .endianness
= DEVICE_LITTLE_ENDIAN
,
1202 .min_access_size
= 4,
1203 .max_access_size
= 4,
1207 static const MemoryRegionOps openpic_cpu_ops_be
= {
1208 .write
= openpic_cpu_write
,
1209 .read
= openpic_cpu_read
,
1210 .endianness
= DEVICE_BIG_ENDIAN
,
1212 .min_access_size
= 4,
1213 .max_access_size
= 4,
1217 static const MemoryRegionOps openpic_src_ops_le
= {
1218 .write
= openpic_src_write
,
1219 .read
= openpic_src_read
,
1220 .endianness
= DEVICE_LITTLE_ENDIAN
,
1222 .min_access_size
= 4,
1223 .max_access_size
= 4,
1227 static const MemoryRegionOps openpic_src_ops_be
= {
1228 .write
= openpic_src_write
,
1229 .read
= openpic_src_read
,
1230 .endianness
= DEVICE_BIG_ENDIAN
,
1232 .min_access_size
= 4,
1233 .max_access_size
= 4,
1237 static const MemoryRegionOps openpic_msi_ops_le
= {
1238 .read
= openpic_msi_read
,
1239 .write
= openpic_msi_write
,
1240 .endianness
= DEVICE_LITTLE_ENDIAN
,
1242 .min_access_size
= 4,
1243 .max_access_size
= 4,
1247 static const MemoryRegionOps openpic_msi_ops_be
= {
1248 .read
= openpic_msi_read
,
1249 .write
= openpic_msi_write
,
1250 .endianness
= DEVICE_BIG_ENDIAN
,
1252 .min_access_size
= 4,
1253 .max_access_size
= 4,
1257 static void openpic_save_IRQ_queue(QEMUFile
* f
, IRQQueue
*q
)
1261 for (i
= 0; i
< ARRAY_SIZE(q
->queue
); i
++) {
1262 /* Always put the lower half of a 64-bit long first, in case we
1263 * restore on a 32-bit host. The least significant bits correspond
1264 * to lower IRQ numbers in the bitmap.
1266 qemu_put_be32(f
, (uint32_t)q
->queue
[i
]);
1267 #if LONG_MAX > 0x7FFFFFFF
1268 qemu_put_be32(f
, (uint32_t)(q
->queue
[i
] >> 32));
1272 qemu_put_sbe32s(f
, &q
->next
);
1273 qemu_put_sbe32s(f
, &q
->priority
);
1276 static void openpic_save(QEMUFile
* f
, void *opaque
)
1278 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1281 qemu_put_be32s(f
, &opp
->gcr
);
1282 qemu_put_be32s(f
, &opp
->vir
);
1283 qemu_put_be32s(f
, &opp
->pir
);
1284 qemu_put_be32s(f
, &opp
->spve
);
1285 qemu_put_be32s(f
, &opp
->tfrr
);
1287 qemu_put_be32s(f
, &opp
->nb_cpus
);
1289 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1290 qemu_put_sbe32s(f
, &opp
->dst
[i
].ctpr
);
1291 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1292 openpic_save_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1293 qemu_put_buffer(f
, (uint8_t *)&opp
->dst
[i
].outputs_active
,
1294 sizeof(opp
->dst
[i
].outputs_active
));
1297 for (i
= 0; i
< MAX_TMR
; i
++) {
1298 qemu_put_be32s(f
, &opp
->timers
[i
].tccr
);
1299 qemu_put_be32s(f
, &opp
->timers
[i
].tbcr
);
1302 for (i
= 0; i
< opp
->max_irq
; i
++) {
1303 qemu_put_be32s(f
, &opp
->src
[i
].ivpr
);
1304 qemu_put_be32s(f
, &opp
->src
[i
].idr
);
1305 qemu_put_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1306 qemu_put_sbe32s(f
, &opp
->src
[i
].pending
);
1310 static void openpic_load_IRQ_queue(QEMUFile
* f
, IRQQueue
*q
)
1314 for (i
= 0; i
< ARRAY_SIZE(q
->queue
); i
++) {
1317 val
= qemu_get_be32(f
);
1318 #if LONG_MAX > 0x7FFFFFFF
1320 val
|= qemu_get_be32(f
);
1326 qemu_get_sbe32s(f
, &q
->next
);
1327 qemu_get_sbe32s(f
, &q
->priority
);
1330 static int openpic_load(QEMUFile
* f
, void *opaque
, int version_id
)
1332 OpenPICState
*opp
= (OpenPICState
*)opaque
;
1335 if (version_id
!= 1) {
1339 qemu_get_be32s(f
, &opp
->gcr
);
1340 qemu_get_be32s(f
, &opp
->vir
);
1341 qemu_get_be32s(f
, &opp
->pir
);
1342 qemu_get_be32s(f
, &opp
->spve
);
1343 qemu_get_be32s(f
, &opp
->tfrr
);
1345 qemu_get_be32s(f
, &opp
->nb_cpus
);
1347 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1348 qemu_get_sbe32s(f
, &opp
->dst
[i
].ctpr
);
1349 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].raised
);
1350 openpic_load_IRQ_queue(f
, &opp
->dst
[i
].servicing
);
1351 qemu_get_buffer(f
, (uint8_t *)&opp
->dst
[i
].outputs_active
,
1352 sizeof(opp
->dst
[i
].outputs_active
));
1355 for (i
= 0; i
< MAX_TMR
; i
++) {
1356 qemu_get_be32s(f
, &opp
->timers
[i
].tccr
);
1357 qemu_get_be32s(f
, &opp
->timers
[i
].tbcr
);
1360 for (i
= 0; i
< opp
->max_irq
; i
++) {
1363 val
= qemu_get_be32(f
);
1364 write_IRQreg_idr(opp
, i
, val
);
1365 val
= qemu_get_be32(f
);
1366 write_IRQreg_ivpr(opp
, i
, val
);
1368 qemu_get_be32s(f
, &opp
->src
[i
].ivpr
);
1369 qemu_get_be32s(f
, &opp
->src
[i
].idr
);
1370 qemu_get_sbe32s(f
, &opp
->src
[i
].last_cpu
);
1371 qemu_get_sbe32s(f
, &opp
->src
[i
].pending
);
1377 typedef struct MemReg
{
1379 MemoryRegionOps
const *ops
;
1385 static int openpic_init(SysBusDevice
*dev
)
1387 OpenPICState
*opp
= FROM_SYSBUS(typeof (*opp
), dev
);
1389 MemReg list_le
[] = {
1390 {"glb", &openpic_glb_ops_le
, true,
1391 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1392 {"tmr", &openpic_tmr_ops_le
, true,
1393 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1394 {"msi", &openpic_msi_ops_le
, true,
1395 OPENPIC_MSI_REG_START
, OPENPIC_MSI_REG_SIZE
},
1396 {"src", &openpic_src_ops_le
, true,
1397 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1398 {"cpu", &openpic_cpu_ops_le
, true,
1399 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1401 MemReg list_be
[] = {
1402 {"glb", &openpic_glb_ops_be
, true,
1403 OPENPIC_GLB_REG_START
, OPENPIC_GLB_REG_SIZE
},
1404 {"tmr", &openpic_tmr_ops_be
, true,
1405 OPENPIC_TMR_REG_START
, OPENPIC_TMR_REG_SIZE
},
1406 {"msi", &openpic_msi_ops_be
, true,
1407 OPENPIC_MSI_REG_START
, OPENPIC_MSI_REG_SIZE
},
1408 {"src", &openpic_src_ops_be
, true,
1409 OPENPIC_SRC_REG_START
, OPENPIC_SRC_REG_SIZE
},
1410 {"cpu", &openpic_cpu_ops_be
, true,
1411 OPENPIC_CPU_REG_START
, OPENPIC_CPU_REG_SIZE
},
1415 switch (opp
->model
) {
1416 case OPENPIC_MODEL_FSL_MPIC_20
:
1418 opp
->flags
|= OPENPIC_FLAG_IDR_CRIT
;
1420 opp
->vid
= VID_REVISION_1_2
;
1421 opp
->vir
= VIR_GENERIC
;
1422 opp
->vector_mask
= 0xFFFF;
1423 opp
->tfrr_reset
= 0;
1424 opp
->ivpr_reset
= IVPR_MASK_MASK
;
1425 opp
->idr_reset
= 1 << 0;
1426 opp
->max_irq
= FSL_MPIC_20_MAX_IRQ
;
1427 opp
->irq_ipi0
= FSL_MPIC_20_IPI_IRQ
;
1428 opp
->irq_tim0
= FSL_MPIC_20_TMR_IRQ
;
1429 opp
->irq_msi
= FSL_MPIC_20_MSI_IRQ
;
1430 opp
->brr1
= FSL_BRR1_IPID
| FSL_BRR1_IPMJ
| FSL_BRR1_IPMN
;
1431 /* XXX really only available as of MPIC 4.0 */
1432 opp
->mpic_mode_mask
= GCR_MODE_PROXY
;
1434 msi_supported
= true;
1437 for (i
= 0; i
< FSL_MPIC_20_MAX_EXT
; i
++) {
1438 opp
->src
[i
].level
= false;
1441 /* Internal interrupts, including message and MSI */
1442 for (i
= 16; i
< MAX_SRC
; i
++) {
1443 opp
->src
[i
].type
= IRQ_TYPE_FSLINT
;
1444 opp
->src
[i
].level
= true;
1447 /* timers and IPIs */
1448 for (i
= MAX_SRC
; i
< MAX_IRQ
; i
++) {
1449 opp
->src
[i
].type
= IRQ_TYPE_FSLSPECIAL
;
1450 opp
->src
[i
].level
= false;
1455 case OPENPIC_MODEL_RAVEN
:
1456 opp
->nb_irqs
= RAVEN_MAX_EXT
;
1457 opp
->vid
= VID_REVISION_1_3
;
1458 opp
->vir
= VIR_GENERIC
;
1459 opp
->vector_mask
= 0xFF;
1460 opp
->tfrr_reset
= 4160000;
1461 opp
->ivpr_reset
= IVPR_MASK_MASK
| IVPR_MODE_MASK
;
1463 opp
->max_irq
= RAVEN_MAX_IRQ
;
1464 opp
->irq_ipi0
= RAVEN_IPI_IRQ
;
1465 opp
->irq_tim0
= RAVEN_TMR_IRQ
;
1468 /* Don't map MSI region */
1469 list
[2].map
= false;
1471 /* Only UP supported today */
1472 if (opp
->nb_cpus
!= 1) {
1478 memory_region_init(&opp
->mem
, "openpic", 0x40000);
1480 for (i
= 0; i
< ARRAY_SIZE(list_le
); i
++) {
1485 memory_region_init_io(&opp
->sub_io_mem
[i
], list
[i
].ops
, opp
,
1486 list
[i
].name
, list
[i
].size
);
1488 memory_region_add_subregion(&opp
->mem
, list
[i
].start_addr
,
1489 &opp
->sub_io_mem
[i
]);
1492 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
1493 opp
->dst
[i
].irqs
= g_new(qemu_irq
, OPENPIC_OUTPUT_NB
);
1494 for (j
= 0; j
< OPENPIC_OUTPUT_NB
; j
++) {
1495 sysbus_init_irq(dev
, &opp
->dst
[i
].irqs
[j
]);
1499 register_savevm(&opp
->busdev
.qdev
, "openpic", 0, 2,
1500 openpic_save
, openpic_load
, opp
);
1502 sysbus_init_mmio(dev
, &opp
->mem
);
1503 qdev_init_gpio_in(&dev
->qdev
, openpic_set_irq
, opp
->max_irq
);
1508 static Property openpic_properties
[] = {
1509 DEFINE_PROP_UINT32("model", OpenPICState
, model
, OPENPIC_MODEL_FSL_MPIC_20
),
1510 DEFINE_PROP_UINT32("nb_cpus", OpenPICState
, nb_cpus
, 1),
1511 DEFINE_PROP_END_OF_LIST(),
1514 static void openpic_class_init(ObjectClass
*klass
, void *data
)
1516 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1517 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1519 k
->init
= openpic_init
;
1520 dc
->props
= openpic_properties
;
1521 dc
->reset
= openpic_reset
;
1524 static const TypeInfo openpic_info
= {
1526 .parent
= TYPE_SYS_BUS_DEVICE
,
1527 .instance_size
= sizeof(OpenPICState
),
1528 .class_init
= openpic_class_init
,
1531 static void openpic_register_types(void)
1533 type_register_static(&openpic_info
);
1536 type_init(openpic_register_types
)