]>
git.proxmox.com Git - qemu.git/blob - hw/openpic.c
4 * Copyright (c) 2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Based on OpenPic implementations:
27 * - Intel GW80314 I/O compagnion chip developper's manual
28 * - Motorola MPC8245 & MPC8540 user manuals.
29 * - Motorola MCP750 (aka Raven) programmer manual.
30 * - Motorola Harrier programmer manuel
32 * Serial interrupts, as implemented in Raven chipset are not supported yet.
40 #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...) do { } while (0)
44 #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
46 #define USE_MPCxxx /* Intel model is broken, for now */
48 #if defined (USE_INTEL_GW80314)
49 /* Intel GW80314 I/O Companion chip */
59 #define VID (0x00000000)
61 #define OPENPIC_LITTLE_ENDIAN 1
62 #define OPENPIC_BIG_ENDIAN 0
64 #elif defined(USE_MPCxxx)
74 #define VID 0x03 /* MPIC version ID */
75 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_LITTLE_ENDIAN 1
83 #define OPENPIC_BIG_ENDIAN 0
86 #error "Please select which OpenPic implementation is to be emulated"
89 #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
90 (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN)
94 /* Interrupt definitions */
95 #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
96 #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */
97 #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */
99 #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
100 #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
102 #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
103 #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
106 #define BF_WIDTH(_bits_) \
107 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
109 static inline void set_bit (uint32_t *field
, int bit
)
111 field
[bit
>> 5] |= 1 << (bit
& 0x1F);
114 static inline void reset_bit (uint32_t *field
, int bit
)
116 field
[bit
>> 5] &= ~(1 << (bit
& 0x1F));
119 static inline int test_bit (uint32_t *field
, int bit
)
121 return (field
[bit
>> 5] & 1 << (bit
& 0x1F)) != 0;
131 typedef struct IRQ_queue_t
{
132 uint32_t queue
[BF_WIDTH(MAX_IRQ
)];
137 typedef struct IRQ_src_t
{
138 uint32_t ipvp
; /* IRQ vector/priority register */
139 uint32_t ide
; /* IRQ destination register */
152 #define IPVP_PRIORITY_MASK (0x1F << 16)
153 #define IPVP_PRIORITY(_ipvpr_) (((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)
154 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
155 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
157 typedef struct IRQ_dst_t
{
158 uint32_t pctp
; /* CPU current task priority */
159 uint32_t pcsr
; /* CPU sensitivity register */
161 IRQ_queue_t servicing
;
162 CPUState
*env
; /* Needed if we did SMP */
165 typedef struct openpic_t
{
167 /* Global registers */
168 uint32_t frep
; /* Feature reporting register */
169 uint32_t glbc
; /* Global configuration register */
170 uint32_t micr
; /* MPIC interrupt configuration register */
171 uint32_t veni
; /* Vendor identification register */
172 uint32_t spve
; /* Spurious vector register */
173 uint32_t tifr
; /* Timer frequency reporting register */
174 /* Source registers */
175 IRQ_src_t src
[MAX_IRQ
];
176 /* Local registers per output pin */
177 IRQ_dst_t dst
[MAX_CPU
];
179 /* Timer registers */
181 uint32_t ticc
; /* Global timer current count register */
182 uint32_t tibc
; /* Global timer base count register */
185 /* Doorbell registers */
186 uint32_t dar
; /* Doorbell activate register */
188 uint32_t dmr
; /* Doorbell messaging register */
189 } doorbells
[MAX_DBL
];
192 /* Mailbox registers */
194 uint32_t mbr
; /* Mailbox register */
195 } mailboxes
[MAX_MAILBOXES
];
199 static inline void IRQ_setbit (IRQ_queue_t
*q
, int n_IRQ
)
201 set_bit(q
->queue
, n_IRQ
);
204 static inline void IRQ_resetbit (IRQ_queue_t
*q
, int n_IRQ
)
206 reset_bit(q
->queue
, n_IRQ
);
209 static inline int IRQ_testbit (IRQ_queue_t
*q
, int n_IRQ
)
211 return test_bit(q
->queue
, n_IRQ
);
214 static void IRQ_check (openpic_t
*opp
, IRQ_queue_t
*q
)
221 for (i
= 0; i
< MAX_IRQ
; i
++) {
222 if (IRQ_testbit(q
, i
)) {
223 if (IPVP_PRIORITY(opp
->src
[i
].ipvp
) > priority
) {
225 priority
= IPVP_PRIORITY(opp
->src
[i
].ipvp
);
230 q
->priority
= priority
;
233 static int IRQ_get_next (openpic_t
*opp
, IRQ_queue_t
*q
)
246 static void IRQ_local_pipe (openpic_t
*opp
, int n_CPU
, int n_IRQ
)
252 dst
= &opp
->dst
[n_CPU
];
253 src
= &opp
->src
[n_IRQ
];
254 priority
= IPVP_PRIORITY(src
->ipvp
);
255 if (priority
<= dst
->pctp
) {
256 /* Too low priority */
259 if (IRQ_testbit(&dst
->raised
, n_IRQ
)) {
263 set_bit(&src
->ipvp
, IPVP_ACTIVITY
);
264 IRQ_setbit(&dst
->raised
, n_IRQ
);
265 if (priority
> dst
->raised
.priority
) {
266 IRQ_get_next(opp
, &dst
->raised
);
267 DPRINTF("Raise CPU IRQ\n");
268 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
272 void openpic_set_IRQ (openpic_t
*opp
, int n_IRQ
, int level
)
277 src
= &opp
->src
[n_IRQ
];
278 if (!test_bit(&src
->ipvp
, IPVP_MASK
)) {
279 /* Interrupt source is disabled */
282 if (IPVP_PRIORITY(src
->ipvp
) == 0) {
283 /* Priority set to zero */
286 if (src
->ide
== 0x00000000) {
291 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
) &&
292 test_bit(&src
->ipvp
, IPVP_SENSE
)) {
293 /* Inactivate a active level-sensitive IRQ */
294 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
297 if (test_bit(&src
->ipvp
, IPVP_ACTIVITY
)) {
298 /* Interrupt already pending */
301 if (!test_bit(&src
->ipvp
, IPVP_MODE
) ||
302 src
->ide
== (1 << src
->last_cpu
)) {
303 /* Directed delivery mode */
304 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
305 if (test_bit(&src
->ide
, i
))
306 IRQ_local_pipe(opp
, i
, n_IRQ
);
309 /* Distributed delivery mode */
310 for (i
= src
->last_cpu
; i
< src
->last_cpu
; i
++) {
313 if (test_bit(&src
->ide
, i
)) {
314 IRQ_local_pipe(opp
, i
, n_IRQ
);
323 static void openpic_reset (openpic_t
*opp
)
327 opp
->glbc
= 0x80000000;
328 /* Initialise controler registers */
329 opp
->frep
= ((EXT_IRQ
- 1) << 16) | ((MAX_CPU
- 1) << 8) | VID
;
331 opp
->spve
= 0x000000FF;
332 opp
->tifr
= 0x003F7A00;
334 opp
->micr
= 0x00000000;
335 /* Initialise IRQ sources */
336 for (i
= 0; i
< MAX_IRQ
; i
++) {
337 opp
->src
[i
].ipvp
= 0xA0000000;
338 opp
->src
[i
].ide
= 0x00000000;
340 /* Initialise IRQ destinations */
341 for (i
= 0; i
< opp
->nb_cpus
; i
++) {
342 opp
->dst
[i
].pctp
= 0x0000000F;
343 opp
->dst
[i
].pcsr
= 0x00000000;
344 memset(&opp
->dst
[i
].raised
, 0, sizeof(IRQ_queue_t
));
345 memset(&opp
->dst
[i
].servicing
, 0, sizeof(IRQ_queue_t
));
347 /* Initialise timers */
348 for (i
= 0; i
< MAX_TMR
; i
++) {
349 opp
->timers
[i
].ticc
= 0x00000000;
350 opp
->timers
[i
].tibc
= 0x80000000;
352 /* Initialise doorbells */
354 opp
->dar
= 0x00000000;
355 for (i
= 0; i
< MAX_DBL
; i
++) {
356 opp
->doorbells
[i
].dmr
= 0x00000000;
359 /* Initialise mailboxes */
361 for (i
= 0; i
< MAX_MBX
; i
++) { /* ? */
362 opp
->mailboxes
[i
].mbr
= 0x00000000;
365 /* Go out of RESET state */
366 opp
->glbc
= 0x00000000;
369 static inline uint32_t read_IRQreg (openpic_t
*opp
, int n_IRQ
, uint32_t reg
)
375 retval
= opp
->src
[n_IRQ
].ipvp
;
378 retval
= opp
->src
[n_IRQ
].ide
;
385 static inline void write_IRQreg (openpic_t
*opp
, int n_IRQ
,
386 uint32_t reg
, uint32_t val
)
392 tmp
= opp
->src
[n_IRQ
].ipvp
& 0x40000000;
394 tmp
|= val
& 0x80000000;
395 if ((opp
->src
[n_IRQ
].type
& IRQ_EXTERNAL
) != 0)
396 tmp
|= val
& 0x40C00000;
397 else if ((opp
->src
[n_IRQ
].type
& IRQ_TIMER
) != 0)
398 tmp
|= val
& 0x00F00000;
400 tmp
|= val
& 0x80000000;
402 opp
->src
[n_IRQ
].ipvp
= tmp
| (val
& 0x000F00FF);
403 DPRINTF("Set IPVP %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ipvp
);
406 tmp
= val
& 0xC0000000;
407 tmp
|= val
& ((1 << MAX_CPU
) - 1);
408 opp
->src
[n_IRQ
].ide
= tmp
;
409 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ
, opp
->src
[n_IRQ
].ide
);
414 #if 0 // Code provision for Intel model
416 static uint32_t read_doorbell_register (openpic_t
*opp
,
417 int n_dbl
, uint32_t offset
)
422 case DBL_IPVP_OFFSET
:
423 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
);
426 retval
= read_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
);
429 retval
= opp
->doorbells
[n_dbl
].dmr
;
436 static void write_doorbell_register (penpic_t
*opp
, int n_dbl
,
437 uint32_t offset
, uint32_t value
)
440 case DBL_IVPR_OFFSET
:
441 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IPVP
, value
);
444 write_IRQreg(opp
, IRQ_DBL0
+ n_dbl
, IRQ_IDE
, value
);
447 opp
->doorbells
[n_dbl
].dmr
= value
;
454 static uint32_t read_mailbox_register (openpic_t
*opp
,
455 int n_mbx
, uint32_t offset
)
461 retval
= opp
->mailboxes
[n_mbx
].mbr
;
463 case MBX_IVPR_OFFSET
:
464 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
);
467 retval
= read_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
);
474 static void write_mailbox_register (openpic_t
*opp
, int n_mbx
,
475 uint32_t address
, uint32_t value
)
479 opp
->mailboxes
[n_mbx
].mbr
= value
;
481 case MBX_IVPR_OFFSET
:
482 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IPVP
, value
);
485 write_IRQreg(opp
, IRQ_MBX0
+ n_mbx
, IRQ_IDE
, value
);
490 #endif /* 0 : Code provision for Intel model */
492 static void openpic_gbl_write (void *opaque
, uint32_t addr
, uint32_t val
)
494 openpic_t
*opp
= opaque
;
496 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
499 #if defined OPENPIC_SWAP
504 case 0x00: /* FREP */
506 case 0x20: /* GLBC */
507 if (val
& 0x80000000)
509 opp
->glbc
= val
& ~0x80000000;
511 case 0x80: /* VENI */
513 case 0x90: /* PINT */
514 /* XXX: Should be able to reset any CPU */
516 DPRINTF("Reset CPU IRQ\n");
517 // cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET);
521 case 0xA0: /* IPI_IPVP */
527 idx
= (addr
- 0xA0) >> 4;
528 write_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IPVP
, val
);
532 case 0xE0: /* SPVE */
533 opp
->spve
= val
& 0x000000FF;
535 case 0xF0: /* TIFR */
543 static uint32_t openpic_gbl_read (void *opaque
, uint32_t addr
)
545 openpic_t
*opp
= opaque
;
548 DPRINTF("%s: addr %08x\n", __func__
, addr
);
554 case 0x00: /* FREP */
557 case 0x20: /* GLBC */
560 case 0x80: /* VENI */
563 case 0x90: /* PINT */
567 case 0xA0: /* IPI_IPVP */
573 idx
= (addr
- 0xA0) >> 4;
574 retval
= read_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IPVP
);
578 case 0xE0: /* SPVE */
581 case 0xF0: /* TIFR */
587 DPRINTF("%s: => %08x\n", __func__
, retval
);
588 #if defined OPENPIC_SWAP
589 retval
= bswap32(retval
);
595 static void openpic_timer_write (void *opaque
, uint32_t addr
, uint32_t val
)
597 openpic_t
*opp
= opaque
;
600 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
603 #if defined OPENPIC_SWAP
608 idx
= (addr
& 0xFFF0) >> 6;
611 case 0x00: /* TICC */
613 case 0x10: /* TIBC */
614 if ((opp
->timers
[idx
].ticc
& 0x80000000) != 0 &&
615 (val
& 0x800000000) == 0 &&
616 (opp
->timers
[idx
].tibc
& 0x80000000) != 0)
617 opp
->timers
[idx
].ticc
&= ~0x80000000;
618 opp
->timers
[idx
].tibc
= val
;
620 case 0x20: /* TIVP */
621 write_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IPVP
, val
);
623 case 0x30: /* TIDE */
624 write_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IDE
, val
);
629 static uint32_t openpic_timer_read (void *opaque
, uint32_t addr
)
631 openpic_t
*opp
= opaque
;
635 DPRINTF("%s: addr %08x\n", __func__
, addr
);
641 idx
= (addr
& 0xFFF0) >> 6;
644 case 0x00: /* TICC */
645 retval
= opp
->timers
[idx
].ticc
;
647 case 0x10: /* TIBC */
648 retval
= opp
->timers
[idx
].tibc
;
650 case 0x20: /* TIPV */
651 retval
= read_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IPVP
);
653 case 0x30: /* TIDE */
654 retval
= read_IRQreg(opp
, IRQ_TIM0
+ idx
, IRQ_IDE
);
657 DPRINTF("%s: => %08x\n", __func__
, retval
);
658 #if defined OPENPIC_SWAP
659 retval
= bswap32(retval
);
665 static void openpic_src_write (void *opaque
, uint32_t addr
, uint32_t val
)
667 openpic_t
*opp
= opaque
;
670 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
673 #if defined OPENPIC_SWAP
676 addr
= addr
& 0xFFF0;
679 /* EXDE / IFEDE / IEEDE */
680 write_IRQreg(opp
, idx
, IRQ_IDE
, val
);
682 /* EXVP / IFEVP / IEEVP */
683 write_IRQreg(opp
, idx
, IRQ_IPVP
, val
);
687 static uint32_t openpic_src_read (void *opaque
, uint32_t addr
)
689 openpic_t
*opp
= opaque
;
693 DPRINTF("%s: addr %08x\n", __func__
, addr
);
697 addr
= addr
& 0xFFF0;
700 /* EXDE / IFEDE / IEEDE */
701 retval
= read_IRQreg(opp
, idx
, IRQ_IDE
);
703 /* EXVP / IFEVP / IEEVP */
704 retval
= read_IRQreg(opp
, idx
, IRQ_IPVP
);
706 DPRINTF("%s: => %08x\n", __func__
, retval
);
707 #if defined OPENPIC_SWAP
708 retval
= tswap32(retval
);
714 static void openpic_cpu_write (void *opaque
, uint32_t addr
, uint32_t val
)
716 openpic_t
*opp
= opaque
;
721 DPRINTF("%s: addr %08x <= %08x\n", __func__
, addr
, val
);
724 #if defined OPENPIC_SWAP
729 dst
= &opp
->dst
[idx
];
733 case 0x40: /* PIPD */
737 idx
= (addr
- 0x40) >> 4;
738 write_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IDE
, val
);
739 openpic_set_IRQ(opp
, IRQ_IPI0
+ idx
, 1);
740 openpic_set_IRQ(opp
, IRQ_IPI0
+ idx
, 0);
743 case 0x80: /* PCTP */
744 dst
->pctp
= val
& 0x0000000F;
746 case 0x90: /* WHOAMI */
747 /* Read-only register */
749 case 0xA0: /* PIAC */
750 /* Read-only register */
752 case 0xB0: /* PEOI */
754 n_IRQ
= IRQ_get_next(opp
, &dst
->servicing
);
755 IRQ_resetbit(&dst
->servicing
, n_IRQ
);
756 dst
->servicing
.next
= -1;
757 src
= &opp
->src
[n_IRQ
];
758 /* Set up next servicing IRQ */
759 IRQ_get_next(opp
, &dst
->servicing
);
760 /* Check queued interrupts. */
761 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
763 src
= &opp
->src
[n_IRQ
];
764 if (IPVP_PRIORITY(src
->ipvp
) > dst
->servicing
.priority
) {
765 DPRINTF("Raise CPU IRQ\n");
766 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HARD
);
775 static uint32_t openpic_cpu_read (void *opaque
, uint32_t addr
)
777 openpic_t
*opp
= opaque
;
783 DPRINTF("%s: addr %08x\n", __func__
, addr
);
789 dst
= &opp
->dst
[idx
];
792 case 0x80: /* PCTP */
795 case 0x90: /* WHOAMI */
798 case 0xA0: /* PIAC */
799 n_IRQ
= IRQ_get_next(opp
, &dst
->raised
);
800 DPRINTF("PIAC: irq=%d\n", n_IRQ
);
802 /* No more interrupt pending */
805 src
= &opp
->src
[n_IRQ
];
806 if (!test_bit(&src
->ipvp
, IPVP_ACTIVITY
) ||
807 !(IPVP_PRIORITY(src
->ipvp
) > dst
->pctp
)) {
808 /* - Spurious level-sensitive IRQ
809 * - Priorities has been changed
810 * and the pending IRQ isn't allowed anymore
812 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
813 retval
= IPVP_VECTOR(opp
->spve
);
815 /* IRQ enter servicing state */
816 IRQ_setbit(&dst
->servicing
, n_IRQ
);
817 retval
= IPVP_VECTOR(src
->ipvp
);
819 IRQ_resetbit(&dst
->raised
, n_IRQ
);
820 dst
->raised
.next
= -1;
821 if (!test_bit(&src
->ipvp
, IPVP_SENSE
))
822 reset_bit(&src
->ipvp
, IPVP_ACTIVITY
);
825 case 0xB0: /* PEOI */
831 idx
= (addr
- 0x40) >> 4;
832 retval
= read_IRQreg(opp
, IRQ_IPI0
+ idx
, IRQ_IDE
);
838 DPRINTF("%s: => %08x\n", __func__
, retval
);
839 #if defined OPENPIC_SWAP
840 retval
= bswap32(retval
);
846 static void openpic_buggy_write (void *opaque
,
847 target_phys_addr_t addr
, uint32_t val
)
849 printf("Invalid OPENPIC write access !\n");
852 static uint32_t openpic_buggy_read (void *opaque
, target_phys_addr_t addr
)
854 printf("Invalid OPENPIC read access !\n");
859 static void openpic_writel (void *opaque
,
860 target_phys_addr_t addr
, uint32_t val
)
862 openpic_t
*opp
= opaque
;
865 DPRINTF("%s: offset %08lx val: %08x\n", __func__
, addr
, val
);
867 /* Global registers */
868 openpic_gbl_write(opp
, addr
, val
);
869 } else if (addr
< 0x10000) {
870 /* Timers registers */
871 openpic_timer_write(opp
, addr
, val
);
872 } else if (addr
< 0x20000) {
873 /* Source registers */
874 openpic_src_write(opp
, addr
, val
);
877 openpic_cpu_write(opp
, addr
, val
);
881 static uint32_t openpic_readl (void *opaque
,target_phys_addr_t addr
)
883 openpic_t
*opp
= opaque
;
887 DPRINTF("%s: offset %08lx\n", __func__
, addr
);
889 /* Global registers */
890 retval
= openpic_gbl_read(opp
, addr
);
891 } else if (addr
< 0x10000) {
892 /* Timers registers */
893 retval
= openpic_timer_read(opp
, addr
);
894 } else if (addr
< 0x20000) {
895 /* Source registers */
896 retval
= openpic_src_read(opp
, addr
);
899 retval
= openpic_cpu_read(opp
, addr
);
905 static CPUWriteMemoryFunc
*openpic_write
[] = {
906 &openpic_buggy_write
,
907 &openpic_buggy_write
,
911 static CPUReadMemoryFunc
*openpic_read
[] = {
917 static void openpic_map(PCIDevice
*pci_dev
, int region_num
,
918 uint32_t addr
, uint32_t size
, int type
)
923 DPRINTF("Map OpenPIC\n");
924 opp
= (openpic_t
*)pci_dev
;
925 /* Global registers */
926 DPRINTF("Register OPENPIC gbl %08x => %08x\n",
927 addr
+ 0x1000, addr
+ 0x1000 + 0x100);
928 /* Timer registers */
929 DPRINTF("Register OPENPIC timer %08x => %08x\n",
930 addr
+ 0x1100, addr
+ 0x1100 + 0x40 * MAX_TMR
);
931 /* Interrupt source registers */
932 DPRINTF("Register OPENPIC src %08x => %08x\n",
933 addr
+ 0x10000, addr
+ 0x10000 + 0x20 * (EXT_IRQ
+ 2));
934 /* Per CPU registers */
935 DPRINTF("Register OPENPIC dst %08x => %08x\n",
936 addr
+ 0x20000, addr
+ 0x20000 + 0x1000 * MAX_CPU
);
937 opp_io_memory
= cpu_register_io_memory(0, openpic_read
,
939 cpu_register_physical_memory(addr
, 0x40000, opp_io_memory
);
940 #if 0 // Don't implement ISU for now
941 opp_io_memory
= cpu_register_io_memory(0, openpic_src_read
,
943 cpu_register_physical_memory(isu_base
, 0x20 * (EXT_IRQ
+ 2),
948 openpic_t
*openpic_init (uint32_t isu_base
, uint32_t idu_base
, int nb_cpus
)
954 /* XXX: for now, only one CPU is supported */
957 opp
= (openpic_t
*)pci_register_device("OpenPIC", sizeof(openpic_t
),
961 pci_conf
= opp
->pci_dev
.config
;
962 pci_conf
[0x00] = 0x14; // IBM MPIC2
963 pci_conf
[0x01] = 0x10;
964 pci_conf
[0x02] = 0xFF;
965 pci_conf
[0x03] = 0xFF;
966 pci_conf
[0x0a] = 0x80; // PIC
967 pci_conf
[0x0b] = 0x08;
968 pci_conf
[0x0e] = 0x00; // header_type
969 pci_conf
[0x3d] = 0x00; // no interrupt pin
971 /* Register I/O spaces */
972 pci_register_io_region((PCIDevice
*)opp
, 0, 0x40000,
973 PCI_ADDRESS_SPACE_MEM
, &openpic_map
);
975 isu_base
&= 0xFFFC0000;
976 opp
->nb_cpus
= nb_cpus
;
978 for (i
= 0; i
< EXT_IRQ
; i
++) {
979 opp
->src
[i
].type
= IRQ_EXTERNAL
;
981 for (; i
< IRQ_TIM0
; i
++) {
982 opp
->src
[i
].type
= IRQ_SPECIAL
;
990 opp
->src
[i
].type
= IRQ_TIMER
;
992 for (; i
< MAX_IRQ
; i
++) {
993 opp
->src
[i
].type
= IRQ_INTERNAL
;