hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msix.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42
  43 /* output Bochs bios info messages */
  44 //#define DEBUG_BIOS
  45
  46 /* debug PC/ISA interrupts */
  47 //#define DEBUG_IRQ
  48
  49 #ifdef DEBUG_IRQ
  50 #define DPRINTF(fmt, ...)                                       \
  51     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  52 #else
  53 #define DPRINTF(fmt, ...)
  54 #endif
  55
  56 #define BIOS_FILENAME "bios.bin"
  57
  58 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  59
  60 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  61 #define ACPI_DATA_SIZE       0x10000
  62 #define BIOS_CFG_IOPORT 0x510
  63 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  64 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  65 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  66 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  67 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  68
  69 #define MSI_ADDR_BASE 0xfee00000
  70
  71 #define E820_NR_ENTRIES         16
  72
  73 struct e820_entry {
  74     uint64_t address;
  75     uint64_t length;
  76     uint32_t type;
  77 };
  78
  79 struct e820_table {
  80     uint32_t count;
  81     struct e820_entry entry[E820_NR_ENTRIES];
  82 };
  83
  84 static struct e820_table e820_table;
  85
  86 void isa_irq_handler(void *opaque, int n, int level)
  87 {
  88     IsaIrqState *isa = (IsaIrqState *)opaque;
  89
  90     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  91     if (n < 16) {
  92         qemu_set_irq(isa->i8259[n], level);
  93     }
  94     if (isa->ioapic)
  95         qemu_set_irq(isa->ioapic[n], level);
  96 };
  97
  98 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  99 {
 100 }
 101
 102 /* MSDOS compatibility mode FPU exception support */
 103 static qemu_irq ferr_irq;
 104
 105 void pc_register_ferr_irq(qemu_irq irq)
 106 {
 107     ferr_irq = irq;
 108 }
 109
 110 /* XXX: add IGNNE support */
 111 void cpu_set_ferr(CPUX86State *s)
 112 {
 113     qemu_irq_raise(ferr_irq);
 114 }
 115
 116 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 117 {
 118     qemu_irq_lower(ferr_irq);
 119 }
 120
 121 /* TSC handling */
 122 uint64_t cpu_get_tsc(CPUX86State *env)
 123 {
 124     return cpu_get_ticks();
 125 }
 126
 127 /* SMM support */
 128
 129 static cpu_set_smm_t smm_set;
 130 static void *smm_arg;
 131
 132 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 133 {
 134     assert(smm_set == NULL);
 135     assert(smm_arg == NULL);
 136     smm_set = callback;
 137     smm_arg = arg;
 138 }
 139
 140 void cpu_smm_update(CPUState *env)
 141 {
 142     if (smm_set && smm_arg && env == first_cpu)
 143         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 144 }
 145
 146
 147 /* IRQ handling */
 148 int cpu_get_pic_interrupt(CPUState *env)
 149 {
 150     int intno;
 151
 152     intno = apic_get_interrupt(env->apic_state);
 153     if (intno >= 0) {
 154         /* set irq request if a PIC irq is still pending */
 155         /* XXX: improve that */
 156         pic_update_irq(isa_pic);
 157         return intno;
 158     }
 159     /* read the irq from the PIC */
 160     if (!apic_accept_pic_intr(env->apic_state)) {
 161         return -1;
 162     }
 163
 164     intno = pic_read_irq(isa_pic);
 165     return intno;
 166 }
 167
 168 static void pic_irq_request(void *opaque, int irq, int level)
 169 {
 170     CPUState *env = first_cpu;
 171
 172     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 173     if (env->apic_state) {
 174         while (env) {
 175             if (apic_accept_pic_intr(env->apic_state)) {
 176                 apic_deliver_pic_intr(env->apic_state, level);
 177             }
 178             env = env->next_cpu;
 179         }
 180     } else {
 181         if (level)
 182             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 183         else
 184             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 185     }
 186 }
 187
 188 /* PC cmos mappings */
 189
 190 #define REG_EQUIPMENT_BYTE          0x14
 191
 192 static int cmos_get_fd_drive_type(int fd0)
 193 {
 194     int val;
 195
 196     switch (fd0) {
 197     case 0:
 198         /* 1.44 Mb 3"5 drive */
 199         val = 4;
 200         break;
 201     case 1:
 202         /* 2.88 Mb 3"5 drive */
 203         val = 5;
 204         break;
 205     case 2:
 206         /* 1.2 Mb 5"5 drive */
 207         val = 2;
 208         break;
 209     default:
 210         val = 0;
 211         break;
 212     }
 213     return val;
 214 }
 215
 216 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 217                          ISADevice *s)
 218 {
 219     int cylinders, heads, sectors;
 220     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 221     rtc_set_memory(s, type_ofs, 47);
 222     rtc_set_memory(s, info_ofs, cylinders);
 223     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 224     rtc_set_memory(s, info_ofs + 2, heads);
 225     rtc_set_memory(s, info_ofs + 3, 0xff);
 226     rtc_set_memory(s, info_ofs + 4, 0xff);
 227     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 228     rtc_set_memory(s, info_ofs + 6, cylinders);
 229     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 230     rtc_set_memory(s, info_ofs + 8, sectors);
 231 }
 232
 233 /* convert boot_device letter to something recognizable by the bios */
 234 static int boot_device2nibble(char boot_device)
 235 {
 236     switch(boot_device) {
 237     case 'a':
 238     case 'b':
 239         return 0x01; /* floppy boot */
 240     case 'c':
 241         return 0x02; /* hard drive boot */
 242     case 'd':
 243         return 0x03; /* CD-ROM boot */
 244     case 'n':
 245         return 0x04; /* Network boot */
 246     }
 247     return 0;
 248 }
 249
 250 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 251 {
 252 #define PC_MAX_BOOT_DEVICES 3
 253     int nbds, bds[3] = { 0, };
 254     int i;
 255
 256     nbds = strlen(boot_device);
 257     if (nbds > PC_MAX_BOOT_DEVICES) {
 258         error_report("Too many boot devices for PC");
 259         return(1);
 260     }
 261     for (i = 0; i < nbds; i++) {
 262         bds[i] = boot_device2nibble(boot_device[i]);
 263         if (bds[i] == 0) {
 264             error_report("Invalid boot device for PC: '%c'",
 265                          boot_device[i]);
 266             return(1);
 267         }
 268     }
 269     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 270     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 271     return(0);
 272 }
 273
 274 static int pc_boot_set(void *opaque, const char *boot_device)
 275 {
 276     return set_boot_dev(opaque, boot_device, 0);
 277 }
 278
 279 typedef struct pc_cmos_init_late_arg {
 280     ISADevice *rtc_state;
 281     BusState *idebus0, *idebus1;
 282 } pc_cmos_init_late_arg;
 283
 284 static void pc_cmos_init_late(void *opaque)
 285 {
 286     pc_cmos_init_late_arg *arg = opaque;
 287     ISADevice *s = arg->rtc_state;
 288     int val;
 289     BlockDriverState *hd_table[4];
 290     int i;
 291
 292     ide_get_bs(hd_table, arg->idebus0);
 293     ide_get_bs(hd_table + 2, arg->idebus1);
 294
 295     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 296     if (hd_table[0])
 297         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 298     if (hd_table[1])
 299         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 300
 301     val = 0;
 302     for (i = 0; i < 4; i++) {
 303         if (hd_table[i]) {
 304             int cylinders, heads, sectors, translation;
 305             /* NOTE: bdrv_get_geometry_hint() returns the physical
 306                 geometry.  It is always such that: 1 <= sects <= 63, 1
 307                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 308                 geometry can be different if a translation is done. */
 309             translation = bdrv_get_translation_hint(hd_table[i]);
 310             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 311                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 312                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 313                     /* No translation. */
 314                     translation = 0;
 315                 } else {
 316                     /* LBA translation. */
 317                     translation = 1;
 318                 }
 319             } else {
 320                 translation--;
 321             }
 322             val |= translation << (i * 2);
 323         }
 324     }
 325     rtc_set_memory(s, 0x39, val);
 326
 327     qemu_unregister_reset(pc_cmos_init_late, opaque);
 328 }
 329
 330 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 331                   const char *boot_device,
 332                   BusState *idebus0, BusState *idebus1,
 333                   FDCtrl *floppy_controller, ISADevice *s)
 334 {
 335     int val;
 336     int fd0, fd1, nb;
 337     static pc_cmos_init_late_arg arg;
 338
 339     /* various important CMOS locations needed by PC/Bochs bios */
 340
 341     /* memory size */
 342     val = 640; /* base memory in K */
 343     rtc_set_memory(s, 0x15, val);
 344     rtc_set_memory(s, 0x16, val >> 8);
 345
 346     val = (ram_size / 1024) - 1024;
 347     if (val > 65535)
 348         val = 65535;
 349     rtc_set_memory(s, 0x17, val);
 350     rtc_set_memory(s, 0x18, val >> 8);
 351     rtc_set_memory(s, 0x30, val);
 352     rtc_set_memory(s, 0x31, val >> 8);
 353
 354     if (above_4g_mem_size) {
 355         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 356         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 357         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 358     }
 359
 360     if (ram_size > (16 * 1024 * 1024))
 361         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 362     else
 363         val = 0;
 364     if (val > 65535)
 365         val = 65535;
 366     rtc_set_memory(s, 0x34, val);
 367     rtc_set_memory(s, 0x35, val >> 8);
 368
 369     /* set the number of CPU */
 370     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 371
 372     /* set boot devices, and disable floppy signature check if requested */
 373     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 374         exit(1);
 375     }
 376
 377     /* floppy type */
 378
 379     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 380     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 381
 382     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 383     rtc_set_memory(s, 0x10, val);
 384
 385     val = 0;
 386     nb = 0;
 387     if (fd0 < 3)
 388         nb++;
 389     if (fd1 < 3)
 390         nb++;
 391     switch (nb) {
 392     case 0:
 393         break;
 394     case 1:
 395         val |= 0x01; /* 1 drive, ready for boot */
 396         break;
 397     case 2:
 398         val |= 0x41; /* 2 drives, ready for boot */
 399         break;
 400     }
 401     val |= 0x02; /* FPU is there */
 402     val |= 0x04; /* PS/2 mouse installed */
 403     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 404
 405     /* hard drives */
 406     arg.rtc_state = s;
 407     arg.idebus0 = idebus0;
 408     arg.idebus1 = idebus1;
 409     qemu_register_reset(pc_cmos_init_late, &arg);
 410 }
 411
 412 static void handle_a20_line_change(void *opaque, int irq, int level)
 413 {
 414     CPUState *cpu = opaque;
 415
 416     /* XXX: send to all CPUs ? */
 417     cpu_x86_set_a20(cpu, level);
 418 }
 419
 420 /***********************************************************/
 421 /* Bochs BIOS debug ports */
 422
 423 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 424 {
 425     static const char shutdown_str[8] = "Shutdown";
 426     static int shutdown_index = 0;
 427
 428     switch(addr) {
 429         /* Bochs BIOS messages */
 430     case 0x400:
 431     case 0x401:
 432         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 433         exit(1);
 434     case 0x402:
 435     case 0x403:
 436 #ifdef DEBUG_BIOS
 437         fprintf(stderr, "%c", val);
 438 #endif
 439         break;
 440     case 0x8900:
 441         /* same as Bochs power off */
 442         if (val == shutdown_str[shutdown_index]) {
 443             shutdown_index++;
 444             if (shutdown_index == 8) {
 445                 shutdown_index = 0;
 446                 qemu_system_shutdown_request();
 447             }
 448         } else {
 449             shutdown_index = 0;
 450         }
 451         break;
 452
 453         /* LGPL'ed VGA BIOS messages */
 454     case 0x501:
 455     case 0x502:
 456         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 457         exit(1);
 458     case 0x500:
 459     case 0x503:
 460 #ifdef DEBUG_BIOS
 461         fprintf(stderr, "%c", val);
 462 #endif
 463         break;
 464     }
 465 }
 466
 467 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 468 {
 469     int index = e820_table.count;
 470     struct e820_entry *entry;
 471
 472     if (index >= E820_NR_ENTRIES)
 473         return -EBUSY;
 474     entry = &e820_table.entry[index];
 475
 476     entry->address = address;
 477     entry->length = length;
 478     entry->type = type;
 479
 480     e820_table.count++;
 481     return e820_table.count;
 482 }
 483
 484 static void *bochs_bios_init(void)
 485 {
 486     void *fw_cfg;
 487     uint8_t *smbios_table;
 488     size_t smbios_len;
 489     uint64_t *numa_fw_cfg;
 490     int i, j;
 491
 492     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 493     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 494     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 495     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 496     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 497
 498     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 499     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 500     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 501     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 502
 503     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 504
 505     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 506     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 507     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 508                      acpi_tables_len);
 509     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 510
 511     smbios_table = smbios_get_table(&smbios_len);
 512     if (smbios_table)
 513         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 514                          smbios_table, smbios_len);
 515     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 516                      sizeof(struct e820_table));
 517
 518     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 519                      sizeof(struct hpet_fw_config));
 520     /* allocate memory for the NUMA channel: one (64bit) word for the number
 521      * of nodes, one word for each VCPU->node and one word for each node to
 522      * hold the amount of memory.
 523      */
 524     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 525     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 526     for (i = 0; i < smp_cpus; i++) {
 527         for (j = 0; j < nb_numa_nodes; j++) {
 528             if (node_cpumask[j] & (1 << i)) {
 529                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 530                 break;
 531             }
 532         }
 533     }
 534     for (i = 0; i < nb_numa_nodes; i++) {
 535         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 536     }
 537     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 538                      (1 + smp_cpus + nb_numa_nodes) * 8);
 539
 540     return fw_cfg;
 541 }
 542
 543 static long get_file_size(FILE *f)
 544 {
 545     long where, size;
 546
 547     /* XXX: on Unix systems, using fstat() probably makes more sense */
 548
 549     where = ftell(f);
 550     fseek(f, 0, SEEK_END);
 551     size = ftell(f);
 552     fseek(f, where, SEEK_SET);
 553
 554     return size;
 555 }
 556
 557 static void load_linux(void *fw_cfg,
 558                        const char *kernel_filename,
 559                        const char *initrd_filename,
 560                        const char *kernel_cmdline,
 561                        target_phys_addr_t max_ram_size)
 562 {
 563     uint16_t protocol;
 564     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 565     uint32_t initrd_max;
 566     uint8_t header[8192], *setup, *kernel, *initrd_data;
 567     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 568     FILE *f;
 569     char *vmode;
 570
 571     /* Align to 16 bytes as a paranoia measure */
 572     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 573
 574     /* load the kernel header */
 575     f = fopen(kernel_filename, "rb");
 576     if (!f || !(kernel_size = get_file_size(f)) ||
 577         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 578         MIN(ARRAY_SIZE(header), kernel_size)) {
 579         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 580                 kernel_filename, strerror(errno));
 581         exit(1);
 582     }
 583
 584     /* kernel protocol version */
 585 #if 0
 586     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 587 #endif
 588     if (ldl_p(header+0x202) == 0x53726448)
 589         protocol = lduw_p(header+0x206);
 590     else {
 591         /* This looks like a multiboot kernel. If it is, let's stop
 592            treating it like a Linux kernel. */
 593         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 594                            kernel_cmdline, kernel_size, header))
 595             return;
 596         protocol = 0;
 597     }
 598
 599     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 600         /* Low kernel */
 601         real_addr    = 0x90000;
 602         cmdline_addr = 0x9a000 - cmdline_size;
 603         prot_addr    = 0x10000;
 604     } else if (protocol < 0x202) {
 605         /* High but ancient kernel */
 606         real_addr    = 0x90000;
 607         cmdline_addr = 0x9a000 - cmdline_size;
 608         prot_addr    = 0x100000;
 609     } else {
 610         /* High and recent kernel */
 611         real_addr    = 0x10000;
 612         cmdline_addr = 0x20000;
 613         prot_addr    = 0x100000;
 614     }
 615
 616 #if 0
 617     fprintf(stderr,
 618             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 619             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 620             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 621             real_addr,
 622             cmdline_addr,
 623             prot_addr);
 624 #endif
 625
 626     /* highest address for loading the initrd */
 627     if (protocol >= 0x203)
 628         initrd_max = ldl_p(header+0x22c);
 629     else
 630         initrd_max = 0x37ffffff;
 631
 632     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 633         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 634
 635     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 636     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 637     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 638                      (uint8_t*)strdup(kernel_cmdline),
 639                      strlen(kernel_cmdline)+1);
 640
 641     if (protocol >= 0x202) {
 642         stl_p(header+0x228, cmdline_addr);
 643     } else {
 644         stw_p(header+0x20, 0xA33F);
 645         stw_p(header+0x22, cmdline_addr-real_addr);
 646     }
 647
 648     /* handle vga= parameter */
 649     vmode = strstr(kernel_cmdline, "vga=");
 650     if (vmode) {
 651         unsigned int video_mode;
 652         /* skip "vga=" */
 653         vmode += 4;
 654         if (!strncmp(vmode, "normal", 6)) {
 655             video_mode = 0xffff;
 656         } else if (!strncmp(vmode, "ext", 3)) {
 657             video_mode = 0xfffe;
 658         } else if (!strncmp(vmode, "ask", 3)) {
 659             video_mode = 0xfffd;
 660         } else {
 661             video_mode = strtol(vmode, NULL, 0);
 662         }
 663         stw_p(header+0x1fa, video_mode);
 664     }
 665
 666     /* loader type */
 667     /* High nybble = B reserved for Qemu; low nybble is revision number.
 668        If this code is substantially changed, you may want to consider
 669        incrementing the revision. */
 670     if (protocol >= 0x200)
 671         header[0x210] = 0xB0;
 672
 673     /* heap */
 674     if (protocol >= 0x201) {
 675         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 676         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 677     }
 678
 679     /* load initrd */
 680     if (initrd_filename) {
 681         if (protocol < 0x200) {
 682             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 683             exit(1);
 684         }
 685
 686         initrd_size = get_image_size(initrd_filename);
 687         if (initrd_size < 0) {
 688             fprintf(stderr, "qemu: error reading initrd %s\n",
 689                     initrd_filename);
 690             exit(1);
 691         }
 692
 693         initrd_addr = (initrd_max-initrd_size) & ~4095;
 694
 695         initrd_data = qemu_malloc(initrd_size);
 696         load_image(initrd_filename, initrd_data);
 697
 698         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 699         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 700         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 701
 702         stl_p(header+0x218, initrd_addr);
 703         stl_p(header+0x21c, initrd_size);
 704     }
 705
 706     /* load kernel and setup */
 707     setup_size = header[0x1f1];
 708     if (setup_size == 0)
 709         setup_size = 4;
 710     setup_size = (setup_size+1)*512;
 711     kernel_size -= setup_size;
 712
 713     setup  = qemu_malloc(setup_size);
 714     kernel = qemu_malloc(kernel_size);
 715     fseek(f, 0, SEEK_SET);
 716     if (fread(setup, 1, setup_size, f) != setup_size) {
 717         fprintf(stderr, "fread() failed\n");
 718         exit(1);
 719     }
 720     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 721         fprintf(stderr, "fread() failed\n");
 722         exit(1);
 723     }
 724     fclose(f);
 725     memcpy(setup, header, MIN(sizeof(header), setup_size));
 726
 727     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 728     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 729     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 730
 731     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 732     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 733     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 734
 735     option_rom[nb_option_roms] = "linuxboot.bin";
 736     nb_option_roms++;
 737 }
 738
 739 #define NE2000_NB_MAX 6
 740
 741 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 742                                               0x280, 0x380 };
 743 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 744
 745 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 746 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 747
 748 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 749 {
 750     struct soundhw *c;
 751
 752     for (c = soundhw; c->name; ++c) {
 753         if (c->enabled) {
 754             if (c->isa) {
 755                 c->init.init_isa(pic);
 756             } else {
 757                 if (pci_bus) {
 758                     c->init.init_pci(pci_bus);
 759                 }
 760             }
 761         }
 762     }
 763 }
 764
 765 void pc_init_ne2k_isa(NICInfo *nd)
 766 {
 767     static int nb_ne2k = 0;
 768
 769     if (nb_ne2k == NE2000_NB_MAX)
 770         return;
 771     isa_ne2000_init(ne2000_io[nb_ne2k],
 772                     ne2000_irq[nb_ne2k], nd);
 773     nb_ne2k++;
 774 }
 775
 776 int cpu_is_bsp(CPUState *env)
 777 {
 778     /* We hard-wire the BSP to the first CPU. */
 779     return env->cpu_index == 0;
 780 }
 781
 782 DeviceState *cpu_get_current_apic(void)
 783 {
 784     if (cpu_single_env) {
 785         return cpu_single_env->apic_state;
 786     } else {
 787         return NULL;
 788     }
 789 }
 790
 791 static DeviceState *apic_init(void *env, uint8_t apic_id)
 792 {
 793     DeviceState *dev;
 794     SysBusDevice *d;
 795     static int apic_mapped;
 796
 797     dev = qdev_create(NULL, "apic");
 798     qdev_prop_set_uint8(dev, "id", apic_id);
 799     qdev_prop_set_ptr(dev, "cpu_env", env);
 800     qdev_init_nofail(dev);
 801     d = sysbus_from_qdev(dev);
 802
 803     /* XXX: mapping more APICs at the same memory location */
 804     if (apic_mapped == 0) {
 805         /* NOTE: the APIC is directly connected to the CPU - it is not
 806            on the global memory bus. */
 807         /* XXX: what if the base changes? */
 808         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 809         apic_mapped = 1;
 810     }
 811
 812     msix_supported = 1;
 813
 814     return dev;
 815 }
 816
 817 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 818    BIOS will read it and start S3 resume at POST Entry */
 819 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 820 {
 821     ISADevice *s = opaque;
 822
 823     if (level) {
 824         rtc_set_memory(s, 0xF, 0xFE);
 825     }
 826 }
 827
 828 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 829 {
 830     CPUState *s = opaque;
 831
 832     if (level) {
 833         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 834     }
 835 }
 836
 837 static void pc_cpu_reset(void *opaque)
 838 {
 839     CPUState *env = opaque;
 840
 841     cpu_reset(env);
 842     env->halted = !cpu_is_bsp(env);
 843 }
 844
 845 static CPUState *pc_new_cpu(const char *cpu_model)
 846 {
 847     CPUState *env;
 848
 849     env = cpu_init(cpu_model);
 850     if (!env) {
 851         fprintf(stderr, "Unable to find x86 CPU definition\n");
 852         exit(1);
 853     }
 854     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 855         env->cpuid_apic_id = env->cpu_index;
 856         env->apic_state = apic_init(env, env->cpuid_apic_id);
 857     }
 858     qemu_register_reset(pc_cpu_reset, env);
 859     pc_cpu_reset(env);
 860     return env;
 861 }
 862
 863 void pc_cpus_init(const char *cpu_model)
 864 {
 865     int i;
 866
 867     /* init CPUs */
 868     if (cpu_model == NULL) {
 869 #ifdef TARGET_X86_64
 870         cpu_model = "qemu64";
 871 #else
 872         cpu_model = "qemu32";
 873 #endif
 874     }
 875
 876     for(i = 0; i < smp_cpus; i++) {
 877         pc_new_cpu(cpu_model);
 878     }
 879 }
 880
 881 void pc_memory_init(ram_addr_t ram_size,
 882                     const char *kernel_filename,
 883                     const char *kernel_cmdline,
 884                     const char *initrd_filename,
 885                     ram_addr_t *below_4g_mem_size_p,
 886                     ram_addr_t *above_4g_mem_size_p)
 887 {
 888     char *filename;
 889     int ret, linux_boot, i;
 890     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 891     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 892     int bios_size, isa_bios_size;
 893     void *fw_cfg;
 894
 895     if (ram_size >= 0xe0000000 ) {
 896         above_4g_mem_size = ram_size - 0xe0000000;
 897         below_4g_mem_size = 0xe0000000;
 898     } else {
 899         below_4g_mem_size = ram_size;
 900     }
 901     *above_4g_mem_size_p = above_4g_mem_size;
 902     *below_4g_mem_size_p = below_4g_mem_size;
 903
 904 #if TARGET_PHYS_ADDR_BITS == 32
 905     if (above_4g_mem_size > 0) {
 906         hw_error("To much RAM for 32-bit physical address");
 907     }
 908 #endif
 909     linux_boot = (kernel_filename != NULL);
 910
 911     /* allocate RAM */
 912     ram_addr = qemu_ram_alloc(NULL, "pc.ram",
 913                               below_4g_mem_size + above_4g_mem_size);
 914     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 915     cpu_register_physical_memory(0x100000,
 916                  below_4g_mem_size - 0x100000,
 917                  ram_addr + 0x100000);
 918 #if TARGET_PHYS_ADDR_BITS > 32
 919     cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
 920                                  ram_addr + below_4g_mem_size);
 921 #endif
 922
 923     /* BIOS load */
 924     if (bios_name == NULL)
 925         bios_name = BIOS_FILENAME;
 926     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 927     if (filename) {
 928         bios_size = get_image_size(filename);
 929     } else {
 930         bios_size = -1;
 931     }
 932     if (bios_size <= 0 ||
 933         (bios_size % 65536) != 0) {
 934         goto bios_error;
 935     }
 936     bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size);
 937     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 938     if (ret != 0) {
 939     bios_error:
 940         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 941         exit(1);
 942     }
 943     if (filename) {
 944         qemu_free(filename);
 945     }
 946     /* map the last 128KB of the BIOS in ISA space */
 947     isa_bios_size = bios_size;
 948     if (isa_bios_size > (128 * 1024))
 949         isa_bios_size = 128 * 1024;
 950     cpu_register_physical_memory(0x100000 - isa_bios_size,
 951                                  isa_bios_size,
 952                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 953
 954     option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE);
 955     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 956
 957     /* map all the bios at the top of memory */
 958     cpu_register_physical_memory((uint32_t)(-bios_size),
 959                                  bios_size, bios_offset | IO_MEM_ROM);
 960
 961     fw_cfg = bochs_bios_init();
 962     rom_set_fw(fw_cfg);
 963
 964     if (linux_boot) {
 965         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 966     }
 967
 968     for (i = 0; i < nb_option_roms; i++) {
 969         rom_add_option(option_rom[i]);
 970     }
 971 }
 972
 973 qemu_irq *pc_allocate_cpu_irq(void)
 974 {
 975     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 976 }
 977
 978 void pc_vga_init(PCIBus *pci_bus)
 979 {
 980     if (cirrus_vga_enabled) {
 981         if (pci_bus) {
 982             pci_cirrus_vga_init(pci_bus);
 983         } else {
 984             isa_cirrus_vga_init();
 985         }
 986     } else if (vmsvga_enabled) {
 987         if (pci_bus)
 988             pci_vmsvga_init(pci_bus);
 989         else
 990             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 991     } else if (std_vga_enabled) {
 992         if (pci_bus) {
 993             pci_vga_init(pci_bus, 0, 0);
 994         } else {
 995             isa_vga_init();
 996         }
 997     }
 998 }
 999
1000 static void cpu_request_exit(void *opaque, int irq, int level)
1001 {
1002     CPUState *env = cpu_single_env;
1003
1004     if (env && level) {
1005         cpu_exit(env);
1006     }
1007 }
1008
1009 void pc_basic_device_init(qemu_irq *isa_irq,
1010                           FDCtrl **floppy_controller,
1011                           ISADevice **rtc_state)
1012 {
1013     int i;
1014     DriveInfo *fd[MAX_FD];
1015     PITState *pit;
1016     qemu_irq rtc_irq = NULL;
1017     qemu_irq *a20_line;
1018     ISADevice *i8042;
1019     qemu_irq *cpu_exit_irq;
1020
1021     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1022
1023     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1024
1025     if (!no_hpet) {
1026         DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
1027
1028         for (i = 0; i < 24; i++) {
1029             sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1030         }
1031         rtc_irq = qdev_get_gpio_in(hpet, 0);
1032     }
1033     *rtc_state = rtc_init(2000, rtc_irq);
1034
1035     qemu_register_boot_set(pc_boot_set, *rtc_state);
1036
1037     pit = pit_init(0x40, isa_reserve_irq(0));
1038     pcspk_init(pit);
1039
1040     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1041         if (serial_hds[i]) {
1042             serial_isa_init(i, serial_hds[i]);
1043         }
1044     }
1045
1046     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1047         if (parallel_hds[i]) {
1048             parallel_init(i, parallel_hds[i]);
1049         }
1050     }
1051
1052     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
1053     i8042 = isa_create_simple("i8042");
1054     i8042_setup_a20_line(i8042, a20_line);
1055     vmmouse_init(i8042);
1056
1057     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1058     DMA_init(0, cpu_exit_irq);
1059
1060     for(i = 0; i < MAX_FD; i++) {
1061         fd[i] = drive_get(IF_FLOPPY, 0, i);
1062     }
1063     *floppy_controller = fdctrl_init_isa(fd);
1064 }
1065
1066 void pc_pci_device_init(PCIBus *pci_bus)
1067 {
1068     int max_bus;
1069     int bus;
1070
1071     max_bus = drive_get_max_bus(IF_SCSI);
1072     for (bus = 0; bus <= max_bus; bus++) {
1073         pci_create_simple(pci_bus, -1, "lsi53c895a");
1074     }
1075 }