hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "monitor.h"
  31 #include "fw_cfg.h"
  32 #include "hpet_emul.h"
  33 #include "smbios.h"
  34 #include "loader.h"
  35 #include "elf.h"
  36 #include "multiboot.h"
  37 #include "mc146818rtc.h"
  38
  39 /* output Bochs bios info messages */
  40 //#define DEBUG_BIOS
  41
  42 #define BIOS_FILENAME "bios.bin"
  43
  44 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  45
  46 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  47 #define ACPI_DATA_SIZE       0x10000
  48 #define BIOS_CFG_IOPORT 0x510
  49 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  50 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  51 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  52 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  53
  54 #define E820_NR_ENTRIES         16
  55
  56 struct e820_entry {
  57     uint64_t address;
  58     uint64_t length;
  59     uint32_t type;
  60 };
  61
  62 struct e820_table {
  63     uint32_t count;
  64     struct e820_entry entry[E820_NR_ENTRIES];
  65 };
  66
  67 static struct e820_table e820_table;
  68
  69 void isa_irq_handler(void *opaque, int n, int level)
  70 {
  71     IsaIrqState *isa = (IsaIrqState *)opaque;
  72
  73     if (n < 16) {
  74         qemu_set_irq(isa->i8259[n], level);
  75     }
  76     if (isa->ioapic)
  77         qemu_set_irq(isa->ioapic[n], level);
  78 };
  79
  80 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  81 {
  82 }
  83
  84 /* MSDOS compatibility mode FPU exception support */
  85 static qemu_irq ferr_irq;
  86
  87 void pc_register_ferr_irq(qemu_irq irq)
  88 {
  89     ferr_irq = irq;
  90 }
  91
  92 /* XXX: add IGNNE support */
  93 void cpu_set_ferr(CPUX86State *s)
  94 {
  95     qemu_irq_raise(ferr_irq);
  96 }
  97
  98 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
  99 {
 100     qemu_irq_lower(ferr_irq);
 101 }
 102
 103 /* TSC handling */
 104 uint64_t cpu_get_tsc(CPUX86State *env)
 105 {
 106     return cpu_get_ticks();
 107 }
 108
 109 /* SMM support */
 110
 111 static cpu_set_smm_t smm_set;
 112 static void *smm_arg;
 113
 114 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 115 {
 116     assert(smm_set == NULL);
 117     assert(smm_arg == NULL);
 118     smm_set = callback;
 119     smm_arg = arg;
 120 }
 121
 122 void cpu_smm_update(CPUState *env)
 123 {
 124     if (smm_set && smm_arg && env == first_cpu)
 125         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 126 }
 127
 128
 129 /* IRQ handling */
 130 int cpu_get_pic_interrupt(CPUState *env)
 131 {
 132     int intno;
 133
 134     intno = apic_get_interrupt(env);
 135     if (intno >= 0) {
 136         /* set irq request if a PIC irq is still pending */
 137         /* XXX: improve that */
 138         pic_update_irq(isa_pic);
 139         return intno;
 140     }
 141     /* read the irq from the PIC */
 142     if (!apic_accept_pic_intr(env))
 143         return -1;
 144
 145     intno = pic_read_irq(isa_pic);
 146     return intno;
 147 }
 148
 149 static void pic_irq_request(void *opaque, int irq, int level)
 150 {
 151     CPUState *env = first_cpu;
 152
 153     if (env->apic_state) {
 154         while (env) {
 155             if (apic_accept_pic_intr(env))
 156                 apic_deliver_pic_intr(env, level);
 157             env = env->next_cpu;
 158         }
 159     } else {
 160         if (level)
 161             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 162         else
 163             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 164     }
 165 }
 166
 167 /* PC cmos mappings */
 168
 169 #define REG_EQUIPMENT_BYTE          0x14
 170
 171 static int cmos_get_fd_drive_type(int fd0)
 172 {
 173     int val;
 174
 175     switch (fd0) {
 176     case 0:
 177         /* 1.44 Mb 3"5 drive */
 178         val = 4;
 179         break;
 180     case 1:
 181         /* 2.88 Mb 3"5 drive */
 182         val = 5;
 183         break;
 184     case 2:
 185         /* 1.2 Mb 5"5 drive */
 186         val = 2;
 187         break;
 188     default:
 189         val = 0;
 190         break;
 191     }
 192     return val;
 193 }
 194
 195 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 196                          ISADevice *s)
 197 {
 198     int cylinders, heads, sectors;
 199     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 200     rtc_set_memory(s, type_ofs, 47);
 201     rtc_set_memory(s, info_ofs, cylinders);
 202     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 203     rtc_set_memory(s, info_ofs + 2, heads);
 204     rtc_set_memory(s, info_ofs + 3, 0xff);
 205     rtc_set_memory(s, info_ofs + 4, 0xff);
 206     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 207     rtc_set_memory(s, info_ofs + 6, cylinders);
 208     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 209     rtc_set_memory(s, info_ofs + 8, sectors);
 210 }
 211
 212 /* convert boot_device letter to something recognizable by the bios */
 213 static int boot_device2nibble(char boot_device)
 214 {
 215     switch(boot_device) {
 216     case 'a':
 217     case 'b':
 218         return 0x01; /* floppy boot */
 219     case 'c':
 220         return 0x02; /* hard drive boot */
 221     case 'd':
 222         return 0x03; /* CD-ROM boot */
 223     case 'n':
 224         return 0x04; /* Network boot */
 225     }
 226     return 0;
 227 }
 228
 229 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 230 {
 231 #define PC_MAX_BOOT_DEVICES 3
 232     int nbds, bds[3] = { 0, };
 233     int i;
 234
 235     nbds = strlen(boot_device);
 236     if (nbds > PC_MAX_BOOT_DEVICES) {
 237         error_report("Too many boot devices for PC");
 238         return(1);
 239     }
 240     for (i = 0; i < nbds; i++) {
 241         bds[i] = boot_device2nibble(boot_device[i]);
 242         if (bds[i] == 0) {
 243             error_report("Invalid boot device for PC: '%c'",
 244                          boot_device[i]);
 245             return(1);
 246         }
 247     }
 248     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 249     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 250     return(0);
 251 }
 252
 253 static int pc_boot_set(void *opaque, const char *boot_device)
 254 {
 255     return set_boot_dev(opaque, boot_device, 0);
 256 }
 257
 258 /* hd_table must contain 4 block drivers */
 259 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 260                   const char *boot_device, DriveInfo **hd_table,
 261                   FDCtrl *floppy_controller, ISADevice *s)
 262 {
 263     int val;
 264     int fd0, fd1, nb;
 265     int i;
 266
 267     /* various important CMOS locations needed by PC/Bochs bios */
 268
 269     /* memory size */
 270     val = 640; /* base memory in K */
 271     rtc_set_memory(s, 0x15, val);
 272     rtc_set_memory(s, 0x16, val >> 8);
 273
 274     val = (ram_size / 1024) - 1024;
 275     if (val > 65535)
 276         val = 65535;
 277     rtc_set_memory(s, 0x17, val);
 278     rtc_set_memory(s, 0x18, val >> 8);
 279     rtc_set_memory(s, 0x30, val);
 280     rtc_set_memory(s, 0x31, val >> 8);
 281
 282     if (above_4g_mem_size) {
 283         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 284         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 285         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 286     }
 287
 288     if (ram_size > (16 * 1024 * 1024))
 289         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 290     else
 291         val = 0;
 292     if (val > 65535)
 293         val = 65535;
 294     rtc_set_memory(s, 0x34, val);
 295     rtc_set_memory(s, 0x35, val >> 8);
 296
 297     /* set the number of CPU */
 298     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 299
 300     /* set boot devices, and disable floppy signature check if requested */
 301     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 302         exit(1);
 303     }
 304
 305     /* floppy type */
 306
 307     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 308     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 309
 310     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 311     rtc_set_memory(s, 0x10, val);
 312
 313     val = 0;
 314     nb = 0;
 315     if (fd0 < 3)
 316         nb++;
 317     if (fd1 < 3)
 318         nb++;
 319     switch (nb) {
 320     case 0:
 321         break;
 322     case 1:
 323         val |= 0x01; /* 1 drive, ready for boot */
 324         break;
 325     case 2:
 326         val |= 0x41; /* 2 drives, ready for boot */
 327         break;
 328     }
 329     val |= 0x02; /* FPU is there */
 330     val |= 0x04; /* PS/2 mouse installed */
 331     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 332
 333     /* hard drives */
 334
 335     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 336     if (hd_table[0])
 337         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv, s);
 338     if (hd_table[1])
 339         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv, s);
 340
 341     val = 0;
 342     for (i = 0; i < 4; i++) {
 343         if (hd_table[i]) {
 344             int cylinders, heads, sectors, translation;
 345             /* NOTE: bdrv_get_geometry_hint() returns the physical
 346                 geometry.  It is always such that: 1 <= sects <= 63, 1
 347                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 348                 geometry can be different if a translation is done. */
 349             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 350             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 351                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 352                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 353                     /* No translation. */
 354                     translation = 0;
 355                 } else {
 356                     /* LBA translation. */
 357                     translation = 1;
 358                 }
 359             } else {
 360                 translation--;
 361             }
 362             val |= translation << (i * 2);
 363         }
 364     }
 365     rtc_set_memory(s, 0x39, val);
 366 }
 367
 368 static void handle_a20_line_change(void *opaque, int irq, int level)
 369 {
 370     CPUState *cpu = opaque;
 371
 372     /* XXX: send to all CPUs ? */
 373     cpu_x86_set_a20(cpu, level);
 374 }
 375
 376 /***********************************************************/
 377 /* Bochs BIOS debug ports */
 378
 379 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 380 {
 381     static const char shutdown_str[8] = "Shutdown";
 382     static int shutdown_index = 0;
 383
 384     switch(addr) {
 385         /* Bochs BIOS messages */
 386     case 0x400:
 387     case 0x401:
 388         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 389         exit(1);
 390     case 0x402:
 391     case 0x403:
 392 #ifdef DEBUG_BIOS
 393         fprintf(stderr, "%c", val);
 394 #endif
 395         break;
 396     case 0x8900:
 397         /* same as Bochs power off */
 398         if (val == shutdown_str[shutdown_index]) {
 399             shutdown_index++;
 400             if (shutdown_index == 8) {
 401                 shutdown_index = 0;
 402                 qemu_system_shutdown_request();
 403             }
 404         } else {
 405             shutdown_index = 0;
 406         }
 407         break;
 408
 409         /* LGPL'ed VGA BIOS messages */
 410     case 0x501:
 411     case 0x502:
 412         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 413         exit(1);
 414     case 0x500:
 415     case 0x503:
 416 #ifdef DEBUG_BIOS
 417         fprintf(stderr, "%c", val);
 418 #endif
 419         break;
 420     }
 421 }
 422
 423 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 424 {
 425     int index = e820_table.count;
 426     struct e820_entry *entry;
 427
 428     if (index >= E820_NR_ENTRIES)
 429         return -EBUSY;
 430     entry = &e820_table.entry[index];
 431
 432     entry->address = address;
 433     entry->length = length;
 434     entry->type = type;
 435
 436     e820_table.count++;
 437     return e820_table.count;
 438 }
 439
 440 static void *bochs_bios_init(void)
 441 {
 442     void *fw_cfg;
 443     uint8_t *smbios_table;
 444     size_t smbios_len;
 445     uint64_t *numa_fw_cfg;
 446     int i, j;
 447
 448     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 449     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 450     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 451     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 452     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 453
 454     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 455     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 456     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 457     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 458
 459     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 460
 461     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 462     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 463     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 464                      acpi_tables_len);
 465     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 466
 467     smbios_table = smbios_get_table(&smbios_len);
 468     if (smbios_table)
 469         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 470                          smbios_table, smbios_len);
 471     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 472                      sizeof(struct e820_table));
 473
 474     /* allocate memory for the NUMA channel: one (64bit) word for the number
 475      * of nodes, one word for each VCPU->node and one word for each node to
 476      * hold the amount of memory.
 477      */
 478     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 479     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 480     for (i = 0; i < smp_cpus; i++) {
 481         for (j = 0; j < nb_numa_nodes; j++) {
 482             if (node_cpumask[j] & (1 << i)) {
 483                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 484                 break;
 485             }
 486         }
 487     }
 488     for (i = 0; i < nb_numa_nodes; i++) {
 489         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 490     }
 491     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 492                      (1 + smp_cpus + nb_numa_nodes) * 8);
 493
 494     return fw_cfg;
 495 }
 496
 497 static long get_file_size(FILE *f)
 498 {
 499     long where, size;
 500
 501     /* XXX: on Unix systems, using fstat() probably makes more sense */
 502
 503     where = ftell(f);
 504     fseek(f, 0, SEEK_END);
 505     size = ftell(f);
 506     fseek(f, where, SEEK_SET);
 507
 508     return size;
 509 }
 510
 511 static void load_linux(void *fw_cfg,
 512                        const char *kernel_filename,
 513                        const char *initrd_filename,
 514                        const char *kernel_cmdline,
 515                        target_phys_addr_t max_ram_size)
 516 {
 517     uint16_t protocol;
 518     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 519     uint32_t initrd_max;
 520     uint8_t header[8192], *setup, *kernel, *initrd_data;
 521     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 522     FILE *f;
 523     char *vmode;
 524
 525     /* Align to 16 bytes as a paranoia measure */
 526     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 527
 528     /* load the kernel header */
 529     f = fopen(kernel_filename, "rb");
 530     if (!f || !(kernel_size = get_file_size(f)) ||
 531         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 532         MIN(ARRAY_SIZE(header), kernel_size)) {
 533         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 534                 kernel_filename, strerror(errno));
 535         exit(1);
 536     }
 537
 538     /* kernel protocol version */
 539 #if 0
 540     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 541 #endif
 542     if (ldl_p(header+0x202) == 0x53726448)
 543         protocol = lduw_p(header+0x206);
 544     else {
 545         /* This looks like a multiboot kernel. If it is, let's stop
 546            treating it like a Linux kernel. */
 547         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 548                            kernel_cmdline, kernel_size, header))
 549             return;
 550         protocol = 0;
 551     }
 552
 553     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 554         /* Low kernel */
 555         real_addr    = 0x90000;
 556         cmdline_addr = 0x9a000 - cmdline_size;
 557         prot_addr    = 0x10000;
 558     } else if (protocol < 0x202) {
 559         /* High but ancient kernel */
 560         real_addr    = 0x90000;
 561         cmdline_addr = 0x9a000 - cmdline_size;
 562         prot_addr    = 0x100000;
 563     } else {
 564         /* High and recent kernel */
 565         real_addr    = 0x10000;
 566         cmdline_addr = 0x20000;
 567         prot_addr    = 0x100000;
 568     }
 569
 570 #if 0
 571     fprintf(stderr,
 572             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 573             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 574             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 575             real_addr,
 576             cmdline_addr,
 577             prot_addr);
 578 #endif
 579
 580     /* highest address for loading the initrd */
 581     if (protocol >= 0x203)
 582         initrd_max = ldl_p(header+0x22c);
 583     else
 584         initrd_max = 0x37ffffff;
 585
 586     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 587         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 588
 589     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 590     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 591     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 592                      (uint8_t*)strdup(kernel_cmdline),
 593                      strlen(kernel_cmdline)+1);
 594
 595     if (protocol >= 0x202) {
 596         stl_p(header+0x228, cmdline_addr);
 597     } else {
 598         stw_p(header+0x20, 0xA33F);
 599         stw_p(header+0x22, cmdline_addr-real_addr);
 600     }
 601
 602     /* handle vga= parameter */
 603     vmode = strstr(kernel_cmdline, "vga=");
 604     if (vmode) {
 605         unsigned int video_mode;
 606         /* skip "vga=" */
 607         vmode += 4;
 608         if (!strncmp(vmode, "normal", 6)) {
 609             video_mode = 0xffff;
 610         } else if (!strncmp(vmode, "ext", 3)) {
 611             video_mode = 0xfffe;
 612         } else if (!strncmp(vmode, "ask", 3)) {
 613             video_mode = 0xfffd;
 614         } else {
 615             video_mode = strtol(vmode, NULL, 0);
 616         }
 617         stw_p(header+0x1fa, video_mode);
 618     }
 619
 620     /* loader type */
 621     /* High nybble = B reserved for Qemu; low nybble is revision number.
 622        If this code is substantially changed, you may want to consider
 623        incrementing the revision. */
 624     if (protocol >= 0x200)
 625         header[0x210] = 0xB0;
 626
 627     /* heap */
 628     if (protocol >= 0x201) {
 629         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 630         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 631     }
 632
 633     /* load initrd */
 634     if (initrd_filename) {
 635         if (protocol < 0x200) {
 636             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 637             exit(1);
 638         }
 639
 640         initrd_size = get_image_size(initrd_filename);
 641         if (initrd_size < 0) {
 642             fprintf(stderr, "qemu: error reading initrd %s\n",
 643                     initrd_filename);
 644             exit(1);
 645         }
 646
 647         initrd_addr = (initrd_max-initrd_size) & ~4095;
 648
 649         initrd_data = qemu_malloc(initrd_size);
 650         load_image(initrd_filename, initrd_data);
 651
 652         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 653         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 654         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 655
 656         stl_p(header+0x218, initrd_addr);
 657         stl_p(header+0x21c, initrd_size);
 658     }
 659
 660     /* load kernel and setup */
 661     setup_size = header[0x1f1];
 662     if (setup_size == 0)
 663         setup_size = 4;
 664     setup_size = (setup_size+1)*512;
 665     kernel_size -= setup_size;
 666
 667     setup  = qemu_malloc(setup_size);
 668     kernel = qemu_malloc(kernel_size);
 669     fseek(f, 0, SEEK_SET);
 670     if (fread(setup, 1, setup_size, f) != setup_size) {
 671         fprintf(stderr, "fread() failed\n");
 672         exit(1);
 673     }
 674     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 675         fprintf(stderr, "fread() failed\n");
 676         exit(1);
 677     }
 678     fclose(f);
 679     memcpy(setup, header, MIN(sizeof(header), setup_size));
 680
 681     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 682     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 683     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 684
 685     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 686     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 687     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 688
 689     option_rom[nb_option_roms] = "linuxboot.bin";
 690     nb_option_roms++;
 691 }
 692
 693 #define NE2000_NB_MAX 6
 694
 695 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 696                                               0x280, 0x380 };
 697 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 698
 699 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 700 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 701
 702 #ifdef HAS_AUDIO
 703 void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
 704 {
 705     struct soundhw *c;
 706
 707     for (c = soundhw; c->name; ++c) {
 708         if (c->enabled) {
 709             if (c->isa) {
 710                 c->init.init_isa(pic);
 711             } else {
 712                 if (pci_bus) {
 713                     c->init.init_pci(pci_bus);
 714                 }
 715             }
 716         }
 717     }
 718 }
 719 #endif
 720
 721 void pc_init_ne2k_isa(NICInfo *nd)
 722 {
 723     static int nb_ne2k = 0;
 724
 725     if (nb_ne2k == NE2000_NB_MAX)
 726         return;
 727     isa_ne2000_init(ne2000_io[nb_ne2k],
 728                     ne2000_irq[nb_ne2k], nd);
 729     nb_ne2k++;
 730 }
 731
 732 int cpu_is_bsp(CPUState *env)
 733 {
 734     /* We hard-wire the BSP to the first CPU. */
 735     return env->cpu_index == 0;
 736 }
 737
 738 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 739    BIOS will read it and start S3 resume at POST Entry */
 740 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 741 {
 742     ISADevice *s = opaque;
 743
 744     if (level) {
 745         rtc_set_memory(s, 0xF, 0xFE);
 746     }
 747 }
 748
 749 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 750 {
 751     CPUState *s = opaque;
 752
 753     if (level) {
 754         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 755     }
 756 }
 757
 758 static CPUState *pc_new_cpu(const char *cpu_model)
 759 {
 760     CPUState *env;
 761
 762     env = cpu_init(cpu_model);
 763     if (!env) {
 764         fprintf(stderr, "Unable to find x86 CPU definition\n");
 765         exit(1);
 766     }
 767     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 768         env->cpuid_apic_id = env->cpu_index;
 769         /* APIC reset callback resets cpu */
 770         apic_init(env);
 771     } else {
 772         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 773     }
 774     return env;
 775 }
 776
 777 void pc_cpus_init(const char *cpu_model)
 778 {
 779     int i;
 780
 781     /* init CPUs */
 782     if (cpu_model == NULL) {
 783 #ifdef TARGET_X86_64
 784         cpu_model = "qemu64";
 785 #else
 786         cpu_model = "qemu32";
 787 #endif
 788     }
 789
 790     for(i = 0; i < smp_cpus; i++) {
 791         pc_new_cpu(cpu_model);
 792     }
 793 }
 794
 795 void pc_memory_init(ram_addr_t ram_size,
 796                     const char *kernel_filename,
 797                     const char *kernel_cmdline,
 798                     const char *initrd_filename,
 799                     ram_addr_t *below_4g_mem_size_p,
 800                     ram_addr_t *above_4g_mem_size_p)
 801 {
 802     char *filename;
 803     int ret, linux_boot, i;
 804     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 805     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 806     int bios_size, isa_bios_size;
 807     void *fw_cfg;
 808
 809     if (ram_size >= 0xe0000000 ) {
 810         above_4g_mem_size = ram_size - 0xe0000000;
 811         below_4g_mem_size = 0xe0000000;
 812     } else {
 813         below_4g_mem_size = ram_size;
 814     }
 815     *above_4g_mem_size_p = above_4g_mem_size;
 816     *below_4g_mem_size_p = below_4g_mem_size;
 817
 818     linux_boot = (kernel_filename != NULL);
 819
 820     /* allocate RAM */
 821     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 822     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 823     cpu_register_physical_memory(0x100000,
 824                  below_4g_mem_size - 0x100000,
 825                  ram_addr + 0x100000);
 826
 827     /* above 4giga memory allocation */
 828     if (above_4g_mem_size > 0) {
 829 #if TARGET_PHYS_ADDR_BITS == 32
 830         hw_error("To much RAM for 32-bit physical address");
 831 #else
 832         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 833         cpu_register_physical_memory(0x100000000ULL,
 834                                      above_4g_mem_size,
 835                                      ram_addr);
 836 #endif
 837     }
 838
 839
 840     /* BIOS load */
 841     if (bios_name == NULL)
 842         bios_name = BIOS_FILENAME;
 843     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 844     if (filename) {
 845         bios_size = get_image_size(filename);
 846     } else {
 847         bios_size = -1;
 848     }
 849     if (bios_size <= 0 ||
 850         (bios_size % 65536) != 0) {
 851         goto bios_error;
 852     }
 853     bios_offset = qemu_ram_alloc(bios_size);
 854     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 855     if (ret != 0) {
 856     bios_error:
 857         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 858         exit(1);
 859     }
 860     if (filename) {
 861         qemu_free(filename);
 862     }
 863     /* map the last 128KB of the BIOS in ISA space */
 864     isa_bios_size = bios_size;
 865     if (isa_bios_size > (128 * 1024))
 866         isa_bios_size = 128 * 1024;
 867     cpu_register_physical_memory(0x100000 - isa_bios_size,
 868                                  isa_bios_size,
 869                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 870
 871     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 872     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 873
 874     /* map all the bios at the top of memory */
 875     cpu_register_physical_memory((uint32_t)(-bios_size),
 876                                  bios_size, bios_offset | IO_MEM_ROM);
 877
 878     fw_cfg = bochs_bios_init();
 879     rom_set_fw(fw_cfg);
 880
 881     if (linux_boot) {
 882         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 883     }
 884
 885     for (i = 0; i < nb_option_roms; i++) {
 886         rom_add_option(option_rom[i]);
 887     }
 888 }
 889
 890 qemu_irq *pc_allocate_cpu_irq(void)
 891 {
 892     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 893 }
 894
 895 void pc_vga_init(PCIBus *pci_bus)
 896 {
 897     if (cirrus_vga_enabled) {
 898         if (pci_bus) {
 899             pci_cirrus_vga_init(pci_bus);
 900         } else {
 901             isa_cirrus_vga_init();
 902         }
 903     } else if (vmsvga_enabled) {
 904         if (pci_bus)
 905             pci_vmsvga_init(pci_bus);
 906         else
 907             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 908     } else if (std_vga_enabled) {
 909         if (pci_bus) {
 910             pci_vga_init(pci_bus, 0, 0);
 911         } else {
 912             isa_vga_init();
 913         }
 914     }
 915 }
 916
 917 void pc_basic_device_init(qemu_irq *isa_irq,
 918                           FDCtrl **floppy_controller,
 919                           ISADevice **rtc_state)
 920 {
 921     int i;
 922     DriveInfo *fd[MAX_FD];
 923     PITState *pit;
 924     qemu_irq *a20_line;
 925     ISADevice *i8042;
 926
 927     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 928
 929     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 930
 931     *rtc_state = rtc_init(2000);
 932
 933     qemu_register_boot_set(pc_boot_set, *rtc_state);
 934
 935     pit = pit_init(0x40, isa_reserve_irq(0));
 936     pcspk_init(pit);
 937     if (!no_hpet) {
 938         hpet_init(isa_irq);
 939     }
 940
 941     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 942         if (serial_hds[i]) {
 943             serial_isa_init(i, serial_hds[i]);
 944         }
 945     }
 946
 947     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 948         if (parallel_hds[i]) {
 949             parallel_init(i, parallel_hds[i]);
 950         }
 951     }
 952
 953     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
 954     i8042 = isa_create_simple("i8042");
 955     i8042_setup_a20_line(i8042, a20_line);
 956     vmmouse_init(i8042);
 957
 958     DMA_init(0);
 959
 960     for(i = 0; i < MAX_FD; i++) {
 961         fd[i] = drive_get(IF_FLOPPY, 0, i);
 962     }
 963     *floppy_controller = fdctrl_init_isa(fd);
 964 }
 965
 966 void pc_pci_device_init(PCIBus *pci_bus)
 967 {
 968     int max_bus;
 969     int bus;
 970
 971     max_bus = drive_get_max_bus(IF_SCSI);
 972     for (bus = 0; bus <= max_bus; bus++) {
 973         pci_create_simple(pci_bus, -1, "lsi53c895a");
 974     }
 975 }