hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msix.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "blockdev.h"
  43 #include "ui/qemu-spice.h"
  44 #include "memory.h"
  45 #include "exec-memory.h"
  46
  47 /* output Bochs bios info messages */
  48 //#define DEBUG_BIOS
  49
  50 /* debug PC/ISA interrupts */
  51 //#define DEBUG_IRQ
  52
  53 #ifdef DEBUG_IRQ
  54 #define DPRINTF(fmt, ...)                                       \
  55     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  56 #else
  57 #define DPRINTF(fmt, ...)
  58 #endif
  59
  60 #define BIOS_FILENAME "bios.bin"
  61
  62 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  63
  64 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  65 #define ACPI_DATA_SIZE       0x10000
  66 #define BIOS_CFG_IOPORT 0x510
  67 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  68 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  69 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  70 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  71 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  72
  73 #define MSI_ADDR_BASE 0xfee00000
  74
  75 #define E820_NR_ENTRIES         16
  76
  77 struct e820_entry {
  78     uint64_t address;
  79     uint64_t length;
  80     uint32_t type;
  81 } QEMU_PACKED __attribute((__aligned__(4)));
  82
  83 struct e820_table {
  84     uint32_t count;
  85     struct e820_entry entry[E820_NR_ENTRIES];
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 static struct e820_table e820_table;
  89 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  90
  91 void isa_irq_handler(void *opaque, int n, int level)
  92 {
  93     IsaIrqState *isa = (IsaIrqState *)opaque;
  94
  95     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
  96     if (n < 16) {
  97         qemu_set_irq(isa->i8259[n], level);
  98     }
  99     if (isa->ioapic)
 100         qemu_set_irq(isa->ioapic[n], level);
 101 };
 102
 103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105 }
 106
 107 /* MSDOS compatibility mode FPU exception support */
 108 static qemu_irq ferr_irq;
 109
 110 void pc_register_ferr_irq(qemu_irq irq)
 111 {
 112     ferr_irq = irq;
 113 }
 114
 115 /* XXX: add IGNNE support */
 116 void cpu_set_ferr(CPUX86State *s)
 117 {
 118     qemu_irq_raise(ferr_irq);
 119 }
 120
 121 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 122 {
 123     qemu_irq_lower(ferr_irq);
 124 }
 125
 126 /* TSC handling */
 127 uint64_t cpu_get_tsc(CPUX86State *env)
 128 {
 129     return cpu_get_ticks();
 130 }
 131
 132 /* SMM support */
 133
 134 static cpu_set_smm_t smm_set;
 135 static void *smm_arg;
 136
 137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 138 {
 139     assert(smm_set == NULL);
 140     assert(smm_arg == NULL);
 141     smm_set = callback;
 142     smm_arg = arg;
 143 }
 144
 145 void cpu_smm_update(CPUState *env)
 146 {
 147     if (smm_set && smm_arg && env == first_cpu)
 148         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 149 }
 150
 151
 152 /* IRQ handling */
 153 int cpu_get_pic_interrupt(CPUState *env)
 154 {
 155     int intno;
 156
 157     intno = apic_get_interrupt(env->apic_state);
 158     if (intno >= 0) {
 159         /* set irq request if a PIC irq is still pending */
 160         /* XXX: improve that */
 161         pic_update_irq(isa_pic);
 162         return intno;
 163     }
 164     /* read the irq from the PIC */
 165     if (!apic_accept_pic_intr(env->apic_state)) {
 166         return -1;
 167     }
 168
 169     intno = pic_read_irq(isa_pic);
 170     return intno;
 171 }
 172
 173 static void pic_irq_request(void *opaque, int irq, int level)
 174 {
 175     CPUState *env = first_cpu;
 176
 177     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 178     if (env->apic_state) {
 179         while (env) {
 180             if (apic_accept_pic_intr(env->apic_state)) {
 181                 apic_deliver_pic_intr(env->apic_state, level);
 182             }
 183             env = env->next_cpu;
 184         }
 185     } else {
 186         if (level)
 187             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 188         else
 189             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 190     }
 191 }
 192
 193 /* PC cmos mappings */
 194
 195 #define REG_EQUIPMENT_BYTE          0x14
 196
 197 static int cmos_get_fd_drive_type(FDriveType fd0)
 198 {
 199     int val;
 200
 201     switch (fd0) {
 202     case FDRIVE_DRV_144:
 203         /* 1.44 Mb 3"5 drive */
 204         val = 4;
 205         break;
 206     case FDRIVE_DRV_288:
 207         /* 2.88 Mb 3"5 drive */
 208         val = 5;
 209         break;
 210     case FDRIVE_DRV_120:
 211         /* 1.2 Mb 5"5 drive */
 212         val = 2;
 213         break;
 214     case FDRIVE_DRV_NONE:
 215     default:
 216         val = 0;
 217         break;
 218     }
 219     return val;
 220 }
 221
 222 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 223                          ISADevice *s)
 224 {
 225     int cylinders, heads, sectors;
 226     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 227     rtc_set_memory(s, type_ofs, 47);
 228     rtc_set_memory(s, info_ofs, cylinders);
 229     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 230     rtc_set_memory(s, info_ofs + 2, heads);
 231     rtc_set_memory(s, info_ofs + 3, 0xff);
 232     rtc_set_memory(s, info_ofs + 4, 0xff);
 233     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 234     rtc_set_memory(s, info_ofs + 6, cylinders);
 235     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 236     rtc_set_memory(s, info_ofs + 8, sectors);
 237 }
 238
 239 /* convert boot_device letter to something recognizable by the bios */
 240 static int boot_device2nibble(char boot_device)
 241 {
 242     switch(boot_device) {
 243     case 'a':
 244     case 'b':
 245         return 0x01; /* floppy boot */
 246     case 'c':
 247         return 0x02; /* hard drive boot */
 248     case 'd':
 249         return 0x03; /* CD-ROM boot */
 250     case 'n':
 251         return 0x04; /* Network boot */
 252     }
 253     return 0;
 254 }
 255
 256 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 257 {
 258 #define PC_MAX_BOOT_DEVICES 3
 259     int nbds, bds[3] = { 0, };
 260     int i;
 261
 262     nbds = strlen(boot_device);
 263     if (nbds > PC_MAX_BOOT_DEVICES) {
 264         error_report("Too many boot devices for PC");
 265         return(1);
 266     }
 267     for (i = 0; i < nbds; i++) {
 268         bds[i] = boot_device2nibble(boot_device[i]);
 269         if (bds[i] == 0) {
 270             error_report("Invalid boot device for PC: '%c'",
 271                          boot_device[i]);
 272             return(1);
 273         }
 274     }
 275     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 276     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 277     return(0);
 278 }
 279
 280 static int pc_boot_set(void *opaque, const char *boot_device)
 281 {
 282     return set_boot_dev(opaque, boot_device, 0);
 283 }
 284
 285 typedef struct pc_cmos_init_late_arg {
 286     ISADevice *rtc_state;
 287     BusState *idebus0, *idebus1;
 288 } pc_cmos_init_late_arg;
 289
 290 static void pc_cmos_init_late(void *opaque)
 291 {
 292     pc_cmos_init_late_arg *arg = opaque;
 293     ISADevice *s = arg->rtc_state;
 294     int val;
 295     BlockDriverState *hd_table[4];
 296     int i;
 297
 298     ide_get_bs(hd_table, arg->idebus0);
 299     ide_get_bs(hd_table + 2, arg->idebus1);
 300
 301     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 302     if (hd_table[0])
 303         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 304     if (hd_table[1])
 305         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 306
 307     val = 0;
 308     for (i = 0; i < 4; i++) {
 309         if (hd_table[i]) {
 310             int cylinders, heads, sectors, translation;
 311             /* NOTE: bdrv_get_geometry_hint() returns the physical
 312                 geometry.  It is always such that: 1 <= sects <= 63, 1
 313                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 314                 geometry can be different if a translation is done. */
 315             translation = bdrv_get_translation_hint(hd_table[i]);
 316             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 317                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 318                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 319                     /* No translation. */
 320                     translation = 0;
 321                 } else {
 322                     /* LBA translation. */
 323                     translation = 1;
 324                 }
 325             } else {
 326                 translation--;
 327             }
 328             val |= translation << (i * 2);
 329         }
 330     }
 331     rtc_set_memory(s, 0x39, val);
 332
 333     qemu_unregister_reset(pc_cmos_init_late, opaque);
 334 }
 335
 336 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 337                   const char *boot_device,
 338                   BusState *idebus0, BusState *idebus1,
 339                   ISADevice *s)
 340 {
 341     int val, nb, nb_heads, max_track, last_sect, i;
 342     FDriveType fd_type[2];
 343     DriveInfo *fd[2];
 344     static pc_cmos_init_late_arg arg;
 345
 346     /* various important CMOS locations needed by PC/Bochs bios */
 347
 348     /* memory size */
 349     val = 640; /* base memory in K */
 350     rtc_set_memory(s, 0x15, val);
 351     rtc_set_memory(s, 0x16, val >> 8);
 352
 353     val = (ram_size / 1024) - 1024;
 354     if (val > 65535)
 355         val = 65535;
 356     rtc_set_memory(s, 0x17, val);
 357     rtc_set_memory(s, 0x18, val >> 8);
 358     rtc_set_memory(s, 0x30, val);
 359     rtc_set_memory(s, 0x31, val >> 8);
 360
 361     if (above_4g_mem_size) {
 362         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 363         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 364         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 365     }
 366
 367     if (ram_size > (16 * 1024 * 1024))
 368         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 369     else
 370         val = 0;
 371     if (val > 65535)
 372         val = 65535;
 373     rtc_set_memory(s, 0x34, val);
 374     rtc_set_memory(s, 0x35, val >> 8);
 375
 376     /* set the number of CPU */
 377     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 378
 379     /* set boot devices, and disable floppy signature check if requested */
 380     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 381         exit(1);
 382     }
 383
 384     /* floppy type */
 385     for (i = 0; i < 2; i++) {
 386         fd[i] = drive_get(IF_FLOPPY, 0, i);
 387         if (fd[i] && bdrv_is_inserted(fd[i]->bdrv)) {
 388             bdrv_get_floppy_geometry_hint(fd[i]->bdrv, &nb_heads, &max_track,
 389                                           &last_sect, FDRIVE_DRV_NONE,
 390                                           &fd_type[i]);
 391         } else {
 392             fd_type[i] = FDRIVE_DRV_NONE;
 393         }
 394     }
 395     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 396         cmos_get_fd_drive_type(fd_type[1]);
 397     rtc_set_memory(s, 0x10, val);
 398
 399     val = 0;
 400     nb = 0;
 401     if (fd_type[0] < FDRIVE_DRV_NONE) {
 402         nb++;
 403     }
 404     if (fd_type[1] < FDRIVE_DRV_NONE) {
 405         nb++;
 406     }
 407     switch (nb) {
 408     case 0:
 409         break;
 410     case 1:
 411         val |= 0x01; /* 1 drive, ready for boot */
 412         break;
 413     case 2:
 414         val |= 0x41; /* 2 drives, ready for boot */
 415         break;
 416     }
 417     val |= 0x02; /* FPU is there */
 418     val |= 0x04; /* PS/2 mouse installed */
 419     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 420
 421     /* hard drives */
 422     arg.rtc_state = s;
 423     arg.idebus0 = idebus0;
 424     arg.idebus1 = idebus1;
 425     qemu_register_reset(pc_cmos_init_late, &arg);
 426 }
 427
 428 /* port 92 stuff: could be split off */
 429 typedef struct Port92State {
 430     ISADevice dev;
 431     MemoryRegion io;
 432     uint8_t outport;
 433     qemu_irq *a20_out;
 434 } Port92State;
 435
 436 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 437 {
 438     Port92State *s = opaque;
 439
 440     DPRINTF("port92: write 0x%02x\n", val);
 441     s->outport = val;
 442     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 443     if (val & 1) {
 444         qemu_system_reset_request();
 445     }
 446 }
 447
 448 static uint32_t port92_read(void *opaque, uint32_t addr)
 449 {
 450     Port92State *s = opaque;
 451     uint32_t ret;
 452
 453     ret = s->outport;
 454     DPRINTF("port92: read 0x%02x\n", ret);
 455     return ret;
 456 }
 457
 458 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 459 {
 460     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 461
 462     s->a20_out = a20_out;
 463 }
 464
 465 static const VMStateDescription vmstate_port92_isa = {
 466     .name = "port92",
 467     .version_id = 1,
 468     .minimum_version_id = 1,
 469     .minimum_version_id_old = 1,
 470     .fields      = (VMStateField []) {
 471         VMSTATE_UINT8(outport, Port92State),
 472         VMSTATE_END_OF_LIST()
 473     }
 474 };
 475
 476 static void port92_reset(DeviceState *d)
 477 {
 478     Port92State *s = container_of(d, Port92State, dev.qdev);
 479
 480     s->outport &= ~1;
 481 }
 482
 483 static const MemoryRegionPortio port92_portio[] = {
 484     { 0, 1, 1, .read = port92_read, .write = port92_write },
 485     PORTIO_END_OF_LIST(),
 486 };
 487
 488 static const MemoryRegionOps port92_ops = {
 489     .old_portio = port92_portio
 490 };
 491
 492 static int port92_initfn(ISADevice *dev)
 493 {
 494     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 495
 496     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 497     isa_register_ioport(dev, &s->io, 0x92);
 498
 499     s->outport = 0;
 500     return 0;
 501 }
 502
 503 static ISADeviceInfo port92_info = {
 504     .qdev.name     = "port92",
 505     .qdev.size     = sizeof(Port92State),
 506     .qdev.vmsd     = &vmstate_port92_isa,
 507     .qdev.no_user  = 1,
 508     .qdev.reset    = port92_reset,
 509     .init          = port92_initfn,
 510 };
 511
 512 static void port92_register(void)
 513 {
 514     isa_qdev_register(&port92_info);
 515 }
 516 device_init(port92_register)
 517
 518 static void handle_a20_line_change(void *opaque, int irq, int level)
 519 {
 520     CPUState *cpu = opaque;
 521
 522     /* XXX: send to all CPUs ? */
 523     /* XXX: add logic to handle multiple A20 line sources */
 524     cpu_x86_set_a20(cpu, level);
 525 }
 526
 527 /***********************************************************/
 528 /* Bochs BIOS debug ports */
 529
 530 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 531 {
 532     static const char shutdown_str[8] = "Shutdown";
 533     static int shutdown_index = 0;
 534
 535     switch(addr) {
 536         /* Bochs BIOS messages */
 537     case 0x400:
 538     case 0x401:
 539         /* used to be panic, now unused */
 540         break;
 541     case 0x402:
 542     case 0x403:
 543 #ifdef DEBUG_BIOS
 544         fprintf(stderr, "%c", val);
 545 #endif
 546         break;
 547     case 0x8900:
 548         /* same as Bochs power off */
 549         if (val == shutdown_str[shutdown_index]) {
 550             shutdown_index++;
 551             if (shutdown_index == 8) {
 552                 shutdown_index = 0;
 553                 qemu_system_shutdown_request();
 554             }
 555         } else {
 556             shutdown_index = 0;
 557         }
 558         break;
 559
 560         /* LGPL'ed VGA BIOS messages */
 561     case 0x501:
 562     case 0x502:
 563         exit((val << 1) | 1);
 564     case 0x500:
 565     case 0x503:
 566 #ifdef DEBUG_BIOS
 567         fprintf(stderr, "%c", val);
 568 #endif
 569         break;
 570     }
 571 }
 572
 573 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 574 {
 575     int index = le32_to_cpu(e820_table.count);
 576     struct e820_entry *entry;
 577
 578     if (index >= E820_NR_ENTRIES)
 579         return -EBUSY;
 580     entry = &e820_table.entry[index++];
 581
 582     entry->address = cpu_to_le64(address);
 583     entry->length = cpu_to_le64(length);
 584     entry->type = cpu_to_le32(type);
 585
 586     e820_table.count = cpu_to_le32(index);
 587     return index;
 588 }
 589
 590 static void *bochs_bios_init(void)
 591 {
 592     void *fw_cfg;
 593     uint8_t *smbios_table;
 594     size_t smbios_len;
 595     uint64_t *numa_fw_cfg;
 596     int i, j;
 597
 598     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 599     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 600     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 601     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 602     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 603
 604     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 605     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 606     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 607     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 608     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 609
 610     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 611
 612     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 613     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 614     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 615                      acpi_tables_len);
 616     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 617
 618     smbios_table = smbios_get_table(&smbios_len);
 619     if (smbios_table)
 620         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 621                          smbios_table, smbios_len);
 622     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 623                      sizeof(struct e820_table));
 624
 625     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 626                      sizeof(struct hpet_fw_config));
 627     /* allocate memory for the NUMA channel: one (64bit) word for the number
 628      * of nodes, one word for each VCPU->node and one word for each node to
 629      * hold the amount of memory.
 630      */
 631     numa_fw_cfg = g_malloc0((1 + smp_cpus + nb_numa_nodes) * 8);
 632     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 633     for (i = 0; i < smp_cpus; i++) {
 634         for (j = 0; j < nb_numa_nodes; j++) {
 635             if (node_cpumask[j] & (1 << i)) {
 636                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 637                 break;
 638             }
 639         }
 640     }
 641     for (i = 0; i < nb_numa_nodes; i++) {
 642         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 643     }
 644     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 645                      (1 + smp_cpus + nb_numa_nodes) * 8);
 646
 647     return fw_cfg;
 648 }
 649
 650 static long get_file_size(FILE *f)
 651 {
 652     long where, size;
 653
 654     /* XXX: on Unix systems, using fstat() probably makes more sense */
 655
 656     where = ftell(f);
 657     fseek(f, 0, SEEK_END);
 658     size = ftell(f);
 659     fseek(f, where, SEEK_SET);
 660
 661     return size;
 662 }
 663
 664 static void load_linux(void *fw_cfg,
 665                        const char *kernel_filename,
 666                        const char *initrd_filename,
 667                        const char *kernel_cmdline,
 668                        target_phys_addr_t max_ram_size)
 669 {
 670     uint16_t protocol;
 671     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 672     uint32_t initrd_max;
 673     uint8_t header[8192], *setup, *kernel, *initrd_data;
 674     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 675     FILE *f;
 676     char *vmode;
 677
 678     /* Align to 16 bytes as a paranoia measure */
 679     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 680
 681     /* load the kernel header */
 682     f = fopen(kernel_filename, "rb");
 683     if (!f || !(kernel_size = get_file_size(f)) ||
 684         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 685         MIN(ARRAY_SIZE(header), kernel_size)) {
 686         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 687                 kernel_filename, strerror(errno));
 688         exit(1);
 689     }
 690
 691     /* kernel protocol version */
 692 #if 0
 693     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 694 #endif
 695     if (ldl_p(header+0x202) == 0x53726448)
 696         protocol = lduw_p(header+0x206);
 697     else {
 698         /* This looks like a multiboot kernel. If it is, let's stop
 699            treating it like a Linux kernel. */
 700         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 701                            kernel_cmdline, kernel_size, header))
 702             return;
 703         protocol = 0;
 704     }
 705
 706     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 707         /* Low kernel */
 708         real_addr    = 0x90000;
 709         cmdline_addr = 0x9a000 - cmdline_size;
 710         prot_addr    = 0x10000;
 711     } else if (protocol < 0x202) {
 712         /* High but ancient kernel */
 713         real_addr    = 0x90000;
 714         cmdline_addr = 0x9a000 - cmdline_size;
 715         prot_addr    = 0x100000;
 716     } else {
 717         /* High and recent kernel */
 718         real_addr    = 0x10000;
 719         cmdline_addr = 0x20000;
 720         prot_addr    = 0x100000;
 721     }
 722
 723 #if 0
 724     fprintf(stderr,
 725             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 726             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 727             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 728             real_addr,
 729             cmdline_addr,
 730             prot_addr);
 731 #endif
 732
 733     /* highest address for loading the initrd */
 734     if (protocol >= 0x203)
 735         initrd_max = ldl_p(header+0x22c);
 736     else
 737         initrd_max = 0x37ffffff;
 738
 739     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 740         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 741
 742     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 743     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 744     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 745                      (uint8_t*)strdup(kernel_cmdline),
 746                      strlen(kernel_cmdline)+1);
 747
 748     if (protocol >= 0x202) {
 749         stl_p(header+0x228, cmdline_addr);
 750     } else {
 751         stw_p(header+0x20, 0xA33F);
 752         stw_p(header+0x22, cmdline_addr-real_addr);
 753     }
 754
 755     /* handle vga= parameter */
 756     vmode = strstr(kernel_cmdline, "vga=");
 757     if (vmode) {
 758         unsigned int video_mode;
 759         /* skip "vga=" */
 760         vmode += 4;
 761         if (!strncmp(vmode, "normal", 6)) {
 762             video_mode = 0xffff;
 763         } else if (!strncmp(vmode, "ext", 3)) {
 764             video_mode = 0xfffe;
 765         } else if (!strncmp(vmode, "ask", 3)) {
 766             video_mode = 0xfffd;
 767         } else {
 768             video_mode = strtol(vmode, NULL, 0);
 769         }
 770         stw_p(header+0x1fa, video_mode);
 771     }
 772
 773     /* loader type */
 774     /* High nybble = B reserved for Qemu; low nybble is revision number.
 775        If this code is substantially changed, you may want to consider
 776        incrementing the revision. */
 777     if (protocol >= 0x200)
 778         header[0x210] = 0xB0;
 779
 780     /* heap */
 781     if (protocol >= 0x201) {
 782         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 783         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 784     }
 785
 786     /* load initrd */
 787     if (initrd_filename) {
 788         if (protocol < 0x200) {
 789             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 790             exit(1);
 791         }
 792
 793         initrd_size = get_image_size(initrd_filename);
 794         if (initrd_size < 0) {
 795             fprintf(stderr, "qemu: error reading initrd %s\n",
 796                     initrd_filename);
 797             exit(1);
 798         }
 799
 800         initrd_addr = (initrd_max-initrd_size) & ~4095;
 801
 802         initrd_data = g_malloc(initrd_size);
 803         load_image(initrd_filename, initrd_data);
 804
 805         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 806         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 807         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 808
 809         stl_p(header+0x218, initrd_addr);
 810         stl_p(header+0x21c, initrd_size);
 811     }
 812
 813     /* load kernel and setup */
 814     setup_size = header[0x1f1];
 815     if (setup_size == 0)
 816         setup_size = 4;
 817     setup_size = (setup_size+1)*512;
 818     kernel_size -= setup_size;
 819
 820     setup  = g_malloc(setup_size);
 821     kernel = g_malloc(kernel_size);
 822     fseek(f, 0, SEEK_SET);
 823     if (fread(setup, 1, setup_size, f) != setup_size) {
 824         fprintf(stderr, "fread() failed\n");
 825         exit(1);
 826     }
 827     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 828         fprintf(stderr, "fread() failed\n");
 829         exit(1);
 830     }
 831     fclose(f);
 832     memcpy(setup, header, MIN(sizeof(header), setup_size));
 833
 834     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 835     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 836     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 837
 838     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 839     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 840     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 841
 842     option_rom[nb_option_roms].name = "linuxboot.bin";
 843     option_rom[nb_option_roms].bootindex = 0;
 844     nb_option_roms++;
 845 }
 846
 847 #define NE2000_NB_MAX 6
 848
 849 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 850                                               0x280, 0x380 };
 851 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 852
 853 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 854 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 855
 856 void pc_init_ne2k_isa(NICInfo *nd)
 857 {
 858     static int nb_ne2k = 0;
 859
 860     if (nb_ne2k == NE2000_NB_MAX)
 861         return;
 862     isa_ne2000_init(ne2000_io[nb_ne2k],
 863                     ne2000_irq[nb_ne2k], nd);
 864     nb_ne2k++;
 865 }
 866
 867 int cpu_is_bsp(CPUState *env)
 868 {
 869     /* We hard-wire the BSP to the first CPU. */
 870     return env->cpu_index == 0;
 871 }
 872
 873 DeviceState *cpu_get_current_apic(void)
 874 {
 875     if (cpu_single_env) {
 876         return cpu_single_env->apic_state;
 877     } else {
 878         return NULL;
 879     }
 880 }
 881
 882 static DeviceState *apic_init(void *env, uint8_t apic_id)
 883 {
 884     DeviceState *dev;
 885     SysBusDevice *d;
 886     static int apic_mapped;
 887
 888     dev = qdev_create(NULL, "apic");
 889     qdev_prop_set_uint8(dev, "id", apic_id);
 890     qdev_prop_set_ptr(dev, "cpu_env", env);
 891     qdev_init_nofail(dev);
 892     d = sysbus_from_qdev(dev);
 893
 894     /* XXX: mapping more APICs at the same memory location */
 895     if (apic_mapped == 0) {
 896         /* NOTE: the APIC is directly connected to the CPU - it is not
 897            on the global memory bus. */
 898         /* XXX: what if the base changes? */
 899         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
 900         apic_mapped = 1;
 901     }
 902
 903     msix_supported = 1;
 904
 905     return dev;
 906 }
 907
 908 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 909    BIOS will read it and start S3 resume at POST Entry */
 910 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 911 {
 912     ISADevice *s = opaque;
 913
 914     if (level) {
 915         rtc_set_memory(s, 0xF, 0xFE);
 916     }
 917 }
 918
 919 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 920 {
 921     CPUState *s = opaque;
 922
 923     if (level) {
 924         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 925     }
 926 }
 927
 928 static void pc_cpu_reset(void *opaque)
 929 {
 930     CPUState *env = opaque;
 931
 932     cpu_reset(env);
 933     env->halted = !cpu_is_bsp(env);
 934 }
 935
 936 static CPUState *pc_new_cpu(const char *cpu_model)
 937 {
 938     CPUState *env;
 939
 940     env = cpu_init(cpu_model);
 941     if (!env) {
 942         fprintf(stderr, "Unable to find x86 CPU definition\n");
 943         exit(1);
 944     }
 945     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 946         env->cpuid_apic_id = env->cpu_index;
 947         env->apic_state = apic_init(env, env->cpuid_apic_id);
 948     }
 949     qemu_register_reset(pc_cpu_reset, env);
 950     pc_cpu_reset(env);
 951     return env;
 952 }
 953
 954 void pc_cpus_init(const char *cpu_model)
 955 {
 956     int i;
 957
 958     /* init CPUs */
 959     if (cpu_model == NULL) {
 960 #ifdef TARGET_X86_64
 961         cpu_model = "qemu64";
 962 #else
 963         cpu_model = "qemu32";
 964 #endif
 965     }
 966
 967     for(i = 0; i < smp_cpus; i++) {
 968         pc_new_cpu(cpu_model);
 969     }
 970 }
 971
 972 void pc_memory_init(MemoryRegion *system_memory,
 973                     const char *kernel_filename,
 974                     const char *kernel_cmdline,
 975                     const char *initrd_filename,
 976                     ram_addr_t below_4g_mem_size,
 977                     ram_addr_t above_4g_mem_size,
 978                     MemoryRegion *rom_memory,
 979                     MemoryRegion **ram_memory)
 980 {
 981     char *filename;
 982     int ret, linux_boot, i;
 983     MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
 984     MemoryRegion *ram_below_4g, *ram_above_4g;
 985     int bios_size, isa_bios_size;
 986     void *fw_cfg;
 987
 988     linux_boot = (kernel_filename != NULL);
 989
 990     /* Allocate RAM.  We allocate it as a single memory region and use
 991      * aliases to address portions of it, mostly for backwards compatiblity
 992      * with older qemus that used qemu_ram_alloc().
 993      */
 994     ram = g_malloc(sizeof(*ram));
 995     memory_region_init_ram(ram, NULL, "pc.ram",
 996                            below_4g_mem_size + above_4g_mem_size);
 997     *ram_memory = ram;
 998     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 999     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1000                              0, below_4g_mem_size);
1001     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1002     if (above_4g_mem_size > 0) {
1003         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1004         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1005                                  below_4g_mem_size, above_4g_mem_size);
1006         memory_region_add_subregion(system_memory, 0x100000000ULL,
1007                                     ram_above_4g);
1008     }
1009
1010     /* BIOS load */
1011     if (bios_name == NULL)
1012         bios_name = BIOS_FILENAME;
1013     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1014     if (filename) {
1015         bios_size = get_image_size(filename);
1016     } else {
1017         bios_size = -1;
1018     }
1019     if (bios_size <= 0 ||
1020         (bios_size % 65536) != 0) {
1021         goto bios_error;
1022     }
1023     bios = g_malloc(sizeof(*bios));
1024     memory_region_init_ram(bios, NULL, "pc.bios", bios_size);
1025     memory_region_set_readonly(bios, true);
1026     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1027     if (ret != 0) {
1028     bios_error:
1029         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1030         exit(1);
1031     }
1032     if (filename) {
1033         g_free(filename);
1034     }
1035     /* map the last 128KB of the BIOS in ISA space */
1036     isa_bios_size = bios_size;
1037     if (isa_bios_size > (128 * 1024))
1038         isa_bios_size = 128 * 1024;
1039     isa_bios = g_malloc(sizeof(*isa_bios));
1040     memory_region_init_alias(isa_bios, "isa-bios", bios,
1041                              bios_size - isa_bios_size, isa_bios_size);
1042     memory_region_add_subregion_overlap(rom_memory,
1043                                         0x100000 - isa_bios_size,
1044                                         isa_bios,
1045                                         1);
1046     memory_region_set_readonly(isa_bios, true);
1047
1048     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1049     memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE);
1050     memory_region_add_subregion_overlap(rom_memory,
1051                                         PC_ROM_MIN_VGA,
1052                                         option_rom_mr,
1053                                         1);
1054
1055     /* map all the bios at the top of memory */
1056     memory_region_add_subregion(rom_memory,
1057                                 (uint32_t)(-bios_size),
1058                                 bios);
1059
1060     fw_cfg = bochs_bios_init();
1061     rom_set_fw(fw_cfg);
1062
1063     if (linux_boot) {
1064         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1065     }
1066
1067     for (i = 0; i < nb_option_roms; i++) {
1068         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1069     }
1070 }
1071
1072 qemu_irq *pc_allocate_cpu_irq(void)
1073 {
1074     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1075 }
1076
1077 void pc_vga_init(PCIBus *pci_bus)
1078 {
1079     if (cirrus_vga_enabled) {
1080         if (pci_bus) {
1081             pci_cirrus_vga_init(pci_bus);
1082         } else {
1083             isa_cirrus_vga_init(get_system_memory());
1084         }
1085     } else if (vmsvga_enabled) {
1086         if (pci_bus) {
1087             if (!pci_vmsvga_init(pci_bus)) {
1088                 fprintf(stderr, "Warning: vmware_vga not available,"
1089                         " using standard VGA instead\n");
1090                 pci_vga_init(pci_bus);
1091             }
1092         } else {
1093             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1094         }
1095 #ifdef CONFIG_SPICE
1096     } else if (qxl_enabled) {
1097         if (pci_bus)
1098             pci_create_simple(pci_bus, -1, "qxl-vga");
1099         else
1100             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1101 #endif
1102     } else if (std_vga_enabled) {
1103         if (pci_bus) {
1104             pci_vga_init(pci_bus);
1105         } else {
1106             isa_vga_init();
1107         }
1108     }
1109
1110     /*
1111      * sga does not suppress normal vga output. So a machine can have both a
1112      * vga card and sga manually enabled. Output will be seen on both.
1113      * For nographic case, sga is enabled at all times
1114      */
1115     if (display_type == DT_NOGRAPHIC) {
1116         isa_create_simple("sga");
1117     }
1118 }
1119
1120 static void cpu_request_exit(void *opaque, int irq, int level)
1121 {
1122     CPUState *env = cpu_single_env;
1123
1124     if (env && level) {
1125         cpu_exit(env);
1126     }
1127 }
1128
1129 void pc_basic_device_init(qemu_irq *isa_irq,
1130                           ISADevice **rtc_state,
1131                           bool no_vmport)
1132 {
1133     int i;
1134     DriveInfo *fd[MAX_FD];
1135     qemu_irq rtc_irq = NULL;
1136     qemu_irq *a20_line;
1137     ISADevice *i8042, *port92, *vmmouse, *pit;
1138     qemu_irq *cpu_exit_irq;
1139
1140     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1141
1142     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1143
1144     if (!no_hpet) {
1145         DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1146
1147         if (hpet) {
1148             for (i = 0; i < 24; i++) {
1149                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
1150             }
1151             rtc_irq = qdev_get_gpio_in(hpet, 0);
1152         }
1153     }
1154     *rtc_state = rtc_init(2000, rtc_irq);
1155
1156     qemu_register_boot_set(pc_boot_set, *rtc_state);
1157
1158     pit = pit_init(0x40, 0);
1159     pcspk_init(pit);
1160
1161     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1162         if (serial_hds[i]) {
1163             serial_isa_init(i, serial_hds[i]);
1164         }
1165     }
1166
1167     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1168         if (parallel_hds[i]) {
1169             parallel_init(i, parallel_hds[i]);
1170         }
1171     }
1172
1173     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1174     i8042 = isa_create_simple("i8042");
1175     i8042_setup_a20_line(i8042, &a20_line[0]);
1176     if (!no_vmport) {
1177         vmport_init();
1178         vmmouse = isa_try_create("vmmouse");
1179     } else {
1180         vmmouse = NULL;
1181     }
1182     if (vmmouse) {
1183         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1184         qdev_init_nofail(&vmmouse->qdev);
1185     }
1186     port92 = isa_create_simple("port92");
1187     port92_init(port92, &a20_line[1]);
1188
1189     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1190     DMA_init(0, cpu_exit_irq);
1191
1192     for(i = 0; i < MAX_FD; i++) {
1193         fd[i] = drive_get(IF_FLOPPY, 0, i);
1194     }
1195     fdctrl_init_isa(fd);
1196 }
1197
1198 void pc_pci_device_init(PCIBus *pci_bus)
1199 {
1200     int max_bus;
1201     int bus;
1202
1203     max_bus = drive_get_max_bus(IF_SCSI);
1204     for (bus = 0; bus <= max_bus; bus++) {
1205         pci_create_simple(pci_bus, -1, "lsi53c895a");
1206     }
1207 }