2 * QEMU PC System Emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "vmware_vga.h"
33 #include "hpet_emul.h"
37 #include "multiboot.h"
38 #include "mc146818rtc.h"
43 #include "ui/qemu-spice.h"
45 /* output Bochs bios info messages */
48 /* debug PC/ISA interrupts */
52 #define DPRINTF(fmt, ...) \
53 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
55 #define DPRINTF(fmt, ...)
58 #define BIOS_FILENAME "bios.bin"
60 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
62 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
63 #define ACPI_DATA_SIZE 0x10000
64 #define BIOS_CFG_IOPORT 0x510
65 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
66 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
67 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
68 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
69 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
71 #define MSI_ADDR_BASE 0xfee00000
73 #define E820_NR_ENTRIES 16
79 } __attribute((__packed__
, __aligned__(4)));
83 struct e820_entry entry
[E820_NR_ENTRIES
];
84 } __attribute((__packed__
, __aligned__(4)));
86 static struct e820_table e820_table
;
87 struct hpet_fw_config hpet_cfg
= {.count
= UINT8_MAX
};
89 void isa_irq_handler(void *opaque
, int n
, int level
)
91 IsaIrqState
*isa
= (IsaIrqState
*)opaque
;
93 DPRINTF("isa_irqs: %s irq %d\n", level
? "raise" : "lower", n
);
95 qemu_set_irq(isa
->i8259
[n
], level
);
98 qemu_set_irq(isa
->ioapic
[n
], level
);
101 static void ioport80_write(void *opaque
, uint32_t addr
, uint32_t data
)
105 /* MSDOS compatibility mode FPU exception support */
106 static qemu_irq ferr_irq
;
108 void pc_register_ferr_irq(qemu_irq irq
)
113 /* XXX: add IGNNE support */
114 void cpu_set_ferr(CPUX86State
*s
)
116 qemu_irq_raise(ferr_irq
);
119 static void ioportF0_write(void *opaque
, uint32_t addr
, uint32_t data
)
121 qemu_irq_lower(ferr_irq
);
125 uint64_t cpu_get_tsc(CPUX86State
*env
)
127 return cpu_get_ticks();
132 static cpu_set_smm_t smm_set
;
133 static void *smm_arg
;
135 void cpu_smm_register(cpu_set_smm_t callback
, void *arg
)
137 assert(smm_set
== NULL
);
138 assert(smm_arg
== NULL
);
143 void cpu_smm_update(CPUState
*env
)
145 if (smm_set
&& smm_arg
&& env
== first_cpu
)
146 smm_set(!!(env
->hflags
& HF_SMM_MASK
), smm_arg
);
151 int cpu_get_pic_interrupt(CPUState
*env
)
155 intno
= apic_get_interrupt(env
->apic_state
);
157 /* set irq request if a PIC irq is still pending */
158 /* XXX: improve that */
159 pic_update_irq(isa_pic
);
162 /* read the irq from the PIC */
163 if (!apic_accept_pic_intr(env
->apic_state
)) {
167 intno
= pic_read_irq(isa_pic
);
171 static void pic_irq_request(void *opaque
, int irq
, int level
)
173 CPUState
*env
= first_cpu
;
175 DPRINTF("pic_irqs: %s irq %d\n", level
? "raise" : "lower", irq
);
176 if (env
->apic_state
) {
178 if (apic_accept_pic_intr(env
->apic_state
)) {
179 apic_deliver_pic_intr(env
->apic_state
, level
);
185 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
187 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
191 /* PC cmos mappings */
193 #define REG_EQUIPMENT_BYTE 0x14
195 static int cmos_get_fd_drive_type(int fd0
)
201 /* 1.44 Mb 3"5 drive */
205 /* 2.88 Mb 3"5 drive */
209 /* 1.2 Mb 5"5 drive */
219 static void cmos_init_hd(int type_ofs
, int info_ofs
, BlockDriverState
*hd
,
222 int cylinders
, heads
, sectors
;
223 bdrv_get_geometry_hint(hd
, &cylinders
, &heads
, §ors
);
224 rtc_set_memory(s
, type_ofs
, 47);
225 rtc_set_memory(s
, info_ofs
, cylinders
);
226 rtc_set_memory(s
, info_ofs
+ 1, cylinders
>> 8);
227 rtc_set_memory(s
, info_ofs
+ 2, heads
);
228 rtc_set_memory(s
, info_ofs
+ 3, 0xff);
229 rtc_set_memory(s
, info_ofs
+ 4, 0xff);
230 rtc_set_memory(s
, info_ofs
+ 5, 0xc0 | ((heads
> 8) << 3));
231 rtc_set_memory(s
, info_ofs
+ 6, cylinders
);
232 rtc_set_memory(s
, info_ofs
+ 7, cylinders
>> 8);
233 rtc_set_memory(s
, info_ofs
+ 8, sectors
);
236 /* convert boot_device letter to something recognizable by the bios */
237 static int boot_device2nibble(char boot_device
)
239 switch(boot_device
) {
242 return 0x01; /* floppy boot */
244 return 0x02; /* hard drive boot */
246 return 0x03; /* CD-ROM boot */
248 return 0x04; /* Network boot */
253 static int set_boot_dev(ISADevice
*s
, const char *boot_device
, int fd_bootchk
)
255 #define PC_MAX_BOOT_DEVICES 3
256 int nbds
, bds
[3] = { 0, };
259 nbds
= strlen(boot_device
);
260 if (nbds
> PC_MAX_BOOT_DEVICES
) {
261 error_report("Too many boot devices for PC");
264 for (i
= 0; i
< nbds
; i
++) {
265 bds
[i
] = boot_device2nibble(boot_device
[i
]);
267 error_report("Invalid boot device for PC: '%c'",
272 rtc_set_memory(s
, 0x3d, (bds
[1] << 4) | bds
[0]);
273 rtc_set_memory(s
, 0x38, (bds
[2] << 4) | (fd_bootchk
? 0x0 : 0x1));
277 static int pc_boot_set(void *opaque
, const char *boot_device
)
279 return set_boot_dev(opaque
, boot_device
, 0);
282 typedef struct pc_cmos_init_late_arg
{
283 ISADevice
*rtc_state
;
284 BusState
*idebus0
, *idebus1
;
285 } pc_cmos_init_late_arg
;
287 static void pc_cmos_init_late(void *opaque
)
289 pc_cmos_init_late_arg
*arg
= opaque
;
290 ISADevice
*s
= arg
->rtc_state
;
292 BlockDriverState
*hd_table
[4];
295 ide_get_bs(hd_table
, arg
->idebus0
);
296 ide_get_bs(hd_table
+ 2, arg
->idebus1
);
298 rtc_set_memory(s
, 0x12, (hd_table
[0] ? 0xf0 : 0) | (hd_table
[1] ? 0x0f : 0));
300 cmos_init_hd(0x19, 0x1b, hd_table
[0], s
);
302 cmos_init_hd(0x1a, 0x24, hd_table
[1], s
);
305 for (i
= 0; i
< 4; i
++) {
307 int cylinders
, heads
, sectors
, translation
;
308 /* NOTE: bdrv_get_geometry_hint() returns the physical
309 geometry. It is always such that: 1 <= sects <= 63, 1
310 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
311 geometry can be different if a translation is done. */
312 translation
= bdrv_get_translation_hint(hd_table
[i
]);
313 if (translation
== BIOS_ATA_TRANSLATION_AUTO
) {
314 bdrv_get_geometry_hint(hd_table
[i
], &cylinders
, &heads
, §ors
);
315 if (cylinders
<= 1024 && heads
<= 16 && sectors
<= 63) {
316 /* No translation. */
319 /* LBA translation. */
325 val
|= translation
<< (i
* 2);
328 rtc_set_memory(s
, 0x39, val
);
330 qemu_unregister_reset(pc_cmos_init_late
, opaque
);
333 void pc_cmos_init(ram_addr_t ram_size
, ram_addr_t above_4g_mem_size
,
334 const char *boot_device
,
335 BusState
*idebus0
, BusState
*idebus1
,
336 FDCtrl
*floppy_controller
, ISADevice
*s
)
340 static pc_cmos_init_late_arg arg
;
342 /* various important CMOS locations needed by PC/Bochs bios */
345 val
= 640; /* base memory in K */
346 rtc_set_memory(s
, 0x15, val
);
347 rtc_set_memory(s
, 0x16, val
>> 8);
349 val
= (ram_size
/ 1024) - 1024;
352 rtc_set_memory(s
, 0x17, val
);
353 rtc_set_memory(s
, 0x18, val
>> 8);
354 rtc_set_memory(s
, 0x30, val
);
355 rtc_set_memory(s
, 0x31, val
>> 8);
357 if (above_4g_mem_size
) {
358 rtc_set_memory(s
, 0x5b, (unsigned int)above_4g_mem_size
>> 16);
359 rtc_set_memory(s
, 0x5c, (unsigned int)above_4g_mem_size
>> 24);
360 rtc_set_memory(s
, 0x5d, (uint64_t)above_4g_mem_size
>> 32);
363 if (ram_size
> (16 * 1024 * 1024))
364 val
= (ram_size
/ 65536) - ((16 * 1024 * 1024) / 65536);
369 rtc_set_memory(s
, 0x34, val
);
370 rtc_set_memory(s
, 0x35, val
>> 8);
372 /* set the number of CPU */
373 rtc_set_memory(s
, 0x5f, smp_cpus
- 1);
375 /* set boot devices, and disable floppy signature check if requested */
376 if (set_boot_dev(s
, boot_device
, fd_bootchk
)) {
382 fd0
= fdctrl_get_drive_type(floppy_controller
, 0);
383 fd1
= fdctrl_get_drive_type(floppy_controller
, 1);
385 val
= (cmos_get_fd_drive_type(fd0
) << 4) | cmos_get_fd_drive_type(fd1
);
386 rtc_set_memory(s
, 0x10, val
);
398 val
|= 0x01; /* 1 drive, ready for boot */
401 val
|= 0x41; /* 2 drives, ready for boot */
404 val
|= 0x02; /* FPU is there */
405 val
|= 0x04; /* PS/2 mouse installed */
406 rtc_set_memory(s
, REG_EQUIPMENT_BYTE
, val
);
410 arg
.idebus0
= idebus0
;
411 arg
.idebus1
= idebus1
;
412 qemu_register_reset(pc_cmos_init_late
, &arg
);
415 /* port 92 stuff: could be split off */
416 typedef struct Port92State
{
422 static void port92_write(void *opaque
, uint32_t addr
, uint32_t val
)
424 Port92State
*s
= opaque
;
426 DPRINTF("port92: write 0x%02x\n", val
);
428 qemu_set_irq(*s
->a20_out
, (val
>> 1) & 1);
430 qemu_system_reset_request();
434 static uint32_t port92_read(void *opaque
, uint32_t addr
)
436 Port92State
*s
= opaque
;
440 DPRINTF("port92: read 0x%02x\n", ret
);
444 static void port92_init(ISADevice
*dev
, qemu_irq
*a20_out
)
446 Port92State
*s
= DO_UPCAST(Port92State
, dev
, dev
);
448 s
->a20_out
= a20_out
;
451 static const VMStateDescription vmstate_port92_isa
= {
454 .minimum_version_id
= 1,
455 .minimum_version_id_old
= 1,
456 .fields
= (VMStateField
[]) {
457 VMSTATE_UINT8(outport
, Port92State
),
458 VMSTATE_END_OF_LIST()
462 static void port92_reset(DeviceState
*d
)
464 Port92State
*s
= container_of(d
, Port92State
, dev
.qdev
);
469 static int port92_initfn(ISADevice
*dev
)
471 Port92State
*s
= DO_UPCAST(Port92State
, dev
, dev
);
473 register_ioport_read(0x92, 1, 1, port92_read
, s
);
474 register_ioport_write(0x92, 1, 1, port92_write
, s
);
475 isa_init_ioport(dev
, 0x92);
480 static ISADeviceInfo port92_info
= {
481 .qdev
.name
= "port92",
482 .qdev
.size
= sizeof(Port92State
),
483 .qdev
.vmsd
= &vmstate_port92_isa
,
485 .qdev
.reset
= port92_reset
,
486 .init
= port92_initfn
,
489 static void port92_register(void)
491 isa_qdev_register(&port92_info
);
493 device_init(port92_register
)
495 static void handle_a20_line_change(void *opaque
, int irq
, int level
)
497 CPUState
*cpu
= opaque
;
499 /* XXX: send to all CPUs ? */
500 /* XXX: add logic to handle multiple A20 line sources */
501 cpu_x86_set_a20(cpu
, level
);
504 /***********************************************************/
505 /* Bochs BIOS debug ports */
507 static void bochs_bios_write(void *opaque
, uint32_t addr
, uint32_t val
)
509 static const char shutdown_str
[8] = "Shutdown";
510 static int shutdown_index
= 0;
513 /* Bochs BIOS messages */
516 /* used to be panic, now unused */
521 fprintf(stderr
, "%c", val
);
525 /* same as Bochs power off */
526 if (val
== shutdown_str
[shutdown_index
]) {
528 if (shutdown_index
== 8) {
530 qemu_system_shutdown_request();
537 /* LGPL'ed VGA BIOS messages */
540 fprintf(stderr
, "VGA BIOS panic, line %d\n", val
);
545 fprintf(stderr
, "%c", val
);
551 int e820_add_entry(uint64_t address
, uint64_t length
, uint32_t type
)
553 int index
= le32_to_cpu(e820_table
.count
);
554 struct e820_entry
*entry
;
556 if (index
>= E820_NR_ENTRIES
)
558 entry
= &e820_table
.entry
[index
++];
560 entry
->address
= cpu_to_le64(address
);
561 entry
->length
= cpu_to_le64(length
);
562 entry
->type
= cpu_to_le32(type
);
564 e820_table
.count
= cpu_to_le32(index
);
568 static void *bochs_bios_init(void)
571 uint8_t *smbios_table
;
573 uint64_t *numa_fw_cfg
;
576 register_ioport_write(0x400, 1, 2, bochs_bios_write
, NULL
);
577 register_ioport_write(0x401, 1, 2, bochs_bios_write
, NULL
);
578 register_ioport_write(0x402, 1, 1, bochs_bios_write
, NULL
);
579 register_ioport_write(0x403, 1, 1, bochs_bios_write
, NULL
);
580 register_ioport_write(0x8900, 1, 1, bochs_bios_write
, NULL
);
582 register_ioport_write(0x501, 1, 2, bochs_bios_write
, NULL
);
583 register_ioport_write(0x502, 1, 2, bochs_bios_write
, NULL
);
584 register_ioport_write(0x500, 1, 1, bochs_bios_write
, NULL
);
585 register_ioport_write(0x503, 1, 1, bochs_bios_write
, NULL
);
587 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
589 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
590 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
591 fw_cfg_add_bytes(fw_cfg
, FW_CFG_ACPI_TABLES
, (uint8_t *)acpi_tables
,
593 fw_cfg_add_bytes(fw_cfg
, FW_CFG_IRQ0_OVERRIDE
, &irq0override
, 1);
595 smbios_table
= smbios_get_table(&smbios_len
);
597 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SMBIOS_ENTRIES
,
598 smbios_table
, smbios_len
);
599 fw_cfg_add_bytes(fw_cfg
, FW_CFG_E820_TABLE
, (uint8_t *)&e820_table
,
600 sizeof(struct e820_table
));
602 fw_cfg_add_bytes(fw_cfg
, FW_CFG_HPET
, (uint8_t *)&hpet_cfg
,
603 sizeof(struct hpet_fw_config
));
604 /* allocate memory for the NUMA channel: one (64bit) word for the number
605 * of nodes, one word for each VCPU->node and one word for each node to
606 * hold the amount of memory.
608 numa_fw_cfg
= qemu_mallocz((1 + smp_cpus
+ nb_numa_nodes
) * 8);
609 numa_fw_cfg
[0] = cpu_to_le64(nb_numa_nodes
);
610 for (i
= 0; i
< smp_cpus
; i
++) {
611 for (j
= 0; j
< nb_numa_nodes
; j
++) {
612 if (node_cpumask
[j
] & (1 << i
)) {
613 numa_fw_cfg
[i
+ 1] = cpu_to_le64(j
);
618 for (i
= 0; i
< nb_numa_nodes
; i
++) {
619 numa_fw_cfg
[smp_cpus
+ 1 + i
] = cpu_to_le64(node_mem
[i
]);
621 fw_cfg_add_bytes(fw_cfg
, FW_CFG_NUMA
, (uint8_t *)numa_fw_cfg
,
622 (1 + smp_cpus
+ nb_numa_nodes
) * 8);
627 static long get_file_size(FILE *f
)
631 /* XXX: on Unix systems, using fstat() probably makes more sense */
634 fseek(f
, 0, SEEK_END
);
636 fseek(f
, where
, SEEK_SET
);
641 static void load_linux(void *fw_cfg
,
642 const char *kernel_filename
,
643 const char *initrd_filename
,
644 const char *kernel_cmdline
,
645 target_phys_addr_t max_ram_size
)
648 int setup_size
, kernel_size
, initrd_size
= 0, cmdline_size
;
650 uint8_t header
[8192], *setup
, *kernel
, *initrd_data
;
651 target_phys_addr_t real_addr
, prot_addr
, cmdline_addr
, initrd_addr
= 0;
655 /* Align to 16 bytes as a paranoia measure */
656 cmdline_size
= (strlen(kernel_cmdline
)+16) & ~15;
658 /* load the kernel header */
659 f
= fopen(kernel_filename
, "rb");
660 if (!f
|| !(kernel_size
= get_file_size(f
)) ||
661 fread(header
, 1, MIN(ARRAY_SIZE(header
), kernel_size
), f
) !=
662 MIN(ARRAY_SIZE(header
), kernel_size
)) {
663 fprintf(stderr
, "qemu: could not load kernel '%s': %s\n",
664 kernel_filename
, strerror(errno
));
668 /* kernel protocol version */
670 fprintf(stderr
, "header magic: %#x\n", ldl_p(header
+0x202));
672 if (ldl_p(header
+0x202) == 0x53726448)
673 protocol
= lduw_p(header
+0x206);
675 /* This looks like a multiboot kernel. If it is, let's stop
676 treating it like a Linux kernel. */
677 if (load_multiboot(fw_cfg
, f
, kernel_filename
, initrd_filename
,
678 kernel_cmdline
, kernel_size
, header
))
683 if (protocol
< 0x200 || !(header
[0x211] & 0x01)) {
686 cmdline_addr
= 0x9a000 - cmdline_size
;
688 } else if (protocol
< 0x202) {
689 /* High but ancient kernel */
691 cmdline_addr
= 0x9a000 - cmdline_size
;
692 prot_addr
= 0x100000;
694 /* High and recent kernel */
696 cmdline_addr
= 0x20000;
697 prot_addr
= 0x100000;
702 "qemu: real_addr = 0x" TARGET_FMT_plx
"\n"
703 "qemu: cmdline_addr = 0x" TARGET_FMT_plx
"\n"
704 "qemu: prot_addr = 0x" TARGET_FMT_plx
"\n",
710 /* highest address for loading the initrd */
711 if (protocol
>= 0x203)
712 initrd_max
= ldl_p(header
+0x22c);
714 initrd_max
= 0x37ffffff;
716 if (initrd_max
>= max_ram_size
-ACPI_DATA_SIZE
)
717 initrd_max
= max_ram_size
-ACPI_DATA_SIZE
-1;
719 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_ADDR
, cmdline_addr
);
720 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, strlen(kernel_cmdline
)+1);
721 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
722 (uint8_t*)strdup(kernel_cmdline
),
723 strlen(kernel_cmdline
)+1);
725 if (protocol
>= 0x202) {
726 stl_p(header
+0x228, cmdline_addr
);
728 stw_p(header
+0x20, 0xA33F);
729 stw_p(header
+0x22, cmdline_addr
-real_addr
);
732 /* handle vga= parameter */
733 vmode
= strstr(kernel_cmdline
, "vga=");
735 unsigned int video_mode
;
738 if (!strncmp(vmode
, "normal", 6)) {
740 } else if (!strncmp(vmode
, "ext", 3)) {
742 } else if (!strncmp(vmode
, "ask", 3)) {
745 video_mode
= strtol(vmode
, NULL
, 0);
747 stw_p(header
+0x1fa, video_mode
);
751 /* High nybble = B reserved for Qemu; low nybble is revision number.
752 If this code is substantially changed, you may want to consider
753 incrementing the revision. */
754 if (protocol
>= 0x200)
755 header
[0x210] = 0xB0;
758 if (protocol
>= 0x201) {
759 header
[0x211] |= 0x80; /* CAN_USE_HEAP */
760 stw_p(header
+0x224, cmdline_addr
-real_addr
-0x200);
764 if (initrd_filename
) {
765 if (protocol
< 0x200) {
766 fprintf(stderr
, "qemu: linux kernel too old to load a ram disk\n");
770 initrd_size
= get_image_size(initrd_filename
);
771 if (initrd_size
< 0) {
772 fprintf(stderr
, "qemu: error reading initrd %s\n",
777 initrd_addr
= (initrd_max
-initrd_size
) & ~4095;
779 initrd_data
= qemu_malloc(initrd_size
);
780 load_image(initrd_filename
, initrd_data
);
782 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, initrd_addr
);
783 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
784 fw_cfg_add_bytes(fw_cfg
, FW_CFG_INITRD_DATA
, initrd_data
, initrd_size
);
786 stl_p(header
+0x218, initrd_addr
);
787 stl_p(header
+0x21c, initrd_size
);
790 /* load kernel and setup */
791 setup_size
= header
[0x1f1];
794 setup_size
= (setup_size
+1)*512;
795 kernel_size
-= setup_size
;
797 setup
= qemu_malloc(setup_size
);
798 kernel
= qemu_malloc(kernel_size
);
799 fseek(f
, 0, SEEK_SET
);
800 if (fread(setup
, 1, setup_size
, f
) != setup_size
) {
801 fprintf(stderr
, "fread() failed\n");
804 if (fread(kernel
, 1, kernel_size
, f
) != kernel_size
) {
805 fprintf(stderr
, "fread() failed\n");
809 memcpy(setup
, header
, MIN(sizeof(header
), setup_size
));
811 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, prot_addr
);
812 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
813 fw_cfg_add_bytes(fw_cfg
, FW_CFG_KERNEL_DATA
, kernel
, kernel_size
);
815 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_ADDR
, real_addr
);
816 fw_cfg_add_i32(fw_cfg
, FW_CFG_SETUP_SIZE
, setup_size
);
817 fw_cfg_add_bytes(fw_cfg
, FW_CFG_SETUP_DATA
, setup
, setup_size
);
819 option_rom
[nb_option_roms
].name
= "linuxboot.bin";
820 option_rom
[nb_option_roms
].bootindex
= 0;
824 #define NE2000_NB_MAX 6
826 static const int ne2000_io
[NE2000_NB_MAX
] = { 0x300, 0x320, 0x340, 0x360,
828 static const int ne2000_irq
[NE2000_NB_MAX
] = { 9, 10, 11, 3, 4, 5 };
830 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
831 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
833 void pc_init_ne2k_isa(NICInfo
*nd
)
835 static int nb_ne2k
= 0;
837 if (nb_ne2k
== NE2000_NB_MAX
)
839 isa_ne2000_init(ne2000_io
[nb_ne2k
],
840 ne2000_irq
[nb_ne2k
], nd
);
844 int cpu_is_bsp(CPUState
*env
)
846 /* We hard-wire the BSP to the first CPU. */
847 return env
->cpu_index
== 0;
850 DeviceState
*cpu_get_current_apic(void)
852 if (cpu_single_env
) {
853 return cpu_single_env
->apic_state
;
859 static DeviceState
*apic_init(void *env
, uint8_t apic_id
)
863 static int apic_mapped
;
865 dev
= qdev_create(NULL
, "apic");
866 qdev_prop_set_uint8(dev
, "id", apic_id
);
867 qdev_prop_set_ptr(dev
, "cpu_env", env
);
868 qdev_init_nofail(dev
);
869 d
= sysbus_from_qdev(dev
);
871 /* XXX: mapping more APICs at the same memory location */
872 if (apic_mapped
== 0) {
873 /* NOTE: the APIC is directly connected to the CPU - it is not
874 on the global memory bus. */
875 /* XXX: what if the base changes? */
876 sysbus_mmio_map(d
, 0, MSI_ADDR_BASE
);
885 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
886 BIOS will read it and start S3 resume at POST Entry */
887 void pc_cmos_set_s3_resume(void *opaque
, int irq
, int level
)
889 ISADevice
*s
= opaque
;
892 rtc_set_memory(s
, 0xF, 0xFE);
896 void pc_acpi_smi_interrupt(void *opaque
, int irq
, int level
)
898 CPUState
*s
= opaque
;
901 cpu_interrupt(s
, CPU_INTERRUPT_SMI
);
905 static void pc_cpu_reset(void *opaque
)
907 CPUState
*env
= opaque
;
910 env
->halted
= !cpu_is_bsp(env
);
913 static CPUState
*pc_new_cpu(const char *cpu_model
)
917 env
= cpu_init(cpu_model
);
919 fprintf(stderr
, "Unable to find x86 CPU definition\n");
922 if ((env
->cpuid_features
& CPUID_APIC
) || smp_cpus
> 1) {
923 env
->cpuid_apic_id
= env
->cpu_index
;
924 env
->apic_state
= apic_init(env
, env
->cpuid_apic_id
);
926 qemu_register_reset(pc_cpu_reset
, env
);
931 void pc_cpus_init(const char *cpu_model
)
936 if (cpu_model
== NULL
) {
938 cpu_model
= "qemu64";
940 cpu_model
= "qemu32";
944 for(i
= 0; i
< smp_cpus
; i
++) {
945 pc_new_cpu(cpu_model
);
949 void pc_memory_init(ram_addr_t ram_size
,
950 const char *kernel_filename
,
951 const char *kernel_cmdline
,
952 const char *initrd_filename
,
953 ram_addr_t
*below_4g_mem_size_p
,
954 ram_addr_t
*above_4g_mem_size_p
)
957 int ret
, linux_boot
, i
;
958 ram_addr_t ram_addr
, bios_offset
, option_rom_offset
;
959 ram_addr_t below_4g_mem_size
, above_4g_mem_size
= 0;
960 int bios_size
, isa_bios_size
;
963 if (ram_size
>= 0xe0000000 ) {
964 above_4g_mem_size
= ram_size
- 0xe0000000;
965 below_4g_mem_size
= 0xe0000000;
967 below_4g_mem_size
= ram_size
;
969 *above_4g_mem_size_p
= above_4g_mem_size
;
970 *below_4g_mem_size_p
= below_4g_mem_size
;
972 #if TARGET_PHYS_ADDR_BITS == 32
973 if (above_4g_mem_size
> 0) {
974 hw_error("To much RAM for 32-bit physical address");
977 linux_boot
= (kernel_filename
!= NULL
);
980 ram_addr
= qemu_ram_alloc(NULL
, "pc.ram",
981 below_4g_mem_size
+ above_4g_mem_size
);
982 cpu_register_physical_memory(0, 0xa0000, ram_addr
);
983 cpu_register_physical_memory(0x100000,
984 below_4g_mem_size
- 0x100000,
985 ram_addr
+ 0x100000);
986 #if TARGET_PHYS_ADDR_BITS > 32
987 if (above_4g_mem_size
> 0) {
988 cpu_register_physical_memory(0x100000000ULL
, above_4g_mem_size
,
989 ram_addr
+ below_4g_mem_size
);
994 if (bios_name
== NULL
)
995 bios_name
= BIOS_FILENAME
;
996 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
998 bios_size
= get_image_size(filename
);
1002 if (bios_size
<= 0 ||
1003 (bios_size
% 65536) != 0) {
1006 bios_offset
= qemu_ram_alloc(NULL
, "pc.bios", bios_size
);
1007 ret
= rom_add_file_fixed(bios_name
, (uint32_t)(-bios_size
), -1);
1010 fprintf(stderr
, "qemu: could not load PC BIOS '%s'\n", bios_name
);
1014 qemu_free(filename
);
1016 /* map the last 128KB of the BIOS in ISA space */
1017 isa_bios_size
= bios_size
;
1018 if (isa_bios_size
> (128 * 1024))
1019 isa_bios_size
= 128 * 1024;
1020 cpu_register_physical_memory(0x100000 - isa_bios_size
,
1022 (bios_offset
+ bios_size
- isa_bios_size
) | IO_MEM_ROM
);
1024 option_rom_offset
= qemu_ram_alloc(NULL
, "pc.rom", PC_ROM_SIZE
);
1025 cpu_register_physical_memory(PC_ROM_MIN_VGA
, PC_ROM_SIZE
, option_rom_offset
);
1027 /* map all the bios at the top of memory */
1028 cpu_register_physical_memory((uint32_t)(-bios_size
),
1029 bios_size
, bios_offset
| IO_MEM_ROM
);
1031 fw_cfg
= bochs_bios_init();
1035 load_linux(fw_cfg
, kernel_filename
, initrd_filename
, kernel_cmdline
, below_4g_mem_size
);
1038 for (i
= 0; i
< nb_option_roms
; i
++) {
1039 rom_add_option(option_rom
[i
].name
, option_rom
[i
].bootindex
);
1043 qemu_irq
*pc_allocate_cpu_irq(void)
1045 return qemu_allocate_irqs(pic_irq_request
, NULL
, 1);
1048 void pc_vga_init(PCIBus
*pci_bus
)
1050 if (cirrus_vga_enabled
) {
1052 pci_cirrus_vga_init(pci_bus
);
1054 isa_cirrus_vga_init();
1056 } else if (vmsvga_enabled
) {
1058 if (!pci_vmsvga_init(pci_bus
)) {
1059 fprintf(stderr
, "Warning: vmware_vga not available,"
1060 " using standard VGA instead\n");
1061 pci_vga_init(pci_bus
);
1064 fprintf(stderr
, "%s: vmware_vga: no PCI bus\n", __FUNCTION__
);
1067 } else if (qxl_enabled
) {
1069 pci_create_simple(pci_bus
, -1, "qxl-vga");
1071 fprintf(stderr
, "%s: qxl: no PCI bus\n", __FUNCTION__
);
1073 } else if (std_vga_enabled
) {
1075 pci_vga_init(pci_bus
);
1082 static void cpu_request_exit(void *opaque
, int irq
, int level
)
1084 CPUState
*env
= cpu_single_env
;
1091 void pc_basic_device_init(qemu_irq
*isa_irq
,
1092 FDCtrl
**floppy_controller
,
1093 ISADevice
**rtc_state
)
1096 DriveInfo
*fd
[MAX_FD
];
1098 qemu_irq rtc_irq
= NULL
;
1100 ISADevice
*i8042
, *port92
, *vmmouse
;
1101 qemu_irq
*cpu_exit_irq
;
1103 register_ioport_write(0x80, 1, 1, ioport80_write
, NULL
);
1105 register_ioport_write(0xf0, 1, 1, ioportF0_write
, NULL
);
1108 DeviceState
*hpet
= sysbus_try_create_simple("hpet", HPET_BASE
, NULL
);
1111 for (i
= 0; i
< 24; i
++) {
1112 sysbus_connect_irq(sysbus_from_qdev(hpet
), i
, isa_irq
[i
]);
1114 rtc_irq
= qdev_get_gpio_in(hpet
, 0);
1117 *rtc_state
= rtc_init(2000, rtc_irq
);
1119 qemu_register_boot_set(pc_boot_set
, *rtc_state
);
1121 pit
= pit_init(0x40, isa_reserve_irq(0));
1124 for(i
= 0; i
< MAX_SERIAL_PORTS
; i
++) {
1125 if (serial_hds
[i
]) {
1126 serial_isa_init(i
, serial_hds
[i
]);
1130 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
1131 if (parallel_hds
[i
]) {
1132 parallel_init(i
, parallel_hds
[i
]);
1136 a20_line
= qemu_allocate_irqs(handle_a20_line_change
, first_cpu
, 2);
1137 i8042
= isa_create_simple("i8042");
1138 i8042_setup_a20_line(i8042
, &a20_line
[0]);
1140 vmmouse
= isa_try_create("vmmouse");
1142 qdev_prop_set_ptr(&vmmouse
->qdev
, "ps2_mouse", i8042
);
1144 port92
= isa_create_simple("port92");
1145 port92_init(port92
, &a20_line
[1]);
1147 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
1148 DMA_init(0, cpu_exit_irq
);
1150 for(i
= 0; i
< MAX_FD
; i
++) {
1151 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1153 *floppy_controller
= fdctrl_init_isa(fd
);
1156 void pc_pci_device_init(PCIBus
*pci_bus
)
1161 max_bus
= drive_get_max_bus(IF_SCSI
);
1162 for (bus
= 0; bus
<= max_bus
; bus
++) {
1163 pci_create_simple(pci_bus
, -1, "lsi53c895a");