4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/pci/pci.h"
26 #include "hw/pci/pci_bridge.h"
27 #include "hw/pci/pci_bus.h"
28 #include "monitor/monitor.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/loader.h"
32 #include "qemu/range.h"
33 #include "qmp-commands.h"
34 #include "hw/pci/msi.h"
35 #include "hw/pci/msix.h"
36 #include "exec/address-spaces.h"
40 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
42 # define PCI_DPRINTF(format, ...) do { } while (0)
45 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
46 static char *pcibus_get_dev_path(DeviceState
*dev
);
47 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
48 static int pcibus_reset(BusState
*qbus
);
50 static Property pci_props
[] = {
51 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
52 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
53 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
54 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
55 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
56 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
57 QEMU_PCI_CAP_SERR_BITNR
, true),
58 DEFINE_PROP_END_OF_LIST()
61 static void pci_bus_class_init(ObjectClass
*klass
, void *data
)
63 BusClass
*k
= BUS_CLASS(klass
);
65 k
->print_dev
= pcibus_dev_print
;
66 k
->get_dev_path
= pcibus_get_dev_path
;
67 k
->get_fw_dev_path
= pcibus_get_fw_dev_path
;
68 k
->reset
= pcibus_reset
;
71 static const TypeInfo pci_bus_info
= {
74 .instance_size
= sizeof(PCIBus
),
75 .class_init
= pci_bus_class_init
,
78 static const TypeInfo pcie_bus_info
= {
79 .name
= TYPE_PCIE_BUS
,
80 .parent
= TYPE_PCI_BUS
,
83 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
84 static void pci_update_mappings(PCIDevice
*d
);
85 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
86 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
87 static void pci_del_option_rom(PCIDevice
*pdev
);
89 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
90 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
95 QLIST_ENTRY(PCIHostBus
) next
;
97 static QLIST_HEAD(, PCIHostBus
) host_buses
;
99 static const VMStateDescription vmstate_pcibus
= {
102 .minimum_version_id
= 1,
103 .minimum_version_id_old
= 1,
104 .fields
= (VMStateField
[]) {
105 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
106 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
107 VMSTATE_END_OF_LIST()
110 static int pci_bar(PCIDevice
*d
, int reg
)
114 if (reg
!= PCI_ROM_SLOT
)
115 return PCI_BASE_ADDRESS_0
+ reg
* 4;
117 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
118 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
121 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
123 return (d
->irq_state
>> irq_num
) & 0x1;
126 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
128 d
->irq_state
&= ~(0x1 << irq_num
);
129 d
->irq_state
|= level
<< irq_num
;
132 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
137 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
140 pci_dev
= bus
->parent_dev
;
142 bus
->irq_count
[irq_num
] += change
;
143 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
146 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
148 assert(irq_num
>= 0);
149 assert(irq_num
< bus
->nirq
);
150 return !!bus
->irq_count
[irq_num
];
153 /* Update interrupt status bit in config space on interrupt
155 static void pci_update_irq_status(PCIDevice
*dev
)
157 if (dev
->irq_state
) {
158 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
160 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
164 void pci_device_deassert_intx(PCIDevice
*dev
)
167 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
168 qemu_set_irq(dev
->irq
[i
], 0);
173 * This function is called on #RST and FLR.
174 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
176 void pci_device_reset(PCIDevice
*dev
)
180 qdev_reset_all(&dev
->qdev
);
183 pci_update_irq_status(dev
);
184 pci_device_deassert_intx(dev
);
185 /* Clear all writable bits */
186 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
187 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
188 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
189 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
190 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
191 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
192 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
193 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
194 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
195 PCIIORegion
*region
= &dev
->io_regions
[r
];
200 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
201 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
202 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
204 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
207 pci_update_mappings(dev
);
214 * Trigger pci bus reset under a given bus.
215 * To be called on RST# assert.
217 void pci_bus_reset(PCIBus
*bus
)
221 for (i
= 0; i
< bus
->nirq
; i
++) {
222 bus
->irq_count
[i
] = 0;
224 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
225 if (bus
->devices
[i
]) {
226 pci_device_reset(bus
->devices
[i
]);
231 static int pcibus_reset(BusState
*qbus
)
233 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
235 /* topology traverse is done by pci_bus_reset().
236 Tell qbus/qdev walker not to traverse the tree */
240 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
242 struct PCIHostBus
*host
;
243 host
= g_malloc0(sizeof(*host
));
244 host
->domain
= domain
;
246 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
249 PCIBus
*pci_find_root_bus(int domain
)
251 struct PCIHostBus
*host
;
253 QLIST_FOREACH(host
, &host_buses
, next
) {
254 if (host
->domain
== domain
) {
262 int pci_find_domain(const PCIBus
*bus
)
265 struct PCIHostBus
*host
;
267 /* obtain root bus */
268 while ((d
= bus
->parent_dev
) != NULL
) {
272 QLIST_FOREACH(host
, &host_buses
, next
) {
273 if (host
->bus
== bus
) {
278 abort(); /* should not be reached */
282 static void pci_bus_init(PCIBus
*bus
, DeviceState
*parent
,
284 MemoryRegion
*address_space_mem
,
285 MemoryRegion
*address_space_io
,
288 assert(PCI_FUNC(devfn_min
) == 0);
289 bus
->devfn_min
= devfn_min
;
290 bus
->address_space_mem
= address_space_mem
;
291 bus
->address_space_io
= address_space_io
;
294 QLIST_INIT(&bus
->child
);
295 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
297 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
300 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
302 MemoryRegion
*address_space_mem
,
303 MemoryRegion
*address_space_io
,
304 uint8_t devfn_min
, const char *typename
)
306 qbus_create_inplace(bus
, typename
, parent
, name
);
307 pci_bus_init(bus
, parent
, name
, address_space_mem
,
308 address_space_io
, devfn_min
);
311 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
312 MemoryRegion
*address_space_mem
,
313 MemoryRegion
*address_space_io
,
314 uint8_t devfn_min
, const char *typename
)
318 bus
= PCI_BUS(qbus_create(typename
, parent
, name
));
319 pci_bus_init(bus
, parent
, name
, address_space_mem
,
320 address_space_io
, devfn_min
);
324 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
325 void *irq_opaque
, int nirq
)
327 bus
->set_irq
= set_irq
;
328 bus
->map_irq
= map_irq
;
329 bus
->irq_opaque
= irq_opaque
;
331 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
334 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
336 bus
->qbus
.allow_hotplug
= 1;
337 bus
->hotplug
= hotplug
;
338 bus
->hotplug_qdev
= qdev
;
341 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
342 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
344 MemoryRegion
*address_space_mem
,
345 MemoryRegion
*address_space_io
,
346 uint8_t devfn_min
, int nirq
, const char *typename
)
350 bus
= pci_bus_new(parent
, name
, address_space_mem
,
351 address_space_io
, devfn_min
, typename
);
352 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
356 int pci_bus_num(PCIBus
*s
)
359 return 0; /* pci host bridge */
360 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
363 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
365 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
369 assert(size
== pci_config_size(s
));
370 config
= g_malloc(size
);
372 qemu_get_buffer(f
, config
, size
);
373 for (i
= 0; i
< size
; ++i
) {
374 if ((config
[i
] ^ s
->config
[i
]) &
375 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
380 memcpy(s
->config
, config
, size
);
382 pci_update_mappings(s
);
384 memory_region_set_enabled(&s
->bus_master_enable_region
,
385 pci_get_word(s
->config
+ PCI_COMMAND
)
386 & PCI_COMMAND_MASTER
);
392 /* just put buffer */
393 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
395 const uint8_t **v
= pv
;
396 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
397 qemu_put_buffer(f
, *v
, size
);
400 static VMStateInfo vmstate_info_pci_config
= {
401 .name
= "pci config",
402 .get
= get_pci_config_device
,
403 .put
= put_pci_config_device
,
406 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
408 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
409 uint32_t irq_state
[PCI_NUM_PINS
];
411 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
412 irq_state
[i
] = qemu_get_be32(f
);
413 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
414 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
420 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
421 pci_set_irq_state(s
, i
, irq_state
[i
]);
427 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
430 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
432 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
433 qemu_put_be32(f
, pci_irq_state(s
, i
));
437 static VMStateInfo vmstate_info_pci_irq_state
= {
438 .name
= "pci irq state",
439 .get
= get_pci_irq_state
,
440 .put
= put_pci_irq_state
,
443 const VMStateDescription vmstate_pci_device
= {
446 .minimum_version_id
= 1,
447 .minimum_version_id_old
= 1,
448 .fields
= (VMStateField
[]) {
449 VMSTATE_INT32_LE(version_id
, PCIDevice
),
450 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
451 vmstate_info_pci_config
,
452 PCI_CONFIG_SPACE_SIZE
),
453 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
454 vmstate_info_pci_irq_state
,
455 PCI_NUM_PINS
* sizeof(int32_t)),
456 VMSTATE_END_OF_LIST()
460 const VMStateDescription vmstate_pcie_device
= {
461 .name
= "PCIEDevice",
463 .minimum_version_id
= 1,
464 .minimum_version_id_old
= 1,
465 .fields
= (VMStateField
[]) {
466 VMSTATE_INT32_LE(version_id
, PCIDevice
),
467 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
468 vmstate_info_pci_config
,
469 PCIE_CONFIG_SPACE_SIZE
),
470 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
471 vmstate_info_pci_irq_state
,
472 PCI_NUM_PINS
* sizeof(int32_t)),
473 VMSTATE_END_OF_LIST()
477 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
479 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
482 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
484 /* Clear interrupt status bit: it is implicit
485 * in irq_state which we are saving.
486 * This makes us compatible with old devices
487 * which never set or clear this bit. */
488 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
489 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
490 /* Restore the interrupt status bit. */
491 pci_update_irq_status(s
);
494 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
497 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
498 /* Restore the interrupt status bit. */
499 pci_update_irq_status(s
);
503 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
505 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
506 pci_default_sub_vendor_id
);
507 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
508 pci_default_sub_device_id
);
512 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
513 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
515 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
516 unsigned int *slotp
, unsigned int *funcp
)
521 unsigned long dom
= 0, bus
= 0;
522 unsigned int slot
= 0;
523 unsigned int func
= 0;
526 val
= strtoul(p
, &e
, 16);
532 val
= strtoul(p
, &e
, 16);
539 val
= strtoul(p
, &e
, 16);
552 val
= strtoul(p
, &e
, 16);
559 /* if funcp == NULL func is 0 */
560 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
574 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
577 /* strip legacy tag */
578 if (!strncmp(addr
, "pci_addr=", 9)) {
581 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
582 monitor_printf(mon
, "Invalid pci address\n");
588 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
595 return pci_find_bus_nr(pci_find_root_bus(0), 0);
598 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
602 *devfnp
= PCI_DEVFN(slot
, 0);
603 return pci_find_bus_nr(pci_find_root_bus(dom
), bus
);
606 static void pci_init_cmask(PCIDevice
*dev
)
608 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
609 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
610 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
611 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
612 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
613 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
614 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
615 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
618 static void pci_init_wmask(PCIDevice
*dev
)
620 int config_size
= pci_config_size(dev
);
622 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
623 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
624 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
625 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
626 PCI_COMMAND_INTX_DISABLE
);
627 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
628 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
631 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
632 config_size
- PCI_CONFIG_HEADER_SIZE
);
635 static void pci_init_w1cmask(PCIDevice
*dev
)
638 * Note: It's okay to set w1cmask even for readonly bits as
639 * long as their value is hardwired to 0.
641 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
642 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
643 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
644 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
647 static void pci_init_mask_bridge(PCIDevice
*d
)
649 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
650 PCI_SEC_LETENCY_TIMER */
651 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
654 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
655 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
656 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
657 PCI_MEMORY_RANGE_MASK
& 0xffff);
658 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
659 PCI_MEMORY_RANGE_MASK
& 0xffff);
660 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
661 PCI_PREF_RANGE_MASK
& 0xffff);
662 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
663 PCI_PREF_RANGE_MASK
& 0xffff);
665 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
666 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
668 /* Supported memory and i/o types */
669 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
670 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
671 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
672 PCI_PREF_RANGE_TYPE_64
);
673 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
674 PCI_PREF_RANGE_TYPE_64
);
677 * TODO: Bridges default to 10-bit VGA decoding but we currently only
678 * implement 16-bit decoding (no alias support).
680 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
681 PCI_BRIDGE_CTL_PARITY
|
682 PCI_BRIDGE_CTL_SERR
|
685 PCI_BRIDGE_CTL_VGA_16BIT
|
686 PCI_BRIDGE_CTL_MASTER_ABORT
|
687 PCI_BRIDGE_CTL_BUS_RESET
|
688 PCI_BRIDGE_CTL_FAST_BACK
|
689 PCI_BRIDGE_CTL_DISCARD
|
690 PCI_BRIDGE_CTL_SEC_DISCARD
|
691 PCI_BRIDGE_CTL_DISCARD_SERR
);
692 /* Below does not do anything as we never set this bit, put here for
694 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
695 PCI_BRIDGE_CTL_DISCARD_STATUS
);
696 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
697 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
698 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
699 PCI_PREF_RANGE_TYPE_MASK
);
700 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
701 PCI_PREF_RANGE_TYPE_MASK
);
704 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
706 uint8_t slot
= PCI_SLOT(dev
->devfn
);
709 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
710 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
714 * multifunction bit is interpreted in two ways as follows.
715 * - all functions must set the bit to 1.
717 * - function 0 must set the bit, but the rest function (> 0)
718 * is allowed to leave the bit to 0.
719 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
721 * So OS (at least Linux) checks the bit of only function 0,
722 * and doesn't see the bit of function > 0.
724 * The below check allows both interpretation.
726 if (PCI_FUNC(dev
->devfn
)) {
727 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
728 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
729 /* function 0 should set multifunction bit */
730 error_report("PCI: single function device can't be populated "
731 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
737 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
740 /* function 0 indicates single function, so function > 0 must be NULL */
741 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
742 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
743 error_report("PCI: %x.0 indicates single function, "
744 "but %x.%x is already populated.",
752 static void pci_config_alloc(PCIDevice
*pci_dev
)
754 int config_size
= pci_config_size(pci_dev
);
756 pci_dev
->config
= g_malloc0(config_size
);
757 pci_dev
->cmask
= g_malloc0(config_size
);
758 pci_dev
->wmask
= g_malloc0(config_size
);
759 pci_dev
->w1cmask
= g_malloc0(config_size
);
760 pci_dev
->used
= g_malloc0(config_size
);
763 static void pci_config_free(PCIDevice
*pci_dev
)
765 g_free(pci_dev
->config
);
766 g_free(pci_dev
->cmask
);
767 g_free(pci_dev
->wmask
);
768 g_free(pci_dev
->w1cmask
);
769 g_free(pci_dev
->used
);
772 /* -1 for devfn means auto assign */
773 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
774 const char *name
, int devfn
)
776 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
777 PCIConfigReadFunc
*config_read
= pc
->config_read
;
778 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
781 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
782 devfn
+= PCI_FUNC_MAX
) {
783 if (!bus
->devices
[devfn
])
786 error_report("PCI: no slot/function available for %s, all in use", name
);
789 } else if (bus
->devices
[devfn
]) {
790 error_report("PCI: slot %d function %d not available for %s, in use by %s",
791 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
795 if (bus
->dma_context_fn
) {
796 pci_dev
->dma
= bus
->dma_context_fn(bus
, bus
->dma_context_opaque
, devfn
);
798 /* FIXME: Make dma_context_fn use MemoryRegions instead, so this path is
799 * taken unconditionally */
800 /* FIXME: inherit memory region from bus creator */
801 memory_region_init_alias(&pci_dev
->bus_master_enable_region
, "bus master",
802 get_system_memory(), 0,
803 memory_region_size(get_system_memory()));
804 memory_region_set_enabled(&pci_dev
->bus_master_enable_region
, false);
805 address_space_init(&pci_dev
->bus_master_as
, &pci_dev
->bus_master_enable_region
);
806 pci_dev
->dma
= g_new(DMAContext
, 1);
807 dma_context_init(pci_dev
->dma
, &pci_dev
->bus_master_as
, NULL
, NULL
, NULL
);
809 pci_dev
->devfn
= devfn
;
810 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
811 pci_dev
->irq_state
= 0;
812 pci_config_alloc(pci_dev
);
814 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
815 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
816 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
817 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
819 if (!pc
->is_bridge
) {
820 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
821 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
822 pc
->subsystem_vendor_id
);
823 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
826 pci_set_default_subsystem_id(pci_dev
);
829 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
830 assert(!pc
->subsystem_vendor_id
);
831 assert(!pc
->subsystem_id
);
833 pci_init_cmask(pci_dev
);
834 pci_init_wmask(pci_dev
);
835 pci_init_w1cmask(pci_dev
);
837 pci_init_mask_bridge(pci_dev
);
839 if (pci_init_multifunction(bus
, pci_dev
)) {
840 pci_config_free(pci_dev
);
845 config_read
= pci_default_read_config
;
847 config_write
= pci_default_write_config
;
848 pci_dev
->config_read
= config_read
;
849 pci_dev
->config_write
= config_write
;
850 bus
->devices
[devfn
] = pci_dev
;
851 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
852 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
856 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
858 qemu_free_irqs(pci_dev
->irq
);
859 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
860 pci_config_free(pci_dev
);
862 if (!pci_dev
->bus
->dma_context_fn
) {
863 address_space_destroy(&pci_dev
->bus_master_as
);
864 memory_region_destroy(&pci_dev
->bus_master_enable_region
);
865 g_free(pci_dev
->dma
);
870 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
875 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
876 r
= &pci_dev
->io_regions
[i
];
877 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
879 memory_region_del_subregion(r
->address_space
, r
->memory
);
882 pci_unregister_vga(pci_dev
);
885 static int pci_unregister_device(DeviceState
*dev
)
887 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
888 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
890 pci_unregister_io_regions(pci_dev
);
891 pci_del_option_rom(pci_dev
);
897 do_pci_unregister_device(pci_dev
);
901 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
902 uint8_t type
, MemoryRegion
*memory
)
907 pcibus_t size
= memory_region_size(memory
);
909 assert(region_num
>= 0);
910 assert(region_num
< PCI_NUM_REGIONS
);
911 if (size
& (size
-1)) {
912 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
913 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
917 r
= &pci_dev
->io_regions
[region_num
];
918 r
->addr
= PCI_BAR_UNMAPPED
;
924 addr
= pci_bar(pci_dev
, region_num
);
925 if (region_num
== PCI_ROM_SLOT
) {
926 /* ROM enable bit is writable */
927 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
929 pci_set_long(pci_dev
->config
+ addr
, type
);
930 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
931 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
932 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
933 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
935 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
936 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
938 pci_dev
->io_regions
[region_num
].memory
= memory
;
939 pci_dev
->io_regions
[region_num
].address_space
940 = type
& PCI_BASE_ADDRESS_SPACE_IO
941 ? pci_dev
->bus
->address_space_io
942 : pci_dev
->bus
->address_space_mem
;
945 static void pci_update_vga(PCIDevice
*pci_dev
)
949 if (!pci_dev
->has_vga
) {
953 cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
955 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
],
956 cmd
& PCI_COMMAND_MEMORY
);
957 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
],
958 cmd
& PCI_COMMAND_IO
);
959 memory_region_set_enabled(pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
],
960 cmd
& PCI_COMMAND_IO
);
963 void pci_register_vga(PCIDevice
*pci_dev
, MemoryRegion
*mem
,
964 MemoryRegion
*io_lo
, MemoryRegion
*io_hi
)
966 assert(!pci_dev
->has_vga
);
968 assert(memory_region_size(mem
) == QEMU_PCI_VGA_MEM_SIZE
);
969 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
] = mem
;
970 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_mem
,
971 QEMU_PCI_VGA_MEM_BASE
, mem
, 1);
973 assert(memory_region_size(io_lo
) == QEMU_PCI_VGA_IO_LO_SIZE
);
974 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
] = io_lo
;
975 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_io
,
976 QEMU_PCI_VGA_IO_LO_BASE
, io_lo
, 1);
978 assert(memory_region_size(io_hi
) == QEMU_PCI_VGA_IO_HI_SIZE
);
979 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
] = io_hi
;
980 memory_region_add_subregion_overlap(pci_dev
->bus
->address_space_io
,
981 QEMU_PCI_VGA_IO_HI_BASE
, io_hi
, 1);
982 pci_dev
->has_vga
= true;
984 pci_update_vga(pci_dev
);
987 void pci_unregister_vga(PCIDevice
*pci_dev
)
989 if (!pci_dev
->has_vga
) {
993 memory_region_del_subregion(pci_dev
->bus
->address_space_mem
,
994 pci_dev
->vga_regions
[QEMU_PCI_VGA_MEM
]);
995 memory_region_del_subregion(pci_dev
->bus
->address_space_io
,
996 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_LO
]);
997 memory_region_del_subregion(pci_dev
->bus
->address_space_io
,
998 pci_dev
->vga_regions
[QEMU_PCI_VGA_IO_HI
]);
999 pci_dev
->has_vga
= false;
1002 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
1004 return pci_dev
->io_regions
[region_num
].addr
;
1007 static pcibus_t
pci_bar_address(PCIDevice
*d
,
1008 int reg
, uint8_t type
, pcibus_t size
)
1010 pcibus_t new_addr
, last_addr
;
1011 int bar
= pci_bar(d
, reg
);
1012 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
1014 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1015 if (!(cmd
& PCI_COMMAND_IO
)) {
1016 return PCI_BAR_UNMAPPED
;
1018 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
1019 last_addr
= new_addr
+ size
- 1;
1020 /* NOTE: we have only 64K ioports on PC */
1021 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
1022 return PCI_BAR_UNMAPPED
;
1027 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
1028 return PCI_BAR_UNMAPPED
;
1030 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
1031 new_addr
= pci_get_quad(d
->config
+ bar
);
1033 new_addr
= pci_get_long(d
->config
+ bar
);
1035 /* the ROM slot has a specific enable bit */
1036 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
1037 return PCI_BAR_UNMAPPED
;
1039 new_addr
&= ~(size
- 1);
1040 last_addr
= new_addr
+ size
- 1;
1041 /* NOTE: we do not support wrapping */
1042 /* XXX: as we cannot support really dynamic
1043 mappings, we handle specific values as invalid
1045 if (last_addr
<= new_addr
|| new_addr
== 0 ||
1046 last_addr
== PCI_BAR_UNMAPPED
) {
1047 return PCI_BAR_UNMAPPED
;
1050 /* Now pcibus_t is 64bit.
1051 * Check if 32 bit BAR wraps around explicitly.
1052 * Without this, PC ide doesn't work well.
1053 * TODO: remove this work around.
1055 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1056 return PCI_BAR_UNMAPPED
;
1060 * OS is allowed to set BAR beyond its addressable
1061 * bits. For example, 32 bit OS can set 64bit bar
1062 * to >4G. Check it. TODO: we might need to support
1063 * it in the future for e.g. PAE.
1065 if (last_addr
>= HWADDR_MAX
) {
1066 return PCI_BAR_UNMAPPED
;
1072 static void pci_update_mappings(PCIDevice
*d
)
1078 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1079 r
= &d
->io_regions
[i
];
1081 /* this region isn't registered */
1085 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1087 /* This bar isn't changed */
1088 if (new_addr
== r
->addr
)
1091 /* now do the real mapping */
1092 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1093 memory_region_del_subregion(r
->address_space
, r
->memory
);
1096 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1097 memory_region_add_subregion_overlap(r
->address_space
,
1098 r
->addr
, r
->memory
, 1);
1105 static inline int pci_irq_disabled(PCIDevice
*d
)
1107 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1110 /* Called after interrupt disabled field update in config space,
1111 * assert/deassert interrupts if necessary.
1112 * Gets original interrupt disable bit value (before update). */
1113 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1115 int i
, disabled
= pci_irq_disabled(d
);
1116 if (disabled
== was_irq_disabled
)
1118 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1119 int state
= pci_irq_state(d
, i
);
1120 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1124 uint32_t pci_default_read_config(PCIDevice
*d
,
1125 uint32_t address
, int len
)
1129 memcpy(&val
, d
->config
+ address
, len
);
1130 return le32_to_cpu(val
);
1133 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1135 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1137 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1138 uint8_t wmask
= d
->wmask
[addr
+ i
];
1139 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1140 assert(!(wmask
& w1cmask
));
1141 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1142 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1144 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1145 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1146 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1147 range_covers_byte(addr
, l
, PCI_COMMAND
))
1148 pci_update_mappings(d
);
1150 if (range_covers_byte(addr
, l
, PCI_COMMAND
)) {
1151 pci_update_irq_disabled(d
, was_irq_disabled
);
1152 memory_region_set_enabled(&d
->bus_master_enable_region
,
1153 pci_get_word(d
->config
+ PCI_COMMAND
)
1154 & PCI_COMMAND_MASTER
);
1157 msi_write_config(d
, addr
, val
, l
);
1158 msix_write_config(d
, addr
, val
, l
);
1161 /***********************************************************/
1162 /* generic PCI irq support */
1164 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1165 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1167 PCIDevice
*pci_dev
= opaque
;
1170 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1174 pci_set_irq_state(pci_dev
, irq_num
, level
);
1175 pci_update_irq_status(pci_dev
);
1176 if (pci_irq_disabled(pci_dev
))
1178 pci_change_irq_level(pci_dev
, irq_num
, change
);
1181 /* Special hooks used by device assignment */
1182 void pci_bus_set_route_irq_fn(PCIBus
*bus
, pci_route_irq_fn route_intx_to_irq
)
1184 assert(!bus
->parent_dev
);
1185 bus
->route_intx_to_irq
= route_intx_to_irq
;
1188 PCIINTxRoute
pci_device_route_intx_to_irq(PCIDevice
*dev
, int pin
)
1194 pin
= bus
->map_irq(dev
, pin
);
1195 dev
= bus
->parent_dev
;
1198 if (!bus
->route_intx_to_irq
) {
1199 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1200 object_get_typename(OBJECT(bus
->qbus
.parent
)));
1201 return (PCIINTxRoute
) { PCI_INTX_DISABLED
, -1 };
1204 return bus
->route_intx_to_irq(bus
->irq_opaque
, pin
);
1207 bool pci_intx_route_changed(PCIINTxRoute
*old
, PCIINTxRoute
*new)
1209 return old
->mode
!= new->mode
|| old
->irq
!= new->irq
;
1212 void pci_bus_fire_intx_routing_notifier(PCIBus
*bus
)
1218 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
1219 dev
= bus
->devices
[i
];
1220 if (dev
&& dev
->intx_routing_notifier
) {
1221 dev
->intx_routing_notifier(dev
);
1225 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1226 pci_bus_fire_intx_routing_notifier(sec
);
1230 void pci_device_set_intx_routing_notifier(PCIDevice
*dev
,
1231 PCIINTxRoutingNotifier notifier
)
1233 dev
->intx_routing_notifier
= notifier
;
1237 * PCI-to-PCI bridge specification
1238 * 9.1: Interrupt routing. Table 9-1
1240 * the PCI Express Base Specification, Revision 2.1
1241 * 2.2.8.1: INTx interrutp signaling - Rules
1242 * the Implementation Note
1246 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1247 * 0-origin unlike PCI interrupt pin register.
1249 int pci_swizzle_map_irq_fn(PCIDevice
*pci_dev
, int pin
)
1251 return (pin
+ PCI_SLOT(pci_dev
->devfn
)) % PCI_NUM_PINS
;
1254 /***********************************************************/
1255 /* monitor info on PCI */
1260 const char *fw_name
;
1261 uint16_t fw_ign_bits
;
1264 static const pci_class_desc pci_class_descriptions
[] =
1266 { 0x0001, "VGA controller", "display"},
1267 { 0x0100, "SCSI controller", "scsi"},
1268 { 0x0101, "IDE controller", "ide"},
1269 { 0x0102, "Floppy controller", "fdc"},
1270 { 0x0103, "IPI controller", "ipi"},
1271 { 0x0104, "RAID controller", "raid"},
1272 { 0x0106, "SATA controller"},
1273 { 0x0107, "SAS controller"},
1274 { 0x0180, "Storage controller"},
1275 { 0x0200, "Ethernet controller", "ethernet"},
1276 { 0x0201, "Token Ring controller", "token-ring"},
1277 { 0x0202, "FDDI controller", "fddi"},
1278 { 0x0203, "ATM controller", "atm"},
1279 { 0x0280, "Network controller"},
1280 { 0x0300, "VGA controller", "display", 0x00ff},
1281 { 0x0301, "XGA controller"},
1282 { 0x0302, "3D controller"},
1283 { 0x0380, "Display controller"},
1284 { 0x0400, "Video controller", "video"},
1285 { 0x0401, "Audio controller", "sound"},
1287 { 0x0403, "Audio controller", "sound"},
1288 { 0x0480, "Multimedia controller"},
1289 { 0x0500, "RAM controller", "memory"},
1290 { 0x0501, "Flash controller", "flash"},
1291 { 0x0580, "Memory controller"},
1292 { 0x0600, "Host bridge", "host"},
1293 { 0x0601, "ISA bridge", "isa"},
1294 { 0x0602, "EISA bridge", "eisa"},
1295 { 0x0603, "MC bridge", "mca"},
1296 { 0x0604, "PCI bridge", "pci"},
1297 { 0x0605, "PCMCIA bridge", "pcmcia"},
1298 { 0x0606, "NUBUS bridge", "nubus"},
1299 { 0x0607, "CARDBUS bridge", "cardbus"},
1300 { 0x0608, "RACEWAY bridge"},
1301 { 0x0680, "Bridge"},
1302 { 0x0700, "Serial port", "serial"},
1303 { 0x0701, "Parallel port", "parallel"},
1304 { 0x0800, "Interrupt controller", "interrupt-controller"},
1305 { 0x0801, "DMA controller", "dma-controller"},
1306 { 0x0802, "Timer", "timer"},
1307 { 0x0803, "RTC", "rtc"},
1308 { 0x0900, "Keyboard", "keyboard"},
1309 { 0x0901, "Pen", "pen"},
1310 { 0x0902, "Mouse", "mouse"},
1311 { 0x0A00, "Dock station", "dock", 0x00ff},
1312 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1313 { 0x0c00, "Fireware contorller", "fireware"},
1314 { 0x0c01, "Access bus controller", "access-bus"},
1315 { 0x0c02, "SSA controller", "ssa"},
1316 { 0x0c03, "USB controller", "usb"},
1317 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1322 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1323 void (*fn
)(PCIBus
*b
, PCIDevice
*d
,
1330 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1331 d
= bus
->devices
[devfn
];
1338 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1339 void (*fn
)(PCIBus
*b
, PCIDevice
*d
, void *opaque
),
1342 bus
= pci_find_bus_nr(bus
, bus_num
);
1345 pci_for_each_device_under_bus(bus
, fn
, opaque
);
1349 static const pci_class_desc
*get_class_desc(int class)
1351 const pci_class_desc
*desc
;
1353 desc
= pci_class_descriptions
;
1354 while (desc
->desc
&& class != desc
->class) {
1361 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1363 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1365 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1368 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1369 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1370 PciMemoryRegionList
*region
;
1376 region
= g_malloc0(sizeof(*region
));
1377 region
->value
= g_malloc0(sizeof(*region
->value
));
1379 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1380 region
->value
->type
= g_strdup("io");
1382 region
->value
->type
= g_strdup("memory");
1383 region
->value
->has_prefetch
= true;
1384 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1385 region
->value
->has_mem_type_64
= true;
1386 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1389 region
->value
->bar
= i
;
1390 region
->value
->address
= r
->addr
;
1391 region
->value
->size
= r
->size
;
1393 /* XXX: waiting for the qapi to support GSList */
1395 head
= cur_item
= region
;
1397 cur_item
->next
= region
;
1405 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1408 PciBridgeInfo
*info
;
1410 info
= g_malloc0(sizeof(*info
));
1412 info
->bus
.number
= dev
->config
[PCI_PRIMARY_BUS
];
1413 info
->bus
.secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1414 info
->bus
.subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1416 info
->bus
.io_range
= g_malloc0(sizeof(*info
->bus
.io_range
));
1417 info
->bus
.io_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1418 info
->bus
.io_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1420 info
->bus
.memory_range
= g_malloc0(sizeof(*info
->bus
.memory_range
));
1421 info
->bus
.memory_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1422 info
->bus
.memory_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1424 info
->bus
.prefetchable_range
= g_malloc0(sizeof(*info
->bus
.prefetchable_range
));
1425 info
->bus
.prefetchable_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1426 info
->bus
.prefetchable_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1428 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1429 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1431 info
->has_devices
= true;
1432 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1439 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1442 const pci_class_desc
*desc
;
1443 PciDeviceInfo
*info
;
1447 info
= g_malloc0(sizeof(*info
));
1448 info
->bus
= bus_num
;
1449 info
->slot
= PCI_SLOT(dev
->devfn
);
1450 info
->function
= PCI_FUNC(dev
->devfn
);
1452 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1453 info
->class_info
.class = class;
1454 desc
= get_class_desc(class);
1456 info
->class_info
.has_desc
= true;
1457 info
->class_info
.desc
= g_strdup(desc
->desc
);
1460 info
->id
.vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1461 info
->id
.device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1462 info
->regions
= qmp_query_pci_regions(dev
);
1463 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1465 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1466 info
->has_irq
= true;
1467 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1470 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1471 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1472 info
->has_pci_bridge
= true;
1473 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1479 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1481 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1485 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1486 dev
= bus
->devices
[devfn
];
1488 info
= g_malloc0(sizeof(*info
));
1489 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1491 /* XXX: waiting for the qapi to support GSList */
1493 head
= cur_item
= info
;
1495 cur_item
->next
= info
;
1504 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1506 PciInfo
*info
= NULL
;
1508 bus
= pci_find_bus_nr(bus
, bus_num
);
1510 info
= g_malloc0(sizeof(*info
));
1511 info
->bus
= bus_num
;
1512 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1518 PciInfoList
*qmp_query_pci(Error
**errp
)
1520 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1521 struct PCIHostBus
*host
;
1523 QLIST_FOREACH(host
, &host_buses
, next
) {
1524 info
= g_malloc0(sizeof(*info
));
1525 info
->value
= qmp_query_pci_bus(host
->bus
, 0);
1527 /* XXX: waiting for the qapi to support GSList */
1529 head
= cur_item
= info
;
1531 cur_item
->next
= info
;
1539 static const char * const pci_nic_models
[] = {
1551 static const char * const pci_nic_names
[] = {
1563 /* Initialize a PCI NIC. */
1564 /* FIXME callers should check for failure, but don't */
1565 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1566 const char *default_devaddr
)
1568 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1575 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1579 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1581 error_report("Invalid PCI device address %s for device %s",
1582 devaddr
, pci_nic_names
[i
]);
1586 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1587 dev
= &pci_dev
->qdev
;
1588 qdev_set_nic_properties(dev
, nd
);
1589 if (qdev_init(dev
) < 0)
1594 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1595 const char *default_devaddr
)
1599 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1602 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1608 PCIDevice
*pci_vga_init(PCIBus
*bus
)
1610 switch (vga_interface_type
) {
1612 return pci_create_simple(bus
, -1, "cirrus-vga");
1614 return pci_create_simple(bus
, -1, "qxl-vga");
1616 return pci_create_simple(bus
, -1, "VGA");
1618 return pci_create_simple(bus
, -1, "vmware-svga");
1620 default: /* Other non-PCI types. Checking for unsupported types is already
1626 /* Whether a given bus number is in range of the secondary
1627 * bus of the given bridge device. */
1628 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1630 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1631 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1632 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1633 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1636 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1644 if (pci_bus_num(bus
) == bus_num
) {
1648 /* Consider all bus numbers in range for the host pci bridge. */
1649 if (bus
->parent_dev
&&
1650 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1655 for (; bus
; bus
= sec
) {
1656 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1657 assert(sec
->parent_dev
);
1658 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1661 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1670 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1672 bus
= pci_find_bus_nr(bus
, bus_num
);
1677 return bus
->devices
[devfn
];
1680 static int pci_qdev_init(DeviceState
*qdev
)
1682 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1683 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1686 bool is_default_rom
;
1688 /* initialize cap_present for pci_is_express() and pci_config_size() */
1689 if (pc
->is_express
) {
1690 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1693 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1694 pci_dev
= do_pci_register_device(pci_dev
, bus
,
1695 object_get_typename(OBJECT(qdev
)),
1697 if (pci_dev
== NULL
)
1699 if (qdev
->hotplugged
&& pc
->no_hotplug
) {
1700 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(pci_dev
)));
1701 do_pci_unregister_device(pci_dev
);
1705 rc
= pc
->init(pci_dev
);
1707 do_pci_unregister_device(pci_dev
);
1713 is_default_rom
= false;
1714 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1715 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1716 is_default_rom
= true;
1718 pci_add_option_rom(pci_dev
, is_default_rom
);
1721 /* Let buses differentiate between hotplug and when device is
1722 * enabled during qemu machine creation. */
1723 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1724 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1725 PCI_COLDPLUG_ENABLED
);
1727 int r
= pci_unregister_device(&pci_dev
->qdev
);
1735 static int pci_unplug_device(DeviceState
*qdev
)
1737 PCIDevice
*dev
= PCI_DEVICE(qdev
);
1738 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1740 if (pc
->no_hotplug
) {
1741 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(dev
)));
1744 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1745 PCI_HOTPLUG_DISABLED
);
1748 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1753 dev
= qdev_create(&bus
->qbus
, name
);
1754 qdev_prop_set_int32(dev
, "addr", devfn
);
1755 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1756 return PCI_DEVICE(dev
);
1759 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1763 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1764 qdev_init_nofail(&dev
->qdev
);
1768 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1770 return pci_create_multifunction(bus
, devfn
, false, name
);
1773 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1775 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1778 static uint8_t pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1780 int offset
= PCI_CONFIG_HEADER_SIZE
;
1782 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
) {
1785 else if (i
- offset
+ 1 == size
)
1791 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1796 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1799 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1800 prev
= next
+ PCI_CAP_LIST_NEXT
)
1801 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1809 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1811 uint8_t next
, prev
, found
= 0;
1813 if (!(pdev
->used
[offset
])) {
1817 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1819 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1820 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1821 if (next
<= offset
&& next
> found
) {
1828 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1829 This is needed for an option rom which is used for more than one device. */
1830 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1834 uint16_t rom_vendor_id
;
1835 uint16_t rom_device_id
;
1837 uint16_t pcir_offset
;
1840 /* Words in rom data are little endian (like in PCI configuration),
1841 so they can be read / written with pci_get_word / pci_set_word. */
1843 /* Only a valid rom will be patched. */
1844 rom_magic
= pci_get_word(ptr
);
1845 if (rom_magic
!= 0xaa55) {
1846 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1849 pcir_offset
= pci_get_word(ptr
+ 0x18);
1850 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1851 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1855 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1856 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1857 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1858 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1860 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1861 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1865 if (vendor_id
!= rom_vendor_id
) {
1866 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1867 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1868 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1869 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1871 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1874 if (device_id
!= rom_device_id
) {
1875 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1876 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1877 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1878 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1880 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1884 /* Add an option rom for the device */
1885 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1891 const VMStateDescription
*vmsd
;
1895 if (strlen(pdev
->romfile
) == 0)
1898 if (!pdev
->rom_bar
) {
1900 * Load rom via fw_cfg instead of creating a rom bar,
1901 * for 0.11 compatibility.
1903 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1904 if (class == 0x0300) {
1905 rom_add_vga(pdev
->romfile
);
1907 rom_add_option(pdev
->romfile
, -1);
1912 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1914 path
= g_strdup(pdev
->romfile
);
1917 size
= get_image_size(path
);
1919 error_report("%s: failed to find romfile \"%s\"",
1920 __func__
, pdev
->romfile
);
1923 } else if (size
== 0) {
1924 error_report("%s: ignoring empty romfile \"%s\"",
1925 __func__
, pdev
->romfile
);
1929 if (size
& (size
- 1)) {
1930 size
= 1 << qemu_fls(size
);
1933 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
1936 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
1938 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
1940 pdev
->has_rom
= true;
1941 memory_region_init_ram(&pdev
->rom
, name
, size
);
1942 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
1943 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1944 load_image(path
, ptr
);
1947 if (is_default_rom
) {
1948 /* Only the default rom images will be patched (if needed). */
1949 pci_patch_ids(pdev
, ptr
, size
);
1952 qemu_put_ram_ptr(ptr
);
1954 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1959 static void pci_del_option_rom(PCIDevice
*pdev
)
1964 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
1965 memory_region_destroy(&pdev
->rom
);
1966 pdev
->has_rom
= false;
1971 * Reserve space and add capability to the linked list in pci config space
1974 * Find and reserve space and add capability to the linked list
1975 * in pci config space */
1976 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1977 uint8_t offset
, uint8_t size
)
1980 int i
, overlapping_cap
;
1983 offset
= pci_find_space(pdev
, size
);
1988 /* Verify that capabilities don't overlap. Note: device assignment
1989 * depends on this check to verify that the device is not broken.
1990 * Should never trigger for emulated devices, but it's helpful
1991 * for debugging these. */
1992 for (i
= offset
; i
< offset
+ size
; i
++) {
1993 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
1994 if (overlapping_cap
) {
1995 fprintf(stderr
, "ERROR: %04x:%02x:%02x.%x "
1996 "Attempt to add PCI capability %x at offset "
1997 "%x overlaps existing capability %x at offset %x\n",
1998 pci_find_domain(pdev
->bus
), pci_bus_num(pdev
->bus
),
1999 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
2000 cap_id
, offset
, overlapping_cap
, i
);
2006 config
= pdev
->config
+ offset
;
2007 config
[PCI_CAP_LIST_ID
] = cap_id
;
2008 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
2009 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
2010 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2011 memset(pdev
->used
+ offset
, 0xFF, QEMU_ALIGN_UP(size
, 4));
2012 /* Make capability read-only by default */
2013 memset(pdev
->wmask
+ offset
, 0, size
);
2014 /* Check capability by default */
2015 memset(pdev
->cmask
+ offset
, 0xFF, size
);
2019 /* Unlink capability from the pci config space. */
2020 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
2022 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
2025 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
2026 /* Make capability writable again */
2027 memset(pdev
->wmask
+ offset
, 0xff, size
);
2028 memset(pdev
->w1cmask
+ offset
, 0, size
);
2029 /* Clear cmask as device-specific registers can't be checked */
2030 memset(pdev
->cmask
+ offset
, 0, size
);
2031 memset(pdev
->used
+ offset
, 0, QEMU_ALIGN_UP(size
, 4));
2033 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
2034 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
2037 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
2039 return pci_find_capability_list(pdev
, cap_id
, NULL
);
2042 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
2044 PCIDevice
*d
= (PCIDevice
*)dev
;
2045 const pci_class_desc
*desc
;
2050 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2051 desc
= pci_class_descriptions
;
2052 while (desc
->desc
&& class != desc
->class)
2055 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
2057 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
2060 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
2061 "pci id %04x:%04x (sub %04x:%04x)\n",
2062 indent
, "", ctxt
, pci_bus_num(d
->bus
),
2063 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
2064 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2065 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
2066 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
2067 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
2068 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
2069 r
= &d
->io_regions
[i
];
2072 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2073 " [0x%"FMT_PCIBUS
"]\n",
2075 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
2076 r
->addr
, r
->addr
+ r
->size
- 1);
2080 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
2082 PCIDevice
*d
= (PCIDevice
*)dev
;
2083 const char *name
= NULL
;
2084 const pci_class_desc
*desc
= pci_class_descriptions
;
2085 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
2087 while (desc
->desc
&&
2088 (class & ~desc
->fw_ign_bits
) !=
2089 (desc
->class & ~desc
->fw_ign_bits
)) {
2094 name
= desc
->fw_name
;
2098 pstrcpy(buf
, len
, name
);
2100 snprintf(buf
, len
, "pci%04x,%04x",
2101 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
2102 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
2108 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
2110 PCIDevice
*d
= (PCIDevice
*)dev
;
2111 char path
[50], name
[33];
2114 off
= snprintf(path
, sizeof(path
), "%s@%x",
2115 pci_dev_fw_name(dev
, name
, sizeof name
),
2116 PCI_SLOT(d
->devfn
));
2117 if (PCI_FUNC(d
->devfn
))
2118 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
2119 return g_strdup(path
);
2122 static char *pcibus_get_dev_path(DeviceState
*dev
)
2124 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
2127 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2128 * 00 is added here to make this format compatible with
2129 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2130 * Slot.Function list specifies the slot and function numbers for all
2131 * devices on the path from root to the specific device. */
2132 char domain
[] = "DDDD:00";
2133 char slot
[] = ":SS.F";
2134 int domain_len
= sizeof domain
- 1 /* For '\0' */;
2135 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2140 /* Calculate # of slots on path between device and root. */;
2142 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2146 path_len
= domain_len
+ slot_len
* slot_depth
;
2148 /* Allocate memory, fill in the terminating null byte. */
2149 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2150 path
[path_len
] = '\0';
2152 /* First field is the domain. */
2153 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
2154 assert(s
== domain_len
);
2155 memcpy(path
, domain
, domain_len
);
2157 /* Fill in slot numbers. We walk up from device to root, so need to print
2158 * them in the reverse order, last to first. */
2159 p
= path
+ path_len
;
2160 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2162 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2163 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2164 assert(s
== slot_len
);
2165 memcpy(p
, slot
, slot_len
);
2171 static int pci_qdev_find_recursive(PCIBus
*bus
,
2172 const char *id
, PCIDevice
**pdev
)
2174 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2179 /* roughly check if given qdev is pci device */
2180 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
2181 *pdev
= PCI_DEVICE(qdev
);
2187 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2189 struct PCIHostBus
*host
;
2192 QLIST_FOREACH(host
, &host_buses
, next
) {
2193 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
2198 if (tmp
!= -ENODEV
) {
2206 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2208 return dev
->bus
->address_space_mem
;
2211 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2213 return dev
->bus
->address_space_io
;
2216 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
2218 DeviceClass
*k
= DEVICE_CLASS(klass
);
2219 k
->init
= pci_qdev_init
;
2220 k
->unplug
= pci_unplug_device
;
2221 k
->exit
= pci_unregister_device
;
2222 k
->bus_type
= TYPE_PCI_BUS
;
2223 k
->props
= pci_props
;
2226 void pci_setup_iommu(PCIBus
*bus
, PCIDMAContextFunc fn
, void *opaque
)
2228 bus
->dma_context_fn
= fn
;
2229 bus
->dma_context_opaque
= opaque
;
2232 static const TypeInfo pci_device_type_info
= {
2233 .name
= TYPE_PCI_DEVICE
,
2234 .parent
= TYPE_DEVICE
,
2235 .instance_size
= sizeof(PCIDevice
),
2237 .class_size
= sizeof(PCIDeviceClass
),
2238 .class_init
= pci_device_class_init
,
2241 static void pci_register_types(void)
2243 type_register_static(&pci_bus_info
);
2244 type_register_static(&pcie_bus_info
);
2245 type_register_static(&pci_device_type_info
);
2248 type_init(pci_register_types
)