hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "hw/qdev.h"
   7 #include "exec/memory.h"
   8 #include "sysemu/dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "hw/isa.h"
  12
  13 #include "hw/pci/pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "hw/pci/pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  80 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  81
  82 #define PCI_VENDOR_ID_REDHAT             0x1b36
  83 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  84 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  85 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  86 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  87 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
  88
  89 #define FMT_PCIBUS                      PRIx64
  90
  91 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  92                                 uint32_t address, uint32_t data, int len);
  93 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  94                                    uint32_t address, int len);
  95 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  96                                 pcibus_t addr, pcibus_t size, int type);
  97 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
  98
  99 typedef struct PCIIORegion {
 100     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 101 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 102     pcibus_t size;
 103     uint8_t type;
 104     MemoryRegion *memory;
 105     MemoryRegion *address_space;
 106 } PCIIORegion;
 107
 108 #define PCI_ROM_SLOT 6
 109 #define PCI_NUM_REGIONS 7
 110
 111 #include "hw/pci/pci_regs.h"
 112
 113 /* PCI HEADER_TYPE */
 114 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 115
 116 /* Size of the standard PCI config header */
 117 #define PCI_CONFIG_HEADER_SIZE 0x40
 118 /* Size of the standard PCI config space */
 119 #define PCI_CONFIG_SPACE_SIZE 0x100
 120 /* Size of the standart PCIe config space: 4KB */
 121 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 122
 123 #define PCI_NUM_PINS 4 /* A-D */
 124
 125 /* Bits in cap_present field. */
 126 enum {
 127     QEMU_PCI_CAP_MSI = 0x1,
 128     QEMU_PCI_CAP_MSIX = 0x2,
 129     QEMU_PCI_CAP_EXPRESS = 0x4,
 130
 131     /* multifunction capable device */
 132 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 133     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 134
 135     /* command register SERR bit enabled */
 136 #define QEMU_PCI_CAP_SERR_BITNR 4
 137     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 138     /* Standard hot plug controller. */
 139 #define QEMU_PCI_SHPC_BITNR 5
 140     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 141 #define QEMU_PCI_SLOTID_BITNR 6
 142     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 143 };
 144
 145 #define TYPE_PCI_DEVICE "pci-device"
 146 #define PCI_DEVICE(obj) \
 147      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 148 #define PCI_DEVICE_CLASS(klass) \
 149      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 150 #define PCI_DEVICE_GET_CLASS(obj) \
 151      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 152
 153 typedef struct PCIINTxRoute {
 154     enum {
 155         PCI_INTX_ENABLED,
 156         PCI_INTX_INVERTED,
 157         PCI_INTX_DISABLED,
 158     } mode;
 159     int irq;
 160 } PCIINTxRoute;
 161
 162 typedef struct PCIDeviceClass {
 163     DeviceClass parent_class;
 164
 165     int (*init)(PCIDevice *dev);
 166     PCIUnregisterFunc *exit;
 167     PCIConfigReadFunc *config_read;
 168     PCIConfigWriteFunc *config_write;
 169
 170     uint16_t vendor_id;
 171     uint16_t device_id;
 172     uint8_t revision;
 173     uint16_t class_id;
 174     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 175     uint16_t subsystem_id;              /* only for header type = 0 */
 176
 177     /*
 178      * pci-to-pci bridge or normal device.
 179      * This doesn't mean pci host switch.
 180      * When card bus bridge is supported, this would be enhanced.
 181      */
 182     int is_bridge;
 183
 184     /* pcie stuff */
 185     int is_express;   /* is this device pci express? */
 186
 187     /* device isn't hot-pluggable */
 188     int no_hotplug;
 189
 190     /* rom bar */
 191     const char *romfile;
 192 } PCIDeviceClass;
 193
 194 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 195 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 196                                       MSIMessage msg);
 197 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 198 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 199                                       unsigned int vector_start,
 200                                       unsigned int vector_end);
 201
 202 struct PCIDevice {
 203     DeviceState qdev;
 204
 205     /* PCI config space */
 206     uint8_t *config;
 207
 208     /* Used to enable config checks on load. Note that writable bits are
 209      * never checked even if set in cmask. */
 210     uint8_t *cmask;
 211
 212     /* Used to implement R/W bytes */
 213     uint8_t *wmask;
 214
 215     /* Used to implement RW1C(Write 1 to Clear) bytes */
 216     uint8_t *w1cmask;
 217
 218     /* Used to allocate config space for capabilities. */
 219     uint8_t *used;
 220
 221     /* the following fields are read only */
 222     PCIBus *bus;
 223     int32_t devfn;
 224     char name[64];
 225     PCIIORegion io_regions[PCI_NUM_REGIONS];
 226     AddressSpace bus_master_as;
 227     MemoryRegion bus_master_enable_region;
 228     DMAContext *dma;
 229
 230     /* do not access the following fields */
 231     PCIConfigReadFunc *config_read;
 232     PCIConfigWriteFunc *config_write;
 233
 234     /* IRQ objects for the INTA-INTD pins.  */
 235     qemu_irq *irq;
 236
 237     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 238     uint8_t irq_state;
 239
 240     /* Capability bits */
 241     uint32_t cap_present;
 242
 243     /* Offset of MSI-X capability in config space */
 244     uint8_t msix_cap;
 245
 246     /* MSI-X entries */
 247     int msix_entries_nr;
 248
 249     /* Space to store MSIX table & pending bit array */
 250     uint8_t *msix_table;
 251     uint8_t *msix_pba;
 252     /* MemoryRegion container for msix exclusive BAR setup */
 253     MemoryRegion msix_exclusive_bar;
 254     /* Memory Regions for MSIX table and pending bit entries. */
 255     MemoryRegion msix_table_mmio;
 256     MemoryRegion msix_pba_mmio;
 257     /* Reference-count for entries actually in use by driver. */
 258     unsigned *msix_entry_used;
 259     /* MSIX function mask set or MSIX disabled */
 260     bool msix_function_masked;
 261     /* Version id needed for VMState */
 262     int32_t version_id;
 263
 264     /* Offset of MSI capability in config space */
 265     uint8_t msi_cap;
 266
 267     /* PCI Express */
 268     PCIExpressDevice exp;
 269
 270     /* SHPC */
 271     SHPCDevice *shpc;
 272
 273     /* Location of option rom */
 274     char *romfile;
 275     bool has_rom;
 276     MemoryRegion rom;
 277     uint32_t rom_bar;
 278
 279     /* INTx routing notifier */
 280     PCIINTxRoutingNotifier intx_routing_notifier;
 281
 282     /* MSI-X notifiers */
 283     MSIVectorUseNotifier msix_vector_use_notifier;
 284     MSIVectorReleaseNotifier msix_vector_release_notifier;
 285     MSIVectorPollNotifier msix_vector_poll_notifier;
 286 };
 287
 288 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 289                       uint8_t attr, MemoryRegion *memory);
 290 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 291
 292 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 293                        uint8_t offset, uint8_t size);
 294
 295 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 296
 297 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 298
 299
 300 uint32_t pci_default_read_config(PCIDevice *d,
 301                                  uint32_t address, int len);
 302 void pci_default_write_config(PCIDevice *d,
 303                               uint32_t address, uint32_t val, int len);
 304 void pci_device_save(PCIDevice *s, QEMUFile *f);
 305 int pci_device_load(PCIDevice *s, QEMUFile *f);
 306 MemoryRegion *pci_address_space(PCIDevice *dev);
 307 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 308
 309 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 310 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 311 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 312
 313 typedef enum {
 314     PCI_HOTPLUG_DISABLED,
 315     PCI_HOTPLUG_ENABLED,
 316     PCI_COLDPLUG_ENABLED,
 317 } PCIHotplugState;
 318
 319 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 320                               PCIHotplugState state);
 321 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 322                          const char *name,
 323                          MemoryRegion *address_space_mem,
 324                          MemoryRegion *address_space_io,
 325                          uint8_t devfn_min);
 326 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 327                     MemoryRegion *address_space_mem,
 328                     MemoryRegion *address_space_io,
 329                     uint8_t devfn_min);
 330 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 331                   void *irq_opaque, int nirq);
 332 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 333 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 334 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 335 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 336 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 337                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 338                          void *irq_opaque,
 339                          MemoryRegion *address_space_mem,
 340                          MemoryRegion *address_space_io,
 341                          uint8_t devfn_min, int nirq);
 342 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 343 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 344 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 345 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 346 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 347                                           PCIINTxRoutingNotifier notifier);
 348 void pci_device_reset(PCIDevice *dev);
 349 void pci_bus_reset(PCIBus *bus);
 350
 351 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 352                         const char *default_devaddr);
 353 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 354                                const char *default_devaddr);
 355
 356 PCIDevice *pci_vga_init(PCIBus *bus);
 357
 358 int pci_bus_num(PCIBus *s);
 359 void pci_for_each_device(PCIBus *bus, int bus_num,
 360                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 361                          void *opaque);
 362 PCIBus *pci_find_root_bus(int domain);
 363 int pci_find_domain(const PCIBus *bus);
 364 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 365 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 366 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 367
 368 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 369                      unsigned *slotp);
 370
 371 void pci_device_deassert_intx(PCIDevice *dev);
 372
 373 typedef DMAContext *(*PCIDMAContextFunc)(PCIBus *, void *, int);
 374
 375 void pci_setup_iommu(PCIBus *bus, PCIDMAContextFunc fn, void *opaque);
 376
 377 static inline void
 378 pci_set_byte(uint8_t *config, uint8_t val)
 379 {
 380     *config = val;
 381 }
 382
 383 static inline uint8_t
 384 pci_get_byte(const uint8_t *config)
 385 {
 386     return *config;
 387 }
 388
 389 static inline void
 390 pci_set_word(uint8_t *config, uint16_t val)
 391 {
 392     cpu_to_le16wu((uint16_t *)config, val);
 393 }
 394
 395 static inline uint16_t
 396 pci_get_word(const uint8_t *config)
 397 {
 398     return le16_to_cpupu((const uint16_t *)config);
 399 }
 400
 401 static inline void
 402 pci_set_long(uint8_t *config, uint32_t val)
 403 {
 404     cpu_to_le32wu((uint32_t *)config, val);
 405 }
 406
 407 static inline uint32_t
 408 pci_get_long(const uint8_t *config)
 409 {
 410     return le32_to_cpupu((const uint32_t *)config);
 411 }
 412
 413 static inline void
 414 pci_set_quad(uint8_t *config, uint64_t val)
 415 {
 416     cpu_to_le64w((uint64_t *)config, val);
 417 }
 418
 419 static inline uint64_t
 420 pci_get_quad(const uint8_t *config)
 421 {
 422     return le64_to_cpup((const uint64_t *)config);
 423 }
 424
 425 static inline void
 426 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 427 {
 428     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 429 }
 430
 431 static inline void
 432 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 433 {
 434     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 435 }
 436
 437 static inline void
 438 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 439 {
 440     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 441 }
 442
 443 static inline void
 444 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 445 {
 446     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 447 }
 448
 449 static inline void
 450 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 451 {
 452     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 453 }
 454
 455 static inline void
 456 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 457 {
 458     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 459 }
 460
 461 /*
 462  * helper functions to do bit mask operation on configuration space.
 463  * Just to set bit, use test-and-set and discard returned value.
 464  * Just to clear bit, use test-and-clear and discard returned value.
 465  * NOTE: They aren't atomic.
 466  */
 467 static inline uint8_t
 468 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 469 {
 470     uint8_t val = pci_get_byte(config);
 471     pci_set_byte(config, val & ~mask);
 472     return val & mask;
 473 }
 474
 475 static inline uint8_t
 476 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 477 {
 478     uint8_t val = pci_get_byte(config);
 479     pci_set_byte(config, val | mask);
 480     return val & mask;
 481 }
 482
 483 static inline uint16_t
 484 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 485 {
 486     uint16_t val = pci_get_word(config);
 487     pci_set_word(config, val & ~mask);
 488     return val & mask;
 489 }
 490
 491 static inline uint16_t
 492 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 493 {
 494     uint16_t val = pci_get_word(config);
 495     pci_set_word(config, val | mask);
 496     return val & mask;
 497 }
 498
 499 static inline uint32_t
 500 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 501 {
 502     uint32_t val = pci_get_long(config);
 503     pci_set_long(config, val & ~mask);
 504     return val & mask;
 505 }
 506
 507 static inline uint32_t
 508 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 509 {
 510     uint32_t val = pci_get_long(config);
 511     pci_set_long(config, val | mask);
 512     return val & mask;
 513 }
 514
 515 static inline uint64_t
 516 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 517 {
 518     uint64_t val = pci_get_quad(config);
 519     pci_set_quad(config, val & ~mask);
 520     return val & mask;
 521 }
 522
 523 static inline uint64_t
 524 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 525 {
 526     uint64_t val = pci_get_quad(config);
 527     pci_set_quad(config, val | mask);
 528     return val & mask;
 529 }
 530
 531 /* Access a register specified by a mask */
 532 static inline void
 533 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 534 {
 535     uint8_t val = pci_get_byte(config);
 536     uint8_t rval = reg << (ffs(mask) - 1);
 537     pci_set_byte(config, (~mask & val) | (mask & rval));
 538 }
 539
 540 static inline uint8_t
 541 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 542 {
 543     uint8_t val = pci_get_byte(config);
 544     return (val & mask) >> (ffs(mask) - 1);
 545 }
 546
 547 static inline void
 548 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 549 {
 550     uint16_t val = pci_get_word(config);
 551     uint16_t rval = reg << (ffs(mask) - 1);
 552     pci_set_word(config, (~mask & val) | (mask & rval));
 553 }
 554
 555 static inline uint16_t
 556 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 557 {
 558     uint16_t val = pci_get_word(config);
 559     return (val & mask) >> (ffs(mask) - 1);
 560 }
 561
 562 static inline void
 563 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 564 {
 565     uint32_t val = pci_get_long(config);
 566     uint32_t rval = reg << (ffs(mask) - 1);
 567     pci_set_long(config, (~mask & val) | (mask & rval));
 568 }
 569
 570 static inline uint32_t
 571 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 572 {
 573     uint32_t val = pci_get_long(config);
 574     return (val & mask) >> (ffs(mask) - 1);
 575 }
 576
 577 static inline void
 578 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 579 {
 580     uint64_t val = pci_get_quad(config);
 581     uint64_t rval = reg << (ffs(mask) - 1);
 582     pci_set_quad(config, (~mask & val) | (mask & rval));
 583 }
 584
 585 static inline uint64_t
 586 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 587 {
 588     uint64_t val = pci_get_quad(config);
 589     return (val & mask) >> (ffs(mask) - 1);
 590 }
 591
 592 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 593                                     const char *name);
 594 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 595                                            bool multifunction,
 596                                            const char *name);
 597 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 598 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 599
 600 static inline int pci_is_express(const PCIDevice *d)
 601 {
 602     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 603 }
 604
 605 static inline uint32_t pci_config_size(const PCIDevice *d)
 606 {
 607     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 608 }
 609
 610 /* DMA access functions */
 611 static inline DMAContext *pci_dma_context(PCIDevice *dev)
 612 {
 613     return dev->dma;
 614 }
 615
 616 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 617                              void *buf, dma_addr_t len, DMADirection dir)
 618 {
 619     dma_memory_rw(pci_dma_context(dev), addr, buf, len, dir);
 620     return 0;
 621 }
 622
 623 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 624                                void *buf, dma_addr_t len)
 625 {
 626     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 627 }
 628
 629 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 630                                 const void *buf, dma_addr_t len)
 631 {
 632     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 633 }
 634
 635 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 636     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 637                                                    dma_addr_t addr)     \
 638     {                                                                   \
 639         return ld##_l##_dma(pci_dma_context(dev), addr);                \
 640     }                                                                   \
 641     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 642                                         dma_addr_t addr, uint##_bits##_t val) \
 643     {                                                                   \
 644         st##_s##_dma(pci_dma_context(dev), addr, val);                  \
 645     }
 646
 647 PCI_DMA_DEFINE_LDST(ub, b, 8);
 648 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 649 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 650 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 651 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 652 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 653 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 654
 655 #undef PCI_DMA_DEFINE_LDST
 656
 657 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 658                                 dma_addr_t *plen, DMADirection dir)
 659 {
 660     void *buf;
 661
 662     buf = dma_memory_map(pci_dma_context(dev), addr, plen, dir);
 663     return buf;
 664 }
 665
 666 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 667                                  DMADirection dir, dma_addr_t access_len)
 668 {
 669     dma_memory_unmap(pci_dma_context(dev), buffer, len, dir, access_len);
 670 }
 671
 672 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 673                                        int alloc_hint)
 674 {
 675     qemu_sglist_init(qsg, alloc_hint, pci_dma_context(dev));
 676 }
 677
 678 extern const VMStateDescription vmstate_pci_device;
 679
 680 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 681     .name       = (stringify(_field)),                               \
 682     .size       = sizeof(PCIDevice),                                 \
 683     .vmsd       = &vmstate_pci_device,                               \
 684     .flags      = VMS_STRUCT,                                        \
 685     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 686 }
 687
 688 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 689     .name       = (stringify(_field)),                               \
 690     .size       = sizeof(PCIDevice),                                 \
 691     .vmsd       = &vmstate_pci_device,                               \
 692     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 693     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 694 }
 695
 696 #endif