4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
5 * VA Linux Systems Japan K.K.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
22 #include "hw/pci/pci_bridge.h"
23 #include "hw/pci/pcie.h"
24 #include "hw/pci/msix.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/pci_bus.h"
27 #include "hw/pci/pcie_regs.h"
28 #include "qemu/range.h"
32 # define PCIE_DPRINTF(fmt, ...) \
33 fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
35 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
37 #define PCIE_DEV_PRINTF(dev, fmt, ...) \
38 PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
41 /***************************************************************************
42 * pci express capability helper functions
44 int pcie_cap_init(PCIDevice
*dev
, uint8_t offset
, uint8_t type
, uint8_t port
)
49 assert(pci_is_express(dev
));
51 pos
= pci_add_capability(dev
, PCI_CAP_ID_EXP
, offset
,
56 dev
->exp
.exp_cap
= pos
;
57 exp_cap
= dev
->config
+ pos
;
59 /* capability register
60 interrupt message number defaults to 0 */
61 pci_set_word(exp_cap
+ PCI_EXP_FLAGS
,
62 ((type
<< PCI_EXP_FLAGS_TYPE_SHIFT
) & PCI_EXP_FLAGS_TYPE
) |
65 /* device capability register
67 * roll based error reporting bit must be set by all
68 * Functions conforming to the ECN, PCI Express Base
69 * Specification, Revision 1.1., or subsequent PCI Express Base
70 * Specification revisions.
72 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP
, PCI_EXP_DEVCAP_RBER
);
74 pci_set_long(exp_cap
+ PCI_EXP_LNKCAP
,
75 (port
<< PCI_EXP_LNKCAP_PN_SHIFT
) |
76 PCI_EXP_LNKCAP_ASPMS_0S
|
80 pci_set_word(exp_cap
+ PCI_EXP_LNKSTA
,
81 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
);
83 pci_set_long(exp_cap
+ PCI_EXP_DEVCAP2
,
84 PCI_EXP_DEVCAP2_EFF
| PCI_EXP_DEVCAP2_EETLPP
);
86 pci_set_word(dev
->wmask
+ pos
, PCI_EXP_DEVCTL2_EETLPPB
);
90 int pcie_endpoint_cap_init(PCIDevice
*dev
, uint8_t offset
)
92 uint8_t type
= PCI_EXP_TYPE_ENDPOINT
;
95 * Windows guests will report Code 10, device cannot start, if
96 * a regular Endpoint type is exposed on a root complex. These
97 * should instead be Root Complex Integrated Endpoints.
99 if (pci_bus_is_express(dev
->bus
) && pci_bus_is_root(dev
->bus
)) {
100 type
= PCI_EXP_TYPE_RC_END
;
103 return pcie_cap_init(dev
, offset
, type
, 0);
106 void pcie_cap_exit(PCIDevice
*dev
)
108 pci_del_capability(dev
, PCI_CAP_ID_EXP
, PCI_EXP_VER2_SIZEOF
);
111 uint8_t pcie_cap_get_type(const PCIDevice
*dev
)
113 uint32_t pos
= dev
->exp
.exp_cap
;
115 return (pci_get_word(dev
->config
+ pos
+ PCI_EXP_FLAGS
) &
116 PCI_EXP_FLAGS_TYPE
) >> PCI_EXP_FLAGS_TYPE_SHIFT
;
120 /* pci express interrupt message number */
121 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
122 void pcie_cap_flags_set_vector(PCIDevice
*dev
, uint8_t vector
)
124 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
126 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_FLAGS
, PCI_EXP_FLAGS_IRQ
);
127 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_FLAGS
,
128 vector
<< PCI_EXP_FLAGS_IRQ_SHIFT
);
131 uint8_t pcie_cap_flags_get_vector(PCIDevice
*dev
)
133 return (pci_get_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_FLAGS
) &
134 PCI_EXP_FLAGS_IRQ
) >> PCI_EXP_FLAGS_IRQ_SHIFT
;
137 void pcie_cap_deverr_init(PCIDevice
*dev
)
139 uint32_t pos
= dev
->exp
.exp_cap
;
140 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP
,
141 PCI_EXP_DEVCAP_RBER
);
142 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
,
143 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
144 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
145 pci_long_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_DEVSTA
,
146 PCI_EXP_DEVSTA_CED
| PCI_EXP_DEVSTA_NFED
|
147 PCI_EXP_DEVSTA_URD
| PCI_EXP_DEVSTA_URD
);
150 void pcie_cap_deverr_reset(PCIDevice
*dev
)
152 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
153 pci_long_test_and_clear_mask(devctl
,
154 PCI_EXP_DEVCTL_CERE
| PCI_EXP_DEVCTL_NFERE
|
155 PCI_EXP_DEVCTL_FERE
| PCI_EXP_DEVCTL_URRE
);
158 static void hotplug_event_update_event_status(PCIDevice
*dev
)
160 uint32_t pos
= dev
->exp
.exp_cap
;
161 uint8_t *exp_cap
= dev
->config
+ pos
;
162 uint16_t sltctl
= pci_get_word(exp_cap
+ PCI_EXP_SLTCTL
);
163 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
165 dev
->exp
.hpev_notified
= (sltctl
& PCI_EXP_SLTCTL_HPIE
) &&
166 (sltsta
& sltctl
& PCI_EXP_HP_EV_SUPPORTED
);
169 static void hotplug_event_notify(PCIDevice
*dev
)
171 bool prev
= dev
->exp
.hpev_notified
;
173 hotplug_event_update_event_status(dev
);
175 if (prev
== dev
->exp
.hpev_notified
) {
179 /* Note: the logic above does not take into account whether interrupts
180 * are masked. The result is that interrupt will be sent when it is
181 * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
182 * The Port may optionally send an MSI when there are hot-plug events that
183 * occur while interrupt generation is disabled, and interrupt generation is
184 * subsequently enabled. */
185 if (msix_enabled(dev
)) {
186 msix_notify(dev
, pcie_cap_flags_get_vector(dev
));
187 } else if (msi_enabled(dev
)) {
188 msi_notify(dev
, pcie_cap_flags_get_vector(dev
));
190 pci_set_irq(dev
, dev
->exp
.hpev_notified
);
194 static void hotplug_event_clear(PCIDevice
*dev
)
196 hotplug_event_update_event_status(dev
);
197 if (!msix_enabled(dev
) && !msi_enabled(dev
) && !dev
->exp
.hpev_notified
) {
198 pci_irq_deassert(dev
);
203 * A PCI Express Hot-Plug Event has occurred, so update slot status register
204 * and notify OS of the event if necessary.
206 * 6.7.3 PCI Express Hot-Plug Events
207 * 6.7.3.4 Software Notification of Hot-Plug Events
209 static void pcie_cap_slot_event(PCIDevice
*dev
, PCIExpressHotPlugEvent event
)
211 /* Minor optimization: if nothing changed - no event is needed. */
212 if (pci_word_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+
213 PCI_EXP_SLTSTA
, event
)) {
216 hotplug_event_notify(dev
);
219 static int pcie_cap_slot_hotplug(DeviceState
*qdev
,
220 PCIDevice
*pci_dev
, PCIHotplugState state
)
222 PCIDevice
*d
= PCI_DEVICE(qdev
);
223 uint8_t *exp_cap
= d
->config
+ d
->exp
.exp_cap
;
224 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
226 /* Don't send event when device is enabled during qemu machine creation:
227 * it is present on boot, no hotplug event is necessary. We do send an
228 * event when the device is disabled later. */
229 if (state
== PCI_COLDPLUG_ENABLED
) {
230 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
235 PCIE_DEV_PRINTF(pci_dev
, "hotplug state: %d\n", state
);
236 if (sltsta
& PCI_EXP_SLTSTA_EIS
) {
237 /* the slot is electromechanically locked.
238 * This error is propagated up to qdev and then to HMP/QMP.
243 /* TODO: multifunction hot-plug.
244 * Right now, only a device of function = 0 is allowed to be
245 * hot plugged/unplugged.
247 assert(PCI_FUNC(pci_dev
->devfn
) == 0);
249 if (state
== PCI_HOTPLUG_ENABLED
) {
250 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTSTA
,
252 pcie_cap_slot_event(d
, PCI_EXP_HP_EV_PDC
);
254 qdev_free(&pci_dev
->qdev
);
255 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
257 pcie_cap_slot_event(d
, PCI_EXP_HP_EV_PDC
);
262 /* pci express slot for pci express root/downstream port
263 PCI express capability slot registers */
264 void pcie_cap_slot_init(PCIDevice
*dev
, uint16_t slot
)
266 uint32_t pos
= dev
->exp
.exp_cap
;
268 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_FLAGS
,
271 pci_long_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
272 ~PCI_EXP_SLTCAP_PSN
);
273 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCAP
,
274 (slot
<< PCI_EXP_SLTCAP_PSN_SHIFT
) |
282 pci_word_test_and_clear_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
285 pci_word_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_SLTCTL
,
286 PCI_EXP_SLTCTL_PIC_OFF
|
287 PCI_EXP_SLTCTL_AIC_OFF
);
288 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
291 PCI_EXP_SLTCTL_HPIE
|
292 PCI_EXP_SLTCTL_CCIE
|
293 PCI_EXP_SLTCTL_PDCE
|
294 PCI_EXP_SLTCTL_ABPE
);
295 /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
296 * make the bit writable here in order to detect 1b is written.
297 * pcie_cap_slot_write_config() test-and-clear the bit, so
298 * this bit always returns 0 to the guest.
300 pci_word_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_SLTCTL
,
303 pci_word_test_and_set_mask(dev
->w1cmask
+ pos
+ PCI_EXP_SLTSTA
,
304 PCI_EXP_HP_EV_SUPPORTED
);
306 dev
->exp
.hpev_notified
= false;
308 pci_bus_hotplug(pci_bridge_get_sec_bus(PCI_BRIDGE(dev
)),
309 pcie_cap_slot_hotplug
, &dev
->qdev
);
312 void pcie_cap_slot_reset(PCIDevice
*dev
)
314 uint8_t *exp_cap
= dev
->config
+ dev
->exp
.exp_cap
;
316 PCIE_DEV_PRINTF(dev
, "reset\n");
318 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
322 PCI_EXP_SLTCTL_HPIE
|
323 PCI_EXP_SLTCTL_CCIE
|
324 PCI_EXP_SLTCTL_PDCE
|
325 PCI_EXP_SLTCTL_ABPE
);
326 pci_word_test_and_set_mask(exp_cap
+ PCI_EXP_SLTCTL
,
327 PCI_EXP_SLTCTL_PIC_OFF
|
328 PCI_EXP_SLTCTL_AIC_OFF
);
330 pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTSTA
,
331 PCI_EXP_SLTSTA_EIS
|/* on reset,
332 the lock is released */
337 hotplug_event_update_event_status(dev
);
340 void pcie_cap_slot_write_config(PCIDevice
*dev
,
341 uint32_t addr
, uint32_t val
, int len
)
343 uint32_t pos
= dev
->exp
.exp_cap
;
344 uint8_t *exp_cap
= dev
->config
+ pos
;
345 uint16_t sltsta
= pci_get_word(exp_cap
+ PCI_EXP_SLTSTA
);
347 if (ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTSTA
, 2)) {
348 hotplug_event_clear(dev
);
351 if (!ranges_overlap(addr
, len
, pos
+ PCI_EXP_SLTCTL
, 2)) {
355 if (pci_word_test_and_clear_mask(exp_cap
+ PCI_EXP_SLTCTL
,
356 PCI_EXP_SLTCTL_EIC
)) {
357 sltsta
^= PCI_EXP_SLTSTA_EIS
; /* toggle PCI_EXP_SLTSTA_EIS bit */
358 pci_set_word(exp_cap
+ PCI_EXP_SLTSTA
, sltsta
);
359 PCIE_DEV_PRINTF(dev
, "PCI_EXP_SLTCTL_EIC: "
360 "sltsta -> 0x%02"PRIx16
"\n",
364 hotplug_event_notify(dev
);
367 * 6.7.3.2 Command Completed Events
369 * Software issues a command to a hot-plug capable Downstream Port by
370 * issuing a write transaction that targets any portion of the Port’s Slot
371 * Control register. A single write to the Slot Control register is
372 * considered to be a single command, even if the write affects more than
373 * one field in the Slot Control register. In response to this transaction,
374 * the Port must carry out the requested actions and then set the
375 * associated status field for the command completed event. */
377 /* Real hardware might take a while to complete requested command because
378 * physical movement would be involved like locking the electromechanical
379 * lock. However in our case, command is completed instantaneously above,
380 * so send a command completion event right now.
382 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_CCI
);
385 int pcie_cap_slot_post_load(void *opaque
, int version_id
)
387 PCIDevice
*dev
= opaque
;
388 hotplug_event_update_event_status(dev
);
392 void pcie_cap_slot_push_attention_button(PCIDevice
*dev
)
394 pcie_cap_slot_event(dev
, PCI_EXP_HP_EV_ABP
);
397 /* root control/capabilities/status. PME isn't emulated for now */
398 void pcie_cap_root_init(PCIDevice
*dev
)
400 pci_set_word(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
,
401 PCI_EXP_RTCTL_SECEE
| PCI_EXP_RTCTL_SENFEE
|
402 PCI_EXP_RTCTL_SEFEE
);
405 void pcie_cap_root_reset(PCIDevice
*dev
)
407 pci_set_word(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_RTCTL
, 0);
410 /* function level reset(FLR) */
411 void pcie_cap_flr_init(PCIDevice
*dev
)
413 pci_long_test_and_set_mask(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCAP
,
416 /* Although reading BCR_FLR returns always 0,
417 * the bit is made writable here in order to detect the 1b is written
418 * pcie_cap_flr_write_config() test-and-clear the bit, so
419 * this bit always returns 0 to the guest.
421 pci_word_test_and_set_mask(dev
->wmask
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
,
422 PCI_EXP_DEVCTL_BCR_FLR
);
425 void pcie_cap_flr_write_config(PCIDevice
*dev
,
426 uint32_t addr
, uint32_t val
, int len
)
428 uint8_t *devctl
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL
;
429 if (pci_get_word(devctl
) & PCI_EXP_DEVCTL_BCR_FLR
) {
430 /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
431 so the handler can detect FLR by looking at this bit. */
432 pci_device_reset(dev
);
433 pci_word_test_and_clear_mask(devctl
, PCI_EXP_DEVCTL_BCR_FLR
);
437 /* Alternative Routing-ID Interpretation (ARI) */
438 /* ari forwarding support for down stream port */
439 void pcie_cap_ari_init(PCIDevice
*dev
)
441 uint32_t pos
= dev
->exp
.exp_cap
;
442 pci_long_test_and_set_mask(dev
->config
+ pos
+ PCI_EXP_DEVCAP2
,
443 PCI_EXP_DEVCAP2_ARI
);
444 pci_long_test_and_set_mask(dev
->wmask
+ pos
+ PCI_EXP_DEVCTL2
,
445 PCI_EXP_DEVCTL2_ARI
);
448 void pcie_cap_ari_reset(PCIDevice
*dev
)
450 uint8_t *devctl2
= dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
;
451 pci_long_test_and_clear_mask(devctl2
, PCI_EXP_DEVCTL2_ARI
);
454 bool pcie_cap_is_ari_enabled(const PCIDevice
*dev
)
456 if (!pci_is_express(dev
)) {
459 if (!dev
->exp
.exp_cap
) {
463 return pci_get_long(dev
->config
+ dev
->exp
.exp_cap
+ PCI_EXP_DEVCTL2
) &
467 /**************************************************************************
468 * pci express extended capability allocation functions
469 * uint16_t ext_cap_id (16 bit)
470 * uint8_t cap_ver (4 bit)
471 * uint16_t cap_offset (12 bit)
472 * uint16_t ext_cap_size
475 static uint16_t pcie_find_capability_list(PCIDevice
*dev
, uint16_t cap_id
,
480 uint32_t header
= pci_get_long(dev
->config
+ PCI_CONFIG_SPACE_SIZE
);
483 /* no extended capability */
487 for (next
= PCI_CONFIG_SPACE_SIZE
; next
;
488 prev
= next
, next
= PCI_EXT_CAP_NEXT(header
)) {
490 assert(next
>= PCI_CONFIG_SPACE_SIZE
);
491 assert(next
<= PCIE_CONFIG_SPACE_SIZE
- 8);
493 header
= pci_get_long(dev
->config
+ next
);
494 if (PCI_EXT_CAP_ID(header
) == cap_id
) {
506 uint16_t pcie_find_capability(PCIDevice
*dev
, uint16_t cap_id
)
508 return pcie_find_capability_list(dev
, cap_id
, NULL
);
511 static void pcie_ext_cap_set_next(PCIDevice
*dev
, uint16_t pos
, uint16_t next
)
513 uint32_t header
= pci_get_long(dev
->config
+ pos
);
514 assert(!(next
& (PCI_EXT_CAP_ALIGN
- 1)));
515 header
= (header
& ~PCI_EXT_CAP_NEXT_MASK
) |
516 ((next
<< PCI_EXT_CAP_NEXT_SHIFT
) & PCI_EXT_CAP_NEXT_MASK
);
517 pci_set_long(dev
->config
+ pos
, header
);
521 * caller must supply valid (offset, size) * such that the range shouldn't
522 * overlap with other capability or other registers.
523 * This function doesn't check it.
525 void pcie_add_capability(PCIDevice
*dev
,
526 uint16_t cap_id
, uint8_t cap_ver
,
527 uint16_t offset
, uint16_t size
)
532 assert(offset
>= PCI_CONFIG_SPACE_SIZE
);
533 assert(offset
< offset
+ size
);
534 assert(offset
+ size
< PCIE_CONFIG_SPACE_SIZE
);
536 assert(pci_is_express(dev
));
538 if (offset
== PCI_CONFIG_SPACE_SIZE
) {
539 header
= pci_get_long(dev
->config
+ offset
);
540 next
= PCI_EXT_CAP_NEXT(header
);
544 /* 0 is reserved cap id. use internally to find the last capability
545 in the linked list */
546 next
= pcie_find_capability_list(dev
, 0, &prev
);
548 assert(prev
>= PCI_CONFIG_SPACE_SIZE
);
550 pcie_ext_cap_set_next(dev
, prev
, offset
);
552 pci_set_long(dev
->config
+ offset
, PCI_EXT_CAP(cap_id
, cap_ver
, next
));
554 /* Make capability read-only by default */
555 memset(dev
->wmask
+ offset
, 0, size
);
556 memset(dev
->w1cmask
+ offset
, 0, size
);
557 /* Check capability by default */
558 memset(dev
->cmask
+ offset
, 0xFF, size
);
561 /**************************************************************************
562 * pci express extended capability helper functions
566 void pcie_ari_init(PCIDevice
*dev
, uint16_t offset
, uint16_t nextfn
)
568 pcie_add_capability(dev
, PCI_EXT_CAP_ID_ARI
, PCI_ARI_VER
,
569 offset
, PCI_ARI_SIZEOF
);
570 pci_set_long(dev
->config
+ offset
+ PCI_ARI_CAP
, PCI_ARI_CAP_NFN(nextfn
));