hw/pci/pcie_port.c

   1 /*
   2  * pcie_port.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "hw/pci/pcie_port.h"
  22
  23 void pcie_port_init_reg(PCIDevice *d)
  24 {
  25     /* Unlike pci bridge,
  26        66MHz and fast back to back don't apply to pci express port. */
  27     pci_set_word(d->config + PCI_STATUS, 0);
  28     pci_set_word(d->config + PCI_SEC_STATUS, 0);
  29
  30     /*
  31      * Unlike conventional pci bridge, for some bits the spec states:
  32      * Does not apply to PCI Express and must be hardwired to 0.
  33      */
  34     pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL,
  35                                  PCI_BRIDGE_CTL_MASTER_ABORT |
  36                                  PCI_BRIDGE_CTL_FAST_BACK |
  37                                  PCI_BRIDGE_CTL_DISCARD |
  38                                  PCI_BRIDGE_CTL_SEC_DISCARD |
  39                                  PCI_BRIDGE_CTL_DISCARD_STATUS |
  40                                  PCI_BRIDGE_CTL_DISCARD_SERR);
  41 }
  42
  43 /**************************************************************************
  44  * (chassis number, pcie physical slot number) -> pcie slot conversion
  45  */
  46 struct PCIEChassis {
  47     uint8_t     number;
  48
  49     QLIST_HEAD(, PCIESlot) slots;
  50     QLIST_ENTRY(PCIEChassis) next;
  51 };
  52
  53 static QLIST_HEAD(, PCIEChassis) chassis = QLIST_HEAD_INITIALIZER(chassis);
  54
  55 static struct PCIEChassis *pcie_chassis_find(uint8_t chassis_number)
  56 {
  57     struct PCIEChassis *c;
  58     QLIST_FOREACH(c, &chassis, next) {
  59         if (c->number == chassis_number) {
  60             break;
  61         }
  62     }
  63     return c;
  64 }
  65
  66 void pcie_chassis_create(uint8_t chassis_number)
  67 {
  68     struct PCIEChassis *c;
  69     c = pcie_chassis_find(chassis_number);
  70     if (c) {
  71         return;
  72     }
  73     c = g_malloc0(sizeof(*c));
  74     c->number = chassis_number;
  75     QLIST_INIT(&c->slots);
  76     QLIST_INSERT_HEAD(&chassis, c, next);
  77 }
  78
  79 static PCIESlot *pcie_chassis_find_slot_with_chassis(struct PCIEChassis *c,
  80                                                      uint8_t slot)
  81 {
  82     PCIESlot *s;
  83     QLIST_FOREACH(s, &c->slots, next) {
  84         if (s->slot == slot) {
  85             break;
  86         }
  87     }
  88     return s;
  89 }
  90
  91 PCIESlot *pcie_chassis_find_slot(uint8_t chassis_number, uint16_t slot)
  92 {
  93     struct PCIEChassis *c;
  94     c = pcie_chassis_find(chassis_number);
  95     if (!c) {
  96         return NULL;
  97     }
  98     return pcie_chassis_find_slot_with_chassis(c, slot);
  99 }
 100
 101 int pcie_chassis_add_slot(struct PCIESlot *slot)
 102 {
 103     struct PCIEChassis *c;
 104     c = pcie_chassis_find(slot->chassis);
 105     if (!c) {
 106         return -ENODEV;
 107     }
 108     if (pcie_chassis_find_slot_with_chassis(c, slot->slot)) {
 109         return -EBUSY;
 110     }
 111     QLIST_INSERT_HEAD(&c->slots, slot, next);
 112     return 0;
 113 }
 114
 115 void pcie_chassis_del_slot(PCIESlot *s)
 116 {
 117     QLIST_REMOVE(s, next);
 118 }
 119
 120 static Property pcie_port_props[] = {
 121     DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
 122     DEFINE_PROP_UINT16("aer_log_max", PCIEPort,
 123                        parent_obj.parent_obj.exp.aer_log.log_max,
 124                        PCIE_AER_LOG_MAX_DEFAULT),
 125     DEFINE_PROP_END_OF_LIST()
 126 };
 127
 128 static void pcie_port_class_init(ObjectClass *oc, void *data)
 129 {
 130     DeviceClass *dc = DEVICE_CLASS(oc);
 131
 132     dc->props = pcie_port_props;
 133 }
 134
 135 static const TypeInfo pcie_port_type_info = {
 136     .name = TYPE_PCIE_PORT,
 137     .parent = TYPE_PCI_BRIDGE,
 138     .instance_size = sizeof(PCIEPort),
 139     .abstract = true,
 140     .class_init = pcie_port_class_init,
 141 };
 142
 143 static Property pcie_slot_props[] = {
 144     DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 145     DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 146     DEFINE_PROP_END_OF_LIST()
 147 };
 148
 149 static void pcie_slot_class_init(ObjectClass *oc, void *data)
 150 {
 151     DeviceClass *dc = DEVICE_CLASS(oc);
 152
 153     dc->props = pcie_slot_props;
 154 }
 155
 156 static const TypeInfo pcie_slot_type_info = {
 157     .name = TYPE_PCIE_SLOT,
 158     .parent = TYPE_PCIE_PORT,
 159     .instance_size = sizeof(PCIESlot),
 160     .abstract = true,
 161     .class_init = pcie_slot_class_init,
 162 };
 163
 164 static void pcie_port_register_types(void)
 165 {
 166     type_register_static(&pcie_port_type_info);
 167     type_register_static(&pcie_slot_type_info);
 168 }
 169
 170 type_init(pcie_port_register_types)