1 #include "qemu-common.h"
4 #include "qemu/range.h"
5 #include "qemu/error-report.h"
6 #include "hw/pci/shpc.h"
7 #include "hw/pci/pci.h"
8 #include "hw/pci/pci_bus.h"
9 #include "hw/pci/msi.h"
11 /* TODO: model power only and disabled slot states. */
12 /* TODO: handle SERR and wakeups */
13 /* TODO: consider enabling 66MHz support */
15 /* TODO: remove fully only on state DISABLED and LED off.
16 * track state to properly record this. */
18 /* SHPC Working Register Set */
19 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
20 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
21 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */
22 #define SHPC_NSLOTS 0x0C /* 1 byte */
23 #define SHPC_FIRST_DEV 0x0D /* 1 byte */
24 #define SHPC_PHYS_SLOT 0x0E /* 2 byte */
25 #define SHPC_PHYS_NUM_MAX 0x7ff
26 #define SHPC_PHYS_NUM_UP 0x2000
27 #define SHPC_PHYS_MRL 0x4000
28 #define SHPC_PHYS_BUTTON 0x8000
29 #define SHPC_SEC_BUS 0x10 /* 2 bytes */
30 #define SHPC_SEC_BUS_33 0x0
31 #define SHPC_SEC_BUS_66 0x1 /* Unused */
32 #define SHPC_SEC_BUS_MASK 0x7
33 #define SHPC_MSI_CTL 0x12 /* 1 byte */
34 #define SHPC_PROG_IFC 0x13 /* 1 byte */
35 #define SHPC_PROG_IFC_1_0 0x1
36 #define SHPC_CMD_CODE 0x14 /* 1 byte */
37 #define SHPC_CMD_TRGT 0x15 /* 1 byte */
38 #define SHPC_CMD_TRGT_MIN 0x1
39 #define SHPC_CMD_TRGT_MAX 0x1f
40 #define SHPC_CMD_STATUS 0x16 /* 2 bytes */
41 #define SHPC_CMD_STATUS_BUSY 0x1
42 #define SHPC_CMD_STATUS_MRL_OPEN 0x2
43 #define SHPC_CMD_STATUS_INVALID_CMD 0x4
44 #define SHPC_CMD_STATUS_INVALID_MODE 0x8
45 #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
46 #define SHPC_INT_COMMAND 0x1
47 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
48 #define SHPC_SERR_INT 0x20 /* 4 bytes */
49 #define SHPC_INT_DIS 0x1
50 #define SHPC_SERR_DIS 0x2
51 #define SHPC_CMD_INT_DIS 0x4
52 #define SHPC_ARB_SERR_DIS 0x8
53 #define SHPC_CMD_DETECTED 0x10000
54 #define SHPC_ARB_DETECTED 0x20000
55 /* 4 bytes * slot # (start from 0) */
56 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
58 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
60 /* Same slot state masks are used for command and status registers */
61 #define SHPC_SLOT_STATE_MASK 0x03
62 #define SHPC_SLOT_STATE_SHIFT \
63 (ffs(SHPC_SLOT_STATE_MASK) - 1)
65 #define SHPC_STATE_NO 0x0
66 #define SHPC_STATE_PWRONLY 0x1
67 #define SHPC_STATE_ENABLED 0x2
68 #define SHPC_STATE_DISABLED 0x3
70 #define SHPC_SLOT_PWR_LED_MASK 0xC
71 #define SHPC_SLOT_PWR_LED_SHIFT \
72 (ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
73 #define SHPC_SLOT_ATTN_LED_MASK 0x30
74 #define SHPC_SLOT_ATTN_LED_SHIFT \
75 (ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
77 #define SHPC_LED_NO 0x0
78 #define SHPC_LED_ON 0x1
79 #define SHPC_LED_BLINK 0x2
80 #define SHPC_LED_OFF 0x3
82 #define SHPC_SLOT_STATUS_PWR_FAULT 0x40
83 #define SHPC_SLOT_STATUS_BUTTON 0x80
84 #define SHPC_SLOT_STATUS_MRL_OPEN 0x100
85 #define SHPC_SLOT_STATUS_66 0x200
86 #define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
87 #define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
88 #define SHPC_SLOT_STATUS_PRSNT_25W 0x1
89 #define SHPC_SLOT_STATUS_PRSNT_15W 0x2
90 #define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
92 #define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
96 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
98 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
99 #define SHPC_SLOT_EVENT_PRESENCE 0x01
100 #define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
101 #define SHPC_SLOT_EVENT_BUTTON 0x04
102 #define SHPC_SLOT_EVENT_MRL 0x08
103 #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
104 /* Bits below are used for Serr/Int disable only */
105 #define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
106 #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
108 #define SHPC_MIN_SLOTS 1
109 #define SHPC_MAX_SLOTS 31
110 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
112 /* SHPC Slot identifiers */
114 /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
115 and give the rest of them physical *and* pci numbers starting from 1, so
116 they match logical numbers. Note: this means that multiple slots must have
117 different chassis number values, to make chassis+physical slot unique.
118 TODO: make this configurable? */
119 #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
120 #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
121 #define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
122 #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
123 #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
125 static int roundup_pow_of_two(int x
)
135 static uint16_t shpc_get_status(SHPCDevice
*shpc
, int slot
, uint16_t msk
)
137 uint8_t *status
= shpc
->config
+ SHPC_SLOT_STATUS(slot
);
138 return (pci_get_word(status
) & msk
) >> (ffs(msk
) - 1);
141 static void shpc_set_status(SHPCDevice
*shpc
,
142 int slot
, uint8_t value
, uint16_t msk
)
144 uint8_t *status
= shpc
->config
+ SHPC_SLOT_STATUS(slot
);
145 pci_word_test_and_clear_mask(status
, msk
);
146 pci_word_test_and_set_mask(status
, value
<< (ffs(msk
) - 1));
149 static void shpc_interrupt_update(PCIDevice
*d
)
151 SHPCDevice
*shpc
= d
->shpc
;
155 uint32_t int_locator
= 0;
157 /* Update interrupt locator register */
158 for (slot
= 0; slot
< shpc
->nslots
; ++slot
) {
159 uint8_t event
= shpc
->config
[SHPC_SLOT_EVENT_LATCH(slot
)];
160 uint8_t disable
= shpc
->config
[SHPC_SLOT_EVENT_SERR_INT_DIS(d
, slot
)];
161 uint32_t mask
= 1 << SHPC_IDX_TO_LOGICAL(slot
);
162 if (event
& ~disable
) {
166 serr_int
= pci_get_long(shpc
->config
+ SHPC_SERR_INT
);
167 if ((serr_int
& SHPC_CMD_DETECTED
) && !(serr_int
& SHPC_CMD_INT_DIS
)) {
168 int_locator
|= SHPC_INT_COMMAND
;
170 pci_set_long(shpc
->config
+ SHPC_INT_LOCATOR
, int_locator
);
171 level
= (!(serr_int
& SHPC_INT_DIS
) && int_locator
) ? 1 : 0;
172 if (msi_enabled(d
) && shpc
->msi_requested
!= level
)
175 pci_set_irq(d
, level
);
176 shpc
->msi_requested
= level
;
179 static void shpc_set_sec_bus_speed(SHPCDevice
*shpc
, uint8_t speed
)
182 case SHPC_SEC_BUS_33
:
183 shpc
->config
[SHPC_SEC_BUS
] &= ~SHPC_SEC_BUS_MASK
;
184 shpc
->config
[SHPC_SEC_BUS
] |= speed
;
187 pci_word_test_and_set_mask(shpc
->config
+ SHPC_CMD_STATUS
,
188 SHPC_CMD_STATUS_INVALID_MODE
);
192 void shpc_reset(PCIDevice
*d
)
194 SHPCDevice
*shpc
= d
->shpc
;
195 int nslots
= shpc
->nslots
;
197 memset(shpc
->config
, 0, SHPC_SIZEOF(d
));
198 pci_set_byte(shpc
->config
+ SHPC_NSLOTS
, nslots
);
199 pci_set_long(shpc
->config
+ SHPC_SLOTS_33
, nslots
);
200 pci_set_long(shpc
->config
+ SHPC_SLOTS_66
, 0);
201 pci_set_byte(shpc
->config
+ SHPC_FIRST_DEV
, SHPC_IDX_TO_PCI(0));
202 pci_set_word(shpc
->config
+ SHPC_PHYS_SLOT
,
203 SHPC_IDX_TO_PHYSICAL(0) |
207 pci_set_long(shpc
->config
+ SHPC_SERR_INT
, SHPC_INT_DIS
|
211 pci_set_byte(shpc
->config
+ SHPC_PROG_IFC
, SHPC_PROG_IFC_1_0
);
212 pci_set_word(shpc
->config
+ SHPC_SEC_BUS
, SHPC_SEC_BUS_33
);
213 for (i
= 0; i
< shpc
->nslots
; ++i
) {
214 pci_set_byte(shpc
->config
+ SHPC_SLOT_EVENT_SERR_INT_DIS(d
, i
),
215 SHPC_SLOT_EVENT_PRESENCE
|
216 SHPC_SLOT_EVENT_ISOLATED_FAULT
|
217 SHPC_SLOT_EVENT_BUTTON
|
218 SHPC_SLOT_EVENT_MRL
|
219 SHPC_SLOT_EVENT_CONNECTED_FAULT
|
220 SHPC_SLOT_EVENT_MRL_SERR_DIS
|
221 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS
);
222 if (shpc
->sec_bus
->devices
[PCI_DEVFN(SHPC_IDX_TO_PCI(i
), 0)]) {
223 shpc_set_status(shpc
, i
, SHPC_STATE_ENABLED
, SHPC_SLOT_STATE_MASK
);
224 shpc_set_status(shpc
, i
, 0, SHPC_SLOT_STATUS_MRL_OPEN
);
225 shpc_set_status(shpc
, i
, SHPC_SLOT_STATUS_PRSNT_7_5W
,
226 SHPC_SLOT_STATUS_PRSNT_MASK
);
227 shpc_set_status(shpc
, i
, SHPC_LED_ON
, SHPC_SLOT_PWR_LED_MASK
);
229 shpc_set_status(shpc
, i
, SHPC_STATE_DISABLED
, SHPC_SLOT_STATE_MASK
);
230 shpc_set_status(shpc
, i
, 1, SHPC_SLOT_STATUS_MRL_OPEN
);
231 shpc_set_status(shpc
, i
, SHPC_SLOT_STATUS_PRSNT_EMPTY
,
232 SHPC_SLOT_STATUS_PRSNT_MASK
);
233 shpc_set_status(shpc
, i
, SHPC_LED_OFF
, SHPC_SLOT_PWR_LED_MASK
);
235 shpc_set_status(shpc
, i
, 0, SHPC_SLOT_STATUS_66
);
237 shpc_set_sec_bus_speed(shpc
, SHPC_SEC_BUS_33
);
238 shpc
->msi_requested
= 0;
239 shpc_interrupt_update(d
);
242 static void shpc_invalid_command(SHPCDevice
*shpc
)
244 pci_word_test_and_set_mask(shpc
->config
+ SHPC_CMD_STATUS
,
245 SHPC_CMD_STATUS_INVALID_CMD
);
248 static void shpc_free_devices_in_slot(SHPCDevice
*shpc
, int slot
)
251 int pci_slot
= SHPC_IDX_TO_PCI(slot
);
252 for (devfn
= PCI_DEVFN(pci_slot
, 0);
253 devfn
<= PCI_DEVFN(pci_slot
, PCI_FUNC_MAX
- 1);
255 PCIDevice
*affected_dev
= shpc
->sec_bus
->devices
[devfn
];
257 qdev_free(&affected_dev
->qdev
);
262 static void shpc_slot_command(SHPCDevice
*shpc
, uint8_t target
,
263 uint8_t state
, uint8_t power
, uint8_t attn
)
265 uint8_t current_state
;
266 int slot
= SHPC_LOGICAL_TO_IDX(target
);
267 if (target
< SHPC_CMD_TRGT_MIN
|| slot
>= shpc
->nslots
) {
268 shpc_invalid_command(shpc
);
271 current_state
= shpc_get_status(shpc
, slot
, SHPC_SLOT_STATE_MASK
);
272 if (current_state
== SHPC_STATE_ENABLED
&& state
== SHPC_STATE_PWRONLY
) {
273 shpc_invalid_command(shpc
);
281 /* TODO: send event to monitor */
282 shpc_set_status(shpc
, slot
, power
, SHPC_SLOT_PWR_LED_MASK
);
288 /* TODO: send event to monitor */
289 shpc_set_status(shpc
, slot
, attn
, SHPC_SLOT_ATTN_LED_MASK
);
292 if ((current_state
== SHPC_STATE_DISABLED
&& state
== SHPC_STATE_PWRONLY
) ||
293 (current_state
== SHPC_STATE_DISABLED
&& state
== SHPC_STATE_ENABLED
)) {
294 shpc_set_status(shpc
, slot
, state
, SHPC_SLOT_STATE_MASK
);
295 } else if ((current_state
== SHPC_STATE_ENABLED
||
296 current_state
== SHPC_STATE_PWRONLY
) &&
297 state
== SHPC_STATE_DISABLED
) {
298 shpc_set_status(shpc
, slot
, state
, SHPC_SLOT_STATE_MASK
);
299 power
= shpc_get_status(shpc
, slot
, SHPC_SLOT_PWR_LED_MASK
);
300 /* TODO: track what monitor requested. */
301 /* Look at LED to figure out whether it's ok to remove the device. */
302 if (power
== SHPC_LED_OFF
) {
303 shpc_free_devices_in_slot(shpc
, slot
);
304 shpc_set_status(shpc
, slot
, 1, SHPC_SLOT_STATUS_MRL_OPEN
);
305 shpc_set_status(shpc
, slot
, SHPC_SLOT_STATUS_PRSNT_EMPTY
,
306 SHPC_SLOT_STATUS_PRSNT_MASK
);
307 shpc
->config
[SHPC_SLOT_EVENT_LATCH(slot
)] |=
308 SHPC_SLOT_EVENT_BUTTON
|
309 SHPC_SLOT_EVENT_MRL
|
310 SHPC_SLOT_EVENT_PRESENCE
;
315 static void shpc_command(SHPCDevice
*shpc
)
317 uint8_t code
= pci_get_byte(shpc
->config
+ SHPC_CMD_CODE
);
325 /* Clear status from the previous command. */
326 pci_word_test_and_clear_mask(shpc
->config
+ SHPC_CMD_STATUS
,
327 SHPC_CMD_STATUS_BUSY
|
328 SHPC_CMD_STATUS_MRL_OPEN
|
329 SHPC_CMD_STATUS_INVALID_CMD
|
330 SHPC_CMD_STATUS_INVALID_MODE
);
333 target
= shpc
->config
[SHPC_CMD_TRGT
] & SHPC_CMD_TRGT_MAX
;
334 state
= (code
& SHPC_SLOT_STATE_MASK
) >> SHPC_SLOT_STATE_SHIFT
;
335 power
= (code
& SHPC_SLOT_PWR_LED_MASK
) >> SHPC_SLOT_PWR_LED_SHIFT
;
336 attn
= (code
& SHPC_SLOT_ATTN_LED_MASK
) >> SHPC_SLOT_ATTN_LED_SHIFT
;
337 shpc_slot_command(shpc
, target
, state
, power
, attn
);
340 speed
= code
& SHPC_SEC_BUS_MASK
;
341 shpc_set_sec_bus_speed(shpc
, speed
);
344 /* Power only all slots */
345 /* first verify no slots are enabled */
346 for (i
= 0; i
< shpc
->nslots
; ++i
) {
347 state
= shpc_get_status(shpc
, i
, SHPC_SLOT_STATE_MASK
);
348 if (state
== SHPC_STATE_ENABLED
) {
349 shpc_invalid_command(shpc
);
353 for (i
= 0; i
< shpc
->nslots
; ++i
) {
354 if (!(shpc_get_status(shpc
, i
, SHPC_SLOT_STATUS_MRL_OPEN
))) {
355 shpc_slot_command(shpc
, i
+ SHPC_CMD_TRGT_MIN
,
356 SHPC_STATE_PWRONLY
, SHPC_LED_ON
, SHPC_LED_NO
);
358 shpc_slot_command(shpc
, i
+ SHPC_CMD_TRGT_MIN
,
359 SHPC_STATE_NO
, SHPC_LED_OFF
, SHPC_LED_NO
);
364 /* Enable all slots */
365 /* TODO: Spec says this shall fail if some are already enabled.
366 * This doesn't make sense - why not? a spec bug? */
367 for (i
= 0; i
< shpc
->nslots
; ++i
) {
368 state
= shpc_get_status(shpc
, i
, SHPC_SLOT_STATE_MASK
);
369 if (state
== SHPC_STATE_ENABLED
) {
370 shpc_invalid_command(shpc
);
374 for (i
= 0; i
< shpc
->nslots
; ++i
) {
375 if (!(shpc_get_status(shpc
, i
, SHPC_SLOT_STATUS_MRL_OPEN
))) {
376 shpc_slot_command(shpc
, i
+ SHPC_CMD_TRGT_MIN
,
377 SHPC_STATE_ENABLED
, SHPC_LED_ON
, SHPC_LED_NO
);
379 shpc_slot_command(shpc
, i
+ SHPC_CMD_TRGT_MIN
,
380 SHPC_STATE_NO
, SHPC_LED_OFF
, SHPC_LED_NO
);
385 shpc_invalid_command(shpc
);
389 pci_long_test_and_set_mask(shpc
->config
+ SHPC_SERR_INT
, SHPC_CMD_DETECTED
);
392 static void shpc_write(PCIDevice
*d
, unsigned addr
, uint64_t val
, int l
)
394 SHPCDevice
*shpc
= d
->shpc
;
396 if (addr
>= SHPC_SIZEOF(d
)) {
399 l
= MIN(l
, SHPC_SIZEOF(d
) - addr
);
401 /* TODO: code duplicated from pci.c */
402 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
403 unsigned a
= addr
+ i
;
404 uint8_t wmask
= shpc
->wmask
[a
];
405 uint8_t w1cmask
= shpc
->w1cmask
[a
];
406 assert(!(wmask
& w1cmask
));
407 shpc
->config
[a
] = (shpc
->config
[a
] & ~wmask
) | (val
& wmask
);
408 shpc
->config
[a
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
410 if (ranges_overlap(addr
, l
, SHPC_CMD_CODE
, 2)) {
413 shpc_interrupt_update(d
);
416 static uint64_t shpc_read(PCIDevice
*d
, unsigned addr
, int l
)
419 if (addr
>= SHPC_SIZEOF(d
)) {
422 l
= MIN(l
, SHPC_SIZEOF(d
) - addr
);
423 memcpy(&val
, d
->shpc
->config
+ addr
, l
);
427 /* SHPC Bridge Capability */
428 #define SHPC_CAP_LENGTH 0x08
429 #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
430 #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
431 #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
432 #define SHPC_CAP_CSP_MASK 0x4
433 #define SHPC_CAP_CIP_MASK 0x8
435 static uint8_t shpc_cap_dword(PCIDevice
*d
)
437 return pci_get_byte(d
->config
+ d
->shpc
->cap
+ SHPC_CAP_DWORD_SELECT
);
440 /* Update dword data capability register */
441 static void shpc_cap_update_dword(PCIDevice
*d
)
444 data
= shpc_read(d
, shpc_cap_dword(d
) * 4, 4);
445 pci_set_long(d
->config
+ d
->shpc
->cap
+ SHPC_CAP_DWORD_DATA
, data
);
448 /* Add SHPC capability to the config space for the device. */
449 static int shpc_cap_add_config(PCIDevice
*d
)
453 config_offset
= pci_add_capability(d
, PCI_CAP_ID_SHPC
,
455 if (config_offset
< 0) {
456 return config_offset
;
458 config
= d
->config
+ config_offset
;
460 pci_set_byte(config
+ SHPC_CAP_DWORD_SELECT
, 0);
461 pci_set_byte(config
+ SHPC_CAP_CxP
, 0);
462 pci_set_long(config
+ SHPC_CAP_DWORD_DATA
, 0);
463 d
->shpc
->cap
= config_offset
;
464 /* Make dword select and data writeable. */
465 pci_set_byte(d
->wmask
+ config_offset
+ SHPC_CAP_DWORD_SELECT
, 0xff);
466 pci_set_long(d
->wmask
+ config_offset
+ SHPC_CAP_DWORD_DATA
, 0xffffffff);
470 static uint64_t shpc_mmio_read(void *opaque
, hwaddr addr
,
473 return shpc_read(opaque
, addr
, size
);
476 static void shpc_mmio_write(void *opaque
, hwaddr addr
,
477 uint64_t val
, unsigned size
)
479 shpc_write(opaque
, addr
, val
, size
);
482 static const MemoryRegionOps shpc_mmio_ops
= {
483 .read
= shpc_mmio_read
,
484 .write
= shpc_mmio_write
,
485 .endianness
= DEVICE_LITTLE_ENDIAN
,
487 /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
488 * It's easier to suppport all sizes than worry about it. */
489 .min_access_size
= 1,
490 .max_access_size
= 4,
494 static int shpc_device_hotplug(DeviceState
*qdev
, PCIDevice
*affected_dev
,
495 PCIHotplugState hotplug_state
)
497 int pci_slot
= PCI_SLOT(affected_dev
->devfn
);
500 PCIDevice
*d
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
501 SHPCDevice
*shpc
= d
->shpc
;
502 int slot
= SHPC_PCI_TO_IDX(pci_slot
);
503 if (pci_slot
< SHPC_IDX_TO_PCI(0) || slot
>= shpc
->nslots
) {
504 error_report("Unsupported PCI slot %d for standard hotplug "
505 "controller. Valid slots are between %d and %d.",
506 pci_slot
, SHPC_IDX_TO_PCI(0),
507 SHPC_IDX_TO_PCI(shpc
->nslots
) - 1);
510 /* Don't send event when device is enabled during qemu machine creation:
511 * it is present on boot, no hotplug event is necessary. We do send an
512 * event when the device is disabled later. */
513 if (hotplug_state
== PCI_COLDPLUG_ENABLED
) {
514 shpc_set_status(shpc
, slot
, 0, SHPC_SLOT_STATUS_MRL_OPEN
);
515 shpc_set_status(shpc
, slot
, SHPC_SLOT_STATUS_PRSNT_7_5W
,
516 SHPC_SLOT_STATUS_PRSNT_MASK
);
519 if (hotplug_state
== PCI_HOTPLUG_DISABLED
) {
520 shpc
->config
[SHPC_SLOT_EVENT_LATCH(slot
)] |= SHPC_SLOT_EVENT_BUTTON
;
521 state
= shpc_get_status(shpc
, slot
, SHPC_SLOT_STATE_MASK
);
522 led
= shpc_get_status(shpc
, slot
, SHPC_SLOT_PWR_LED_MASK
);
523 if (state
== SHPC_STATE_DISABLED
&& led
== SHPC_LED_OFF
) {
524 shpc_free_devices_in_slot(shpc
, slot
);
525 shpc_set_status(shpc
, slot
, 1, SHPC_SLOT_STATUS_MRL_OPEN
);
526 shpc_set_status(shpc
, slot
, SHPC_SLOT_STATUS_PRSNT_EMPTY
,
527 SHPC_SLOT_STATUS_PRSNT_MASK
);
528 shpc
->config
[SHPC_SLOT_EVENT_LATCH(slot
)] |=
529 SHPC_SLOT_EVENT_MRL
|
530 SHPC_SLOT_EVENT_PRESENCE
;
533 /* This could be a cancellation of the previous removal.
534 * We check MRL state to figure out. */
535 if (shpc_get_status(shpc
, slot
, SHPC_SLOT_STATUS_MRL_OPEN
)) {
536 shpc_set_status(shpc
, slot
, 0, SHPC_SLOT_STATUS_MRL_OPEN
);
537 shpc_set_status(shpc
, slot
, SHPC_SLOT_STATUS_PRSNT_7_5W
,
538 SHPC_SLOT_STATUS_PRSNT_MASK
);
539 shpc
->config
[SHPC_SLOT_EVENT_LATCH(slot
)] |=
540 SHPC_SLOT_EVENT_BUTTON
|
541 SHPC_SLOT_EVENT_MRL
|
542 SHPC_SLOT_EVENT_PRESENCE
;
544 /* Press attention button to cancel removal */
545 shpc
->config
[SHPC_SLOT_EVENT_LATCH(slot
)] |=
546 SHPC_SLOT_EVENT_BUTTON
;
549 shpc_set_status(shpc
, slot
, 0, SHPC_SLOT_STATUS_66
);
550 shpc_interrupt_update(d
);
554 /* Initialize the SHPC structure in bridge's BAR. */
555 int shpc_init(PCIDevice
*d
, PCIBus
*sec_bus
, MemoryRegion
*bar
, unsigned offset
)
558 int nslots
= SHPC_MAX_SLOTS
; /* TODO: qdev property? */
559 SHPCDevice
*shpc
= d
->shpc
= g_malloc0(sizeof(*d
->shpc
));
560 shpc
->sec_bus
= sec_bus
;
561 ret
= shpc_cap_add_config(d
);
566 if (nslots
< SHPC_MIN_SLOTS
) {
569 if (nslots
> SHPC_MAX_SLOTS
||
570 SHPC_IDX_TO_PCI(nslots
) > PCI_SLOT_MAX
) {
571 /* TODO: report an error mesage that makes sense. */
574 shpc
->nslots
= nslots
;
575 shpc
->config
= g_malloc0(SHPC_SIZEOF(d
));
576 shpc
->cmask
= g_malloc0(SHPC_SIZEOF(d
));
577 shpc
->wmask
= g_malloc0(SHPC_SIZEOF(d
));
578 shpc
->w1cmask
= g_malloc0(SHPC_SIZEOF(d
));
582 pci_set_long(shpc
->config
+ SHPC_BASE_OFFSET
, offset
);
584 pci_set_byte(shpc
->wmask
+ SHPC_CMD_CODE
, 0xff);
585 pci_set_byte(shpc
->wmask
+ SHPC_CMD_TRGT
, SHPC_CMD_TRGT_MAX
);
586 pci_set_byte(shpc
->wmask
+ SHPC_CMD_TRGT
, SHPC_CMD_TRGT_MAX
);
587 pci_set_long(shpc
->wmask
+ SHPC_SERR_INT
,
592 pci_set_long(shpc
->w1cmask
+ SHPC_SERR_INT
,
595 for (i
= 0; i
< nslots
; ++i
) {
596 pci_set_byte(shpc
->wmask
+
597 SHPC_SLOT_EVENT_SERR_INT_DIS(d
, i
),
598 SHPC_SLOT_EVENT_PRESENCE
|
599 SHPC_SLOT_EVENT_ISOLATED_FAULT
|
600 SHPC_SLOT_EVENT_BUTTON
|
601 SHPC_SLOT_EVENT_MRL
|
602 SHPC_SLOT_EVENT_CONNECTED_FAULT
|
603 SHPC_SLOT_EVENT_MRL_SERR_DIS
|
604 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS
);
605 pci_set_byte(shpc
->w1cmask
+
606 SHPC_SLOT_EVENT_LATCH(i
),
607 SHPC_SLOT_EVENT_PRESENCE
|
608 SHPC_SLOT_EVENT_ISOLATED_FAULT
|
609 SHPC_SLOT_EVENT_BUTTON
|
610 SHPC_SLOT_EVENT_MRL
|
611 SHPC_SLOT_EVENT_CONNECTED_FAULT
);
614 /* TODO: init cmask */
615 memory_region_init_io(&shpc
->mmio
, OBJECT(d
), &shpc_mmio_ops
,
616 d
, "shpc-mmio", SHPC_SIZEOF(d
));
617 shpc_cap_update_dword(d
);
618 memory_region_add_subregion(bar
, offset
, &shpc
->mmio
);
619 pci_bus_hotplug(sec_bus
, shpc_device_hotplug
, &d
->qdev
);
621 d
->cap_present
|= QEMU_PCI_CAP_SHPC
;
625 int shpc_bar_size(PCIDevice
*d
)
627 return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS
));
630 void shpc_cleanup(PCIDevice
*d
, MemoryRegion
*bar
)
632 SHPCDevice
*shpc
= d
->shpc
;
633 d
->cap_present
&= ~QEMU_PCI_CAP_SHPC
;
634 memory_region_del_subregion(bar
, &shpc
->mmio
);
635 /* TODO: cleanup config space changes? */
636 g_free(shpc
->config
);
639 g_free(shpc
->w1cmask
);
640 memory_region_destroy(&shpc
->mmio
);
644 void shpc_cap_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
646 if (!ranges_overlap(addr
, l
, d
->shpc
->cap
, SHPC_CAP_LENGTH
)) {
649 if (ranges_overlap(addr
, l
, d
->shpc
->cap
+ SHPC_CAP_DWORD_DATA
, 4)) {
651 dword_data
= pci_get_long(d
->shpc
->config
+ d
->shpc
->cap
652 + SHPC_CAP_DWORD_DATA
);
653 shpc_write(d
, shpc_cap_dword(d
) * 4, dword_data
, 4);
655 /* Update cap dword data in case guest is going to read it. */
656 shpc_cap_update_dword(d
);
659 static void shpc_save(QEMUFile
*f
, void *pv
, size_t size
)
661 PCIDevice
*d
= container_of(pv
, PCIDevice
, shpc
);
662 qemu_put_buffer(f
, d
->shpc
->config
, SHPC_SIZEOF(d
));
665 static int shpc_load(QEMUFile
*f
, void *pv
, size_t size
)
667 PCIDevice
*d
= container_of(pv
, PCIDevice
, shpc
);
668 int ret
= qemu_get_buffer(f
, d
->shpc
->config
, SHPC_SIZEOF(d
));
669 if (ret
!= SHPC_SIZEOF(d
)) {
672 /* Make sure we don't lose notifications. An extra interrupt is harmless. */
673 d
->shpc
->msi_requested
= 0;
674 shpc_interrupt_update(d
);
678 VMStateInfo shpc_vmstate_info
= {