hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen/xen.h"
  33 #include "hw/pci-host/pam.h"
  34 #include "sysemu/sysemu.h"
  35
  36 /*
  37  * I440FX chipset data sheet.
  38  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  39  */
  40
  41 typedef struct I440FXState {
  42     PCIHostState parent_obj;
  43 } I440FXState;
  44
  45 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  46 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  47 #define XEN_PIIX_NUM_PIRQS      128ULL
  48 #define PIIX_PIRQC              0x60
  49
  50 /*
  51  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  52  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  53  */
  54 #define RCR_IOPORT 0xcf9
  55
  56 typedef struct PIIX3State {
  57     PCIDevice dev;
  58
  59     /*
  60      * bitmap to track pic levels.
  61      * The pic level is the logical OR of all the PCI irqs mapped to it
  62      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  63      *
  64      * PIRQ is mapped to PIC pins, we track it by
  65      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  66      * pic_irq * PIIX_NUM_PIRQS + pirq
  67      */
  68 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  69 #error "unable to encode pic state in 64bit in pic_levels."
  70 #endif
  71     uint64_t pic_levels;
  72
  73     qemu_irq *pic;
  74
  75     /* This member isn't used. Just for save/load compatibility */
  76     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  77
  78     /* Reset Control Register contents */
  79     uint8_t rcr;
  80
  81     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  82     MemoryRegion rcr_mem;
  83 } PIIX3State;
  84
  85 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  86 #define I440FX_PCI_DEVICE(obj) \
  87     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
  88
  89 struct PCII440FXState {
  90     PCIDevice dev;
  91     MemoryRegion *system_memory;
  92     MemoryRegion *pci_address_space;
  93     MemoryRegion *ram_memory;
  94     MemoryRegion pci_hole;
  95     MemoryRegion pci_hole_64bit;
  96     PAMMemoryRegion pam_regions[13];
  97     MemoryRegion smram_region;
  98     uint8_t smm_enabled;
  99 };
 100
 101
 102 #define I440FX_PAM      0x59
 103 #define I440FX_PAM_SIZE 7
 104 #define I440FX_SMRAM    0x72
 105
 106 static void piix3_set_irq(void *opaque, int pirq, int level);
 107 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 108 static void piix3_write_config_xen(PCIDevice *dev,
 109                                uint32_t address, uint32_t val, int len);
 110
 111 /* return the global irq number corresponding to a given device irq
 112    pin. We could also use the bus number to have a more precise
 113    mapping. */
 114 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 115 {
 116     int slot_addend;
 117     slot_addend = (pci_dev->devfn >> 3) - 1;
 118     return (pci_intx + slot_addend) & 3;
 119 }
 120
 121 static void i440fx_update_memory_mappings(PCII440FXState *d)
 122 {
 123     int i;
 124
 125     memory_region_transaction_begin();
 126     for (i = 0; i < 13; i++) {
 127         pam_update(&d->pam_regions[i], i,
 128                    d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
 129     }
 130     smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
 131     memory_region_transaction_commit();
 132 }
 133
 134 static void i440fx_set_smm(int val, void *arg)
 135 {
 136     PCII440FXState *d = arg;
 137
 138     memory_region_transaction_begin();
 139     smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
 140                   &d->smram_region);
 141     memory_region_transaction_commit();
 142 }
 143
 144
 145 static void i440fx_write_config(PCIDevice *dev,
 146                                 uint32_t address, uint32_t val, int len)
 147 {
 148     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 149
 150     /* XXX: implement SMRAM.D_LOCK */
 151     pci_default_write_config(dev, address, val, len);
 152     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 153         range_covers_byte(address, len, I440FX_SMRAM)) {
 154         i440fx_update_memory_mappings(d);
 155     }
 156 }
 157
 158 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 159 {
 160     PCII440FXState *d = opaque;
 161     int ret, i;
 162
 163     ret = pci_device_load(&d->dev, f);
 164     if (ret < 0)
 165         return ret;
 166     i440fx_update_memory_mappings(d);
 167     qemu_get_8s(f, &d->smm_enabled);
 168
 169     if (version_id == 2) {
 170         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 171             qemu_get_be32(f); /* dummy load for compatibility */
 172         }
 173     }
 174
 175     return 0;
 176 }
 177
 178 static int i440fx_post_load(void *opaque, int version_id)
 179 {
 180     PCII440FXState *d = opaque;
 181
 182     i440fx_update_memory_mappings(d);
 183     return 0;
 184 }
 185
 186 static const VMStateDescription vmstate_i440fx = {
 187     .name = "I440FX",
 188     .version_id = 3,
 189     .minimum_version_id = 3,
 190     .minimum_version_id_old = 1,
 191     .load_state_old = i440fx_load_old,
 192     .post_load = i440fx_post_load,
 193     .fields      = (VMStateField []) {
 194         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 195         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 196         VMSTATE_END_OF_LIST()
 197     }
 198 };
 199
 200 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 201 {
 202     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 203
 204     memory_region_init_io(&s->conf_mem, OBJECT(dev), &pci_host_conf_le_ops, s,
 205                           "pci-conf-idx", 4);
 206     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 207     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 208
 209     memory_region_init_io(&s->data_mem, OBJECT(dev), &pci_host_data_le_ops, s,
 210                           "pci-conf-data", 4);
 211     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 212     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 213
 214     return 0;
 215 }
 216
 217 static int i440fx_initfn(PCIDevice *dev)
 218 {
 219     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 220
 221     d->dev.config[I440FX_SMRAM] = 0x02;
 222
 223     cpu_smm_register(&i440fx_set_smm, d);
 224     return 0;
 225 }
 226
 227 static PCIBus *i440fx_common_init(const char *device_name,
 228                                   PCII440FXState **pi440fx_state,
 229                                   int *piix3_devfn,
 230                                   ISABus **isa_bus, qemu_irq *pic,
 231                                   MemoryRegion *address_space_mem,
 232                                   MemoryRegion *address_space_io,
 233                                   ram_addr_t ram_size,
 234                                   hwaddr pci_hole_start,
 235                                   hwaddr pci_hole_size,
 236                                   hwaddr pci_hole64_start,
 237                                   hwaddr pci_hole64_size,
 238                                   MemoryRegion *pci_address_space,
 239                                   MemoryRegion *ram_memory)
 240 {
 241     DeviceState *dev;
 242     PCIBus *b;
 243     PCIDevice *d;
 244     PCIHostState *s;
 245     PIIX3State *piix3;
 246     PCII440FXState *f;
 247     unsigned i;
 248
 249     dev = qdev_create(NULL, "i440FX-pcihost");
 250     s = PCI_HOST_BRIDGE(dev);
 251     b = pci_bus_new(dev, NULL, pci_address_space,
 252                     address_space_io, 0, TYPE_PCI_BUS);
 253     s->bus = b;
 254     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 255     qdev_init_nofail(dev);
 256
 257     d = pci_create_simple(b, 0, device_name);
 258     *pi440fx_state = I440FX_PCI_DEVICE(d);
 259     f = *pi440fx_state;
 260     f->system_memory = address_space_mem;
 261     f->pci_address_space = pci_address_space;
 262     f->ram_memory = ram_memory;
 263     memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
 264                              pci_hole_start, pci_hole_size);
 265     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 266     memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
 267                              f->pci_address_space,
 268                              pci_hole64_start, pci_hole64_size);
 269     if (pci_hole64_size) {
 270         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 271                                     &f->pci_hole_64bit);
 272     }
 273     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 274                              f->pci_address_space, 0xa0000, 0x20000);
 275     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 276                                         &f->smram_region, 1);
 277     memory_region_set_enabled(&f->smram_region, false);
 278     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 279              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 280     for (i = 0; i < 12; ++i) {
 281         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 282                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 283                  PAM_EXPAN_SIZE);
 284     }
 285
 286     /* Xen supports additional interrupt routes from the PCI devices to
 287      * the IOAPIC: the four pins of each PCI device on the bus are also
 288      * connected to the IOAPIC directly.
 289      * These additional routes can be discovered through ACPI. */
 290     if (xen_enabled()) {
 291         piix3 = DO_UPCAST(PIIX3State, dev,
 292                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 293         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 294                 piix3, XEN_PIIX_NUM_PIRQS);
 295     } else {
 296         piix3 = DO_UPCAST(PIIX3State, dev,
 297                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 298         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 299                 PIIX_NUM_PIRQS);
 300         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 301     }
 302     piix3->pic = pic;
 303     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 304
 305     *piix3_devfn = piix3->dev.devfn;
 306
 307     ram_size = ram_size / 8 / 1024 / 1024;
 308     if (ram_size > 255)
 309         ram_size = 255;
 310     (*pi440fx_state)->dev.config[0x57]=ram_size;
 311
 312     i440fx_update_memory_mappings(f);
 313
 314     return b;
 315 }
 316
 317 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 318                     ISABus **isa_bus, qemu_irq *pic,
 319                     MemoryRegion *address_space_mem,
 320                     MemoryRegion *address_space_io,
 321                     ram_addr_t ram_size,
 322                     hwaddr pci_hole_start,
 323                     hwaddr pci_hole_size,
 324                     hwaddr pci_hole64_start,
 325                     hwaddr pci_hole64_size,
 326                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 327
 328 {
 329     PCIBus *b;
 330
 331     b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE, pi440fx_state,
 332                            piix3_devfn, isa_bus, pic,
 333                            address_space_mem, address_space_io, ram_size,
 334                            pci_hole_start, pci_hole_size,
 335                            pci_hole64_start, pci_hole64_size,
 336                            pci_memory, ram_memory);
 337     return b;
 338 }
 339
 340 /* PIIX3 PCI to ISA bridge */
 341 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 342 {
 343     qemu_set_irq(piix3->pic[pic_irq],
 344                  !!(piix3->pic_levels &
 345                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 346                      (pic_irq * PIIX_NUM_PIRQS))));
 347 }
 348
 349 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 350 {
 351     int pic_irq;
 352     uint64_t mask;
 353
 354     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 355     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 356         return;
 357     }
 358
 359     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 360     piix3->pic_levels &= ~mask;
 361     piix3->pic_levels |= mask * !!level;
 362
 363     piix3_set_irq_pic(piix3, pic_irq);
 364 }
 365
 366 static void piix3_set_irq(void *opaque, int pirq, int level)
 367 {
 368     PIIX3State *piix3 = opaque;
 369     piix3_set_irq_level(piix3, pirq, level);
 370 }
 371
 372 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 373 {
 374     PIIX3State *piix3 = opaque;
 375     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 376     PCIINTxRoute route;
 377
 378     if (irq < PIIX_NUM_PIC_IRQS) {
 379         route.mode = PCI_INTX_ENABLED;
 380         route.irq = irq;
 381     } else {
 382         route.mode = PCI_INTX_DISABLED;
 383         route.irq = -1;
 384     }
 385     return route;
 386 }
 387
 388 /* irq routing is changed. so rebuild bitmap */
 389 static void piix3_update_irq_levels(PIIX3State *piix3)
 390 {
 391     int pirq;
 392
 393     piix3->pic_levels = 0;
 394     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 395         piix3_set_irq_level(piix3, pirq,
 396                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 397     }
 398 }
 399
 400 static void piix3_write_config(PCIDevice *dev,
 401                                uint32_t address, uint32_t val, int len)
 402 {
 403     pci_default_write_config(dev, address, val, len);
 404     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 405         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 406         int pic_irq;
 407
 408         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 409         piix3_update_irq_levels(piix3);
 410         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 411             piix3_set_irq_pic(piix3, pic_irq);
 412         }
 413     }
 414 }
 415
 416 static void piix3_write_config_xen(PCIDevice *dev,
 417                                uint32_t address, uint32_t val, int len)
 418 {
 419     xen_piix_pci_write_config_client(address, val, len);
 420     piix3_write_config(dev, address, val, len);
 421 }
 422
 423 static void piix3_reset(void *opaque)
 424 {
 425     PIIX3State *d = opaque;
 426     uint8_t *pci_conf = d->dev.config;
 427
 428     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 429     pci_conf[0x05] = 0x00;
 430     pci_conf[0x06] = 0x00;
 431     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 432     pci_conf[0x4c] = 0x4d;
 433     pci_conf[0x4e] = 0x03;
 434     pci_conf[0x4f] = 0x00;
 435     pci_conf[0x60] = 0x80;
 436     pci_conf[0x61] = 0x80;
 437     pci_conf[0x62] = 0x80;
 438     pci_conf[0x63] = 0x80;
 439     pci_conf[0x69] = 0x02;
 440     pci_conf[0x70] = 0x80;
 441     pci_conf[0x76] = 0x0c;
 442     pci_conf[0x77] = 0x0c;
 443     pci_conf[0x78] = 0x02;
 444     pci_conf[0x79] = 0x00;
 445     pci_conf[0x80] = 0x00;
 446     pci_conf[0x82] = 0x00;
 447     pci_conf[0xa0] = 0x08;
 448     pci_conf[0xa2] = 0x00;
 449     pci_conf[0xa3] = 0x00;
 450     pci_conf[0xa4] = 0x00;
 451     pci_conf[0xa5] = 0x00;
 452     pci_conf[0xa6] = 0x00;
 453     pci_conf[0xa7] = 0x00;
 454     pci_conf[0xa8] = 0x0f;
 455     pci_conf[0xaa] = 0x00;
 456     pci_conf[0xab] = 0x00;
 457     pci_conf[0xac] = 0x00;
 458     pci_conf[0xae] = 0x00;
 459
 460     d->pic_levels = 0;
 461     d->rcr = 0;
 462 }
 463
 464 static int piix3_post_load(void *opaque, int version_id)
 465 {
 466     PIIX3State *piix3 = opaque;
 467     piix3_update_irq_levels(piix3);
 468     return 0;
 469 }
 470
 471 static void piix3_pre_save(void *opaque)
 472 {
 473     int i;
 474     PIIX3State *piix3 = opaque;
 475
 476     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 477         piix3->pci_irq_levels_vmstate[i] =
 478             pci_bus_get_irq_level(piix3->dev.bus, i);
 479     }
 480 }
 481
 482 static bool piix3_rcr_needed(void *opaque)
 483 {
 484     PIIX3State *piix3 = opaque;
 485
 486     return (piix3->rcr != 0);
 487 }
 488
 489 static const VMStateDescription vmstate_piix3_rcr = {
 490     .name = "PIIX3/rcr",
 491     .version_id = 1,
 492     .minimum_version_id = 1,
 493     .fields = (VMStateField []) {
 494         VMSTATE_UINT8(rcr, PIIX3State),
 495         VMSTATE_END_OF_LIST()
 496     }
 497 };
 498
 499 static const VMStateDescription vmstate_piix3 = {
 500     .name = "PIIX3",
 501     .version_id = 3,
 502     .minimum_version_id = 2,
 503     .minimum_version_id_old = 2,
 504     .post_load = piix3_post_load,
 505     .pre_save = piix3_pre_save,
 506     .fields      = (VMStateField[]) {
 507         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 508         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 509                               PIIX_NUM_PIRQS, 3),
 510         VMSTATE_END_OF_LIST()
 511     },
 512     .subsections = (VMStateSubsection[]) {
 513         {
 514             .vmsd = &vmstate_piix3_rcr,
 515             .needed = piix3_rcr_needed,
 516         },
 517         { 0 }
 518     }
 519 };
 520
 521
 522 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 523 {
 524     PIIX3State *d = opaque;
 525
 526     if (val & 4) {
 527         qemu_system_reset_request();
 528         return;
 529     }
 530     d->rcr = val & 2; /* keep System Reset type only */
 531 }
 532
 533 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 534 {
 535     PIIX3State *d = opaque;
 536
 537     return d->rcr;
 538 }
 539
 540 static const MemoryRegionOps rcr_ops = {
 541     .read = rcr_read,
 542     .write = rcr_write,
 543     .endianness = DEVICE_LITTLE_ENDIAN
 544 };
 545
 546 static int piix3_initfn(PCIDevice *dev)
 547 {
 548     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 549
 550     isa_bus_new(DEVICE(d), pci_address_space_io(dev));
 551
 552     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 553                           "piix3-reset-control", 1);
 554     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 555                                         &d->rcr_mem, 1);
 556
 557     qemu_register_reset(piix3_reset, d);
 558     return 0;
 559 }
 560
 561 static void piix3_class_init(ObjectClass *klass, void *data)
 562 {
 563     DeviceClass *dc = DEVICE_CLASS(klass);
 564     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 565
 566     dc->desc        = "ISA bridge";
 567     dc->vmsd        = &vmstate_piix3;
 568     dc->no_user     = 1,
 569     k->no_hotplug   = 1;
 570     k->init         = piix3_initfn;
 571     k->config_write = piix3_write_config;
 572     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 573     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 574     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 575     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 576 }
 577
 578 static const TypeInfo piix3_info = {
 579     .name          = "PIIX3",
 580     .parent        = TYPE_PCI_DEVICE,
 581     .instance_size = sizeof(PIIX3State),
 582     .class_init    = piix3_class_init,
 583 };
 584
 585 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 586 {
 587     DeviceClass *dc = DEVICE_CLASS(klass);
 588     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 589
 590     dc->desc        = "ISA bridge";
 591     dc->vmsd        = &vmstate_piix3;
 592     dc->no_user     = 1;
 593     k->no_hotplug   = 1;
 594     k->init         = piix3_initfn;
 595     k->config_write = piix3_write_config_xen;
 596     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 597     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 598     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 599     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 600 };
 601
 602 static const TypeInfo piix3_xen_info = {
 603     .name          = "PIIX3-xen",
 604     .parent        = TYPE_PCI_DEVICE,
 605     .instance_size = sizeof(PIIX3State),
 606     .class_init    = piix3_xen_class_init,
 607 };
 608
 609 static void i440fx_class_init(ObjectClass *klass, void *data)
 610 {
 611     DeviceClass *dc = DEVICE_CLASS(klass);
 612     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 613
 614     k->no_hotplug = 1;
 615     k->init = i440fx_initfn;
 616     k->config_write = i440fx_write_config;
 617     k->vendor_id = PCI_VENDOR_ID_INTEL;
 618     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 619     k->revision = 0x02;
 620     k->class_id = PCI_CLASS_BRIDGE_HOST;
 621     dc->desc = "Host bridge";
 622     dc->no_user = 1;
 623     dc->vmsd = &vmstate_i440fx;
 624 }
 625
 626 static const TypeInfo i440fx_info = {
 627     .name          = TYPE_I440FX_PCI_DEVICE,
 628     .parent        = TYPE_PCI_DEVICE,
 629     .instance_size = sizeof(PCII440FXState),
 630     .class_init    = i440fx_class_init,
 631 };
 632
 633 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 634                                                 PCIBus *rootbus)
 635 {
 636     /* For backwards compat with old device paths */
 637     return "0000";
 638 }
 639
 640 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 641 {
 642     DeviceClass *dc = DEVICE_CLASS(klass);
 643     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 644     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 645
 646     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 647     k->init = i440fx_pcihost_initfn;
 648     dc->fw_name = "pci";
 649     dc->no_user = 1;
 650 }
 651
 652 static const TypeInfo i440fx_pcihost_info = {
 653     .name          = "i440FX-pcihost",
 654     .parent        = TYPE_PCI_HOST_BRIDGE,
 655     .instance_size = sizeof(I440FXState),
 656     .class_init    = i440fx_pcihost_class_init,
 657 };
 658
 659 static void i440fx_register_types(void)
 660 {
 661     type_register_static(&i440fx_info);
 662     type_register_static(&piix3_info);
 663     type_register_static(&piix3_xen_info);
 664     type_register_static(&i440fx_pcihost_info);
 665 }
 666
 667 type_init(i440fx_register_types)