hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen/xen.h"
  33 #include "hw/pci-host/pam.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/i386/ioapic.h"
  36 #include "qapi/visitor.h"
  37
  38 /*
  39  * I440FX chipset data sheet.
  40  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  41  */
  42
  43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
  44 #define I440FX_PCI_HOST_BRIDGE(obj) \
  45     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  46
  47 typedef struct I440FXState {
  48     PCIHostState parent_obj;
  49     PcPciInfo pci_info;
  50     uint64_t pci_hole64_size;
  51     uint32_t short_root_bus;
  52 } I440FXState;
  53
  54 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  55 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  56 #define XEN_PIIX_NUM_PIRQS      128ULL
  57 #define PIIX_PIRQC              0x60
  58
  59 /*
  60  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  61  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  62  */
  63 #define RCR_IOPORT 0xcf9
  64
  65 typedef struct PIIX3State {
  66     PCIDevice dev;
  67
  68     /*
  69      * bitmap to track pic levels.
  70      * The pic level is the logical OR of all the PCI irqs mapped to it
  71      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  72      *
  73      * PIRQ is mapped to PIC pins, we track it by
  74      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  75      * pic_irq * PIIX_NUM_PIRQS + pirq
  76      */
  77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  78 #error "unable to encode pic state in 64bit in pic_levels."
  79 #endif
  80     uint64_t pic_levels;
  81
  82     qemu_irq *pic;
  83
  84     /* This member isn't used. Just for save/load compatibility */
  85     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  86
  87     /* Reset Control Register contents */
  88     uint8_t rcr;
  89
  90     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  91     MemoryRegion rcr_mem;
  92 } PIIX3State;
  93
  94 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  95 #define I440FX_PCI_DEVICE(obj) \
  96     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
  97
  98 struct PCII440FXState {
  99     /*< private >*/
 100     PCIDevice parent_obj;
 101     /*< public >*/
 102
 103     MemoryRegion *system_memory;
 104     MemoryRegion *pci_address_space;
 105     MemoryRegion *ram_memory;
 106     MemoryRegion pci_hole;
 107     MemoryRegion pci_hole_64bit;
 108     PAMMemoryRegion pam_regions[13];
 109     MemoryRegion smram_region;
 110     uint8_t smm_enabled;
 111 };
 112
 113
 114 #define I440FX_PAM      0x59
 115 #define I440FX_PAM_SIZE 7
 116 #define I440FX_SMRAM    0x72
 117
 118 static void piix3_set_irq(void *opaque, int pirq, int level);
 119 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 120 static void piix3_write_config_xen(PCIDevice *dev,
 121                                uint32_t address, uint32_t val, int len);
 122
 123 /* return the global irq number corresponding to a given device irq
 124    pin. We could also use the bus number to have a more precise
 125    mapping. */
 126 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 127 {
 128     int slot_addend;
 129     slot_addend = (pci_dev->devfn >> 3) - 1;
 130     return (pci_intx + slot_addend) & 3;
 131 }
 132
 133 static void i440fx_update_memory_mappings(PCII440FXState *d)
 134 {
 135     int i;
 136     PCIDevice *pd = PCI_DEVICE(d);
 137
 138     memory_region_transaction_begin();
 139     for (i = 0; i < 13; i++) {
 140         pam_update(&d->pam_regions[i], i,
 141                    pd->config[I440FX_PAM + ((i + 1) / 2)]);
 142     }
 143     smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
 144     memory_region_transaction_commit();
 145 }
 146
 147 static void i440fx_set_smm(int val, void *arg)
 148 {
 149     PCII440FXState *d = arg;
 150     PCIDevice *pd = PCI_DEVICE(d);
 151
 152     memory_region_transaction_begin();
 153     smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
 154                   &d->smram_region);
 155     memory_region_transaction_commit();
 156 }
 157
 158
 159 static void i440fx_write_config(PCIDevice *dev,
 160                                 uint32_t address, uint32_t val, int len)
 161 {
 162     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 163
 164     /* XXX: implement SMRAM.D_LOCK */
 165     pci_default_write_config(dev, address, val, len);
 166     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 167         range_covers_byte(address, len, I440FX_SMRAM)) {
 168         i440fx_update_memory_mappings(d);
 169     }
 170 }
 171
 172 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 173 {
 174     PCII440FXState *d = opaque;
 175     PCIDevice *pd = PCI_DEVICE(d);
 176     int ret, i;
 177
 178     ret = pci_device_load(pd, f);
 179     if (ret < 0)
 180         return ret;
 181     i440fx_update_memory_mappings(d);
 182     qemu_get_8s(f, &d->smm_enabled);
 183
 184     if (version_id == 2) {
 185         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 186             qemu_get_be32(f); /* dummy load for compatibility */
 187         }
 188     }
 189
 190     return 0;
 191 }
 192
 193 static int i440fx_post_load(void *opaque, int version_id)
 194 {
 195     PCII440FXState *d = opaque;
 196
 197     i440fx_update_memory_mappings(d);
 198     return 0;
 199 }
 200
 201 static const VMStateDescription vmstate_i440fx = {
 202     .name = "I440FX",
 203     .version_id = 3,
 204     .minimum_version_id = 3,
 205     .minimum_version_id_old = 1,
 206     .load_state_old = i440fx_load_old,
 207     .post_load = i440fx_post_load,
 208     .fields      = (VMStateField []) {
 209         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 210         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 211         VMSTATE_END_OF_LIST()
 212     }
 213 };
 214
 215 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 216                                               void *opaque, const char *name,
 217                                               Error **errp)
 218 {
 219     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 220     uint32_t value = s->pci_info.w32.begin;
 221
 222     visit_type_uint32(v, &value, name, errp);
 223 }
 224
 225 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 226                                             void *opaque, const char *name,
 227                                             Error **errp)
 228 {
 229     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 230     uint32_t value = s->pci_info.w32.end;
 231
 232     visit_type_uint32(v, &value, name, errp);
 233 }
 234
 235 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 236                                                 void *opaque, const char *name,
 237                                                 Error **errp)
 238 {
 239     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 240     Range w64;
 241
 242     pci_bus_get_w64_range(h->bus, &w64);
 243
 244     visit_type_uint64(v, &w64.begin, name, errp);
 245 }
 246
 247 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 248                                               void *opaque, const char *name,
 249                                               Error **errp)
 250 {
 251     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 252     Range w64;
 253
 254     pci_bus_get_w64_range(h->bus, &w64);
 255
 256     visit_type_uint64(v, &w64.end, name, errp);
 257 }
 258
 259 static void i440fx_pcihost_initfn(Object *obj)
 260 {
 261     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 262     I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
 263
 264     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 265                           "pci-conf-idx", 4);
 266     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 267                           "pci-conf-data", 4);
 268
 269     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 270                         i440fx_pcihost_get_pci_hole_start,
 271                         NULL, NULL, NULL, NULL);
 272
 273     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 274                         i440fx_pcihost_get_pci_hole_end,
 275                         NULL, NULL, NULL, NULL);
 276
 277     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 278                         i440fx_pcihost_get_pci_hole64_start,
 279                         NULL, NULL, NULL, NULL);
 280
 281     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 282                         i440fx_pcihost_get_pci_hole64_end,
 283                         NULL, NULL, NULL, NULL);
 284
 285     d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 286 }
 287
 288 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 289 {
 290     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 291     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 292
 293     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 294     sysbus_init_ioports(sbd, 0xcf8, 4);
 295
 296     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 297     sysbus_init_ioports(sbd, 0xcfc, 4);
 298 }
 299
 300 static int i440fx_initfn(PCIDevice *dev)
 301 {
 302     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 303
 304     dev->config[I440FX_SMRAM] = 0x02;
 305
 306     cpu_smm_register(&i440fx_set_smm, d);
 307     return 0;
 308 }
 309
 310 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
 311                     int *piix3_devfn,
 312                     ISABus **isa_bus, qemu_irq *pic,
 313                     MemoryRegion *address_space_mem,
 314                     MemoryRegion *address_space_io,
 315                     ram_addr_t ram_size,
 316                     hwaddr pci_hole_start,
 317                     hwaddr pci_hole_size,
 318                     ram_addr_t above_4g_mem_size,
 319                     MemoryRegion *pci_address_space,
 320                     MemoryRegion *ram_memory)
 321 {
 322     DeviceState *dev;
 323     PCIBus *b;
 324     PCIDevice *d;
 325     PCIHostState *s;
 326     PIIX3State *piix3;
 327     PCII440FXState *f;
 328     unsigned i;
 329     I440FXState *i440fx;
 330     uint64_t pci_hole64_size;
 331
 332     dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
 333     s = PCI_HOST_BRIDGE(dev);
 334     b = pci_bus_new(dev, NULL, pci_address_space,
 335                     address_space_io, 0, TYPE_PCI_BUS);
 336     s->bus = b;
 337     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 338     qdev_init_nofail(dev);
 339
 340     d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
 341     *pi440fx_state = I440FX_PCI_DEVICE(d);
 342     f = *pi440fx_state;
 343     f->system_memory = address_space_mem;
 344     f->pci_address_space = pci_address_space;
 345     f->ram_memory = ram_memory;
 346
 347     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 348     /* Set PCI window size the way seabios has always done it. */
 349     /* Power of 2 so bios can cover it with a single MTRR */
 350     if (ram_size <= 0x80000000) {
 351         i440fx->pci_info.w32.begin = 0x80000000;
 352     } else if (ram_size <= 0xc0000000) {
 353         i440fx->pci_info.w32.begin = 0xc0000000;
 354     } else {
 355         i440fx->pci_info.w32.begin = 0xe0000000;
 356     }
 357
 358     memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
 359                              pci_hole_start, pci_hole_size);
 360     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 361
 362     pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size);
 363
 364     pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
 365                        pci_hole64_size);
 366     memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
 367                              f->pci_address_space,
 368                              i440fx->pci_info.w64.begin,
 369                              pci_hole64_size);
 370     if (pci_hole64_size) {
 371         memory_region_add_subregion(f->system_memory,
 372                                     i440fx->pci_info.w64.begin,
 373                                     &f->pci_hole_64bit);
 374     }
 375     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 376                              f->pci_address_space, 0xa0000, 0x20000);
 377     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 378                                         &f->smram_region, 1);
 379     memory_region_set_enabled(&f->smram_region, false);
 380     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 381              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 382     for (i = 0; i < 12; ++i) {
 383         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 384                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 385                  PAM_EXPAN_SIZE);
 386     }
 387
 388     /* Xen supports additional interrupt routes from the PCI devices to
 389      * the IOAPIC: the four pins of each PCI device on the bus are also
 390      * connected to the IOAPIC directly.
 391      * These additional routes can be discovered through ACPI. */
 392     if (xen_enabled()) {
 393         piix3 = DO_UPCAST(PIIX3State, dev,
 394                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 395         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 396                 piix3, XEN_PIIX_NUM_PIRQS);
 397     } else {
 398         piix3 = DO_UPCAST(PIIX3State, dev,
 399                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 400         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 401                 PIIX_NUM_PIRQS);
 402         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 403     }
 404     piix3->pic = pic;
 405     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 406
 407     *piix3_devfn = piix3->dev.devfn;
 408
 409     ram_size = ram_size / 8 / 1024 / 1024;
 410     if (ram_size > 255) {
 411         ram_size = 255;
 412     }
 413     d->config[0x57] = ram_size;
 414
 415     i440fx_update_memory_mappings(f);
 416
 417     return b;
 418 }
 419
 420 PCIBus *find_i440fx(void)
 421 {
 422     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 423                                    object_resolve_path("/machine/i440fx", NULL),
 424                                    TYPE_PCI_HOST_BRIDGE);
 425     return s ? s->bus : NULL;
 426 }
 427
 428 /* PIIX3 PCI to ISA bridge */
 429 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 430 {
 431     qemu_set_irq(piix3->pic[pic_irq],
 432                  !!(piix3->pic_levels &
 433                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 434                      (pic_irq * PIIX_NUM_PIRQS))));
 435 }
 436
 437 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 438 {
 439     int pic_irq;
 440     uint64_t mask;
 441
 442     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 443     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 444         return;
 445     }
 446
 447     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 448     piix3->pic_levels &= ~mask;
 449     piix3->pic_levels |= mask * !!level;
 450
 451     piix3_set_irq_pic(piix3, pic_irq);
 452 }
 453
 454 static void piix3_set_irq(void *opaque, int pirq, int level)
 455 {
 456     PIIX3State *piix3 = opaque;
 457     piix3_set_irq_level(piix3, pirq, level);
 458 }
 459
 460 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 461 {
 462     PIIX3State *piix3 = opaque;
 463     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 464     PCIINTxRoute route;
 465
 466     if (irq < PIIX_NUM_PIC_IRQS) {
 467         route.mode = PCI_INTX_ENABLED;
 468         route.irq = irq;
 469     } else {
 470         route.mode = PCI_INTX_DISABLED;
 471         route.irq = -1;
 472     }
 473     return route;
 474 }
 475
 476 /* irq routing is changed. so rebuild bitmap */
 477 static void piix3_update_irq_levels(PIIX3State *piix3)
 478 {
 479     int pirq;
 480
 481     piix3->pic_levels = 0;
 482     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 483         piix3_set_irq_level(piix3, pirq,
 484                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 485     }
 486 }
 487
 488 static void piix3_write_config(PCIDevice *dev,
 489                                uint32_t address, uint32_t val, int len)
 490 {
 491     pci_default_write_config(dev, address, val, len);
 492     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 493         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 494         int pic_irq;
 495
 496         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 497         piix3_update_irq_levels(piix3);
 498         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 499             piix3_set_irq_pic(piix3, pic_irq);
 500         }
 501     }
 502 }
 503
 504 static void piix3_write_config_xen(PCIDevice *dev,
 505                                uint32_t address, uint32_t val, int len)
 506 {
 507     xen_piix_pci_write_config_client(address, val, len);
 508     piix3_write_config(dev, address, val, len);
 509 }
 510
 511 static void piix3_reset(void *opaque)
 512 {
 513     PIIX3State *d = opaque;
 514     uint8_t *pci_conf = d->dev.config;
 515
 516     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 517     pci_conf[0x05] = 0x00;
 518     pci_conf[0x06] = 0x00;
 519     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 520     pci_conf[0x4c] = 0x4d;
 521     pci_conf[0x4e] = 0x03;
 522     pci_conf[0x4f] = 0x00;
 523     pci_conf[0x60] = 0x80;
 524     pci_conf[0x61] = 0x80;
 525     pci_conf[0x62] = 0x80;
 526     pci_conf[0x63] = 0x80;
 527     pci_conf[0x69] = 0x02;
 528     pci_conf[0x70] = 0x80;
 529     pci_conf[0x76] = 0x0c;
 530     pci_conf[0x77] = 0x0c;
 531     pci_conf[0x78] = 0x02;
 532     pci_conf[0x79] = 0x00;
 533     pci_conf[0x80] = 0x00;
 534     pci_conf[0x82] = 0x00;
 535     pci_conf[0xa0] = 0x08;
 536     pci_conf[0xa2] = 0x00;
 537     pci_conf[0xa3] = 0x00;
 538     pci_conf[0xa4] = 0x00;
 539     pci_conf[0xa5] = 0x00;
 540     pci_conf[0xa6] = 0x00;
 541     pci_conf[0xa7] = 0x00;
 542     pci_conf[0xa8] = 0x0f;
 543     pci_conf[0xaa] = 0x00;
 544     pci_conf[0xab] = 0x00;
 545     pci_conf[0xac] = 0x00;
 546     pci_conf[0xae] = 0x00;
 547
 548     d->pic_levels = 0;
 549     d->rcr = 0;
 550 }
 551
 552 static int piix3_post_load(void *opaque, int version_id)
 553 {
 554     PIIX3State *piix3 = opaque;
 555     piix3_update_irq_levels(piix3);
 556     return 0;
 557 }
 558
 559 static void piix3_pre_save(void *opaque)
 560 {
 561     int i;
 562     PIIX3State *piix3 = opaque;
 563
 564     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 565         piix3->pci_irq_levels_vmstate[i] =
 566             pci_bus_get_irq_level(piix3->dev.bus, i);
 567     }
 568 }
 569
 570 static bool piix3_rcr_needed(void *opaque)
 571 {
 572     PIIX3State *piix3 = opaque;
 573
 574     return (piix3->rcr != 0);
 575 }
 576
 577 static const VMStateDescription vmstate_piix3_rcr = {
 578     .name = "PIIX3/rcr",
 579     .version_id = 1,
 580     .minimum_version_id = 1,
 581     .fields = (VMStateField []) {
 582         VMSTATE_UINT8(rcr, PIIX3State),
 583         VMSTATE_END_OF_LIST()
 584     }
 585 };
 586
 587 static const VMStateDescription vmstate_piix3 = {
 588     .name = "PIIX3",
 589     .version_id = 3,
 590     .minimum_version_id = 2,
 591     .minimum_version_id_old = 2,
 592     .post_load = piix3_post_load,
 593     .pre_save = piix3_pre_save,
 594     .fields      = (VMStateField[]) {
 595         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 596         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 597                               PIIX_NUM_PIRQS, 3),
 598         VMSTATE_END_OF_LIST()
 599     },
 600     .subsections = (VMStateSubsection[]) {
 601         {
 602             .vmsd = &vmstate_piix3_rcr,
 603             .needed = piix3_rcr_needed,
 604         },
 605         { 0 }
 606     }
 607 };
 608
 609
 610 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 611 {
 612     PIIX3State *d = opaque;
 613
 614     if (val & 4) {
 615         qemu_system_reset_request();
 616         return;
 617     }
 618     d->rcr = val & 2; /* keep System Reset type only */
 619 }
 620
 621 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 622 {
 623     PIIX3State *d = opaque;
 624
 625     return d->rcr;
 626 }
 627
 628 static const MemoryRegionOps rcr_ops = {
 629     .read = rcr_read,
 630     .write = rcr_write,
 631     .endianness = DEVICE_LITTLE_ENDIAN
 632 };
 633
 634 static int piix3_initfn(PCIDevice *dev)
 635 {
 636     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 637
 638     isa_bus_new(DEVICE(d), pci_address_space_io(dev));
 639
 640     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 641                           "piix3-reset-control", 1);
 642     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 643                                         &d->rcr_mem, 1);
 644
 645     qemu_register_reset(piix3_reset, d);
 646     return 0;
 647 }
 648
 649 static void piix3_class_init(ObjectClass *klass, void *data)
 650 {
 651     DeviceClass *dc = DEVICE_CLASS(klass);
 652     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 653
 654     dc->desc        = "ISA bridge";
 655     dc->vmsd        = &vmstate_piix3;
 656     dc->no_user     = 1,
 657     k->no_hotplug   = 1;
 658     k->init         = piix3_initfn;
 659     k->config_write = piix3_write_config;
 660     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 661     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 662     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 663     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 664 }
 665
 666 static const TypeInfo piix3_info = {
 667     .name          = "PIIX3",
 668     .parent        = TYPE_PCI_DEVICE,
 669     .instance_size = sizeof(PIIX3State),
 670     .class_init    = piix3_class_init,
 671 };
 672
 673 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 674 {
 675     DeviceClass *dc = DEVICE_CLASS(klass);
 676     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 677
 678     dc->desc        = "ISA bridge";
 679     dc->vmsd        = &vmstate_piix3;
 680     dc->no_user     = 1;
 681     k->no_hotplug   = 1;
 682     k->init         = piix3_initfn;
 683     k->config_write = piix3_write_config_xen;
 684     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 685     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 686     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 687     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 688 };
 689
 690 static const TypeInfo piix3_xen_info = {
 691     .name          = "PIIX3-xen",
 692     .parent        = TYPE_PCI_DEVICE,
 693     .instance_size = sizeof(PIIX3State),
 694     .class_init    = piix3_xen_class_init,
 695 };
 696
 697 static void i440fx_class_init(ObjectClass *klass, void *data)
 698 {
 699     DeviceClass *dc = DEVICE_CLASS(klass);
 700     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 701
 702     k->no_hotplug = 1;
 703     k->init = i440fx_initfn;
 704     k->config_write = i440fx_write_config;
 705     k->vendor_id = PCI_VENDOR_ID_INTEL;
 706     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 707     k->revision = 0x02;
 708     k->class_id = PCI_CLASS_BRIDGE_HOST;
 709     dc->desc = "Host bridge";
 710     dc->no_user = 1;
 711     dc->vmsd = &vmstate_i440fx;
 712 }
 713
 714 static const TypeInfo i440fx_info = {
 715     .name          = TYPE_I440FX_PCI_DEVICE,
 716     .parent        = TYPE_PCI_DEVICE,
 717     .instance_size = sizeof(PCII440FXState),
 718     .class_init    = i440fx_class_init,
 719 };
 720
 721 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 722                                                 PCIBus *rootbus)
 723 {
 724     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 725
 726     /* For backwards compat with old device paths */
 727     if (s->short_root_bus) {
 728         return "0000";
 729     }
 730     return "0000:00";
 731 }
 732
 733 static Property i440fx_props[] = {
 734     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 735                      pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 736     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 737     DEFINE_PROP_END_OF_LIST(),
 738 };
 739
 740 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 741 {
 742     DeviceClass *dc = DEVICE_CLASS(klass);
 743     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 744
 745     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 746     dc->realize = i440fx_pcihost_realize;
 747     dc->fw_name = "pci";
 748     dc->no_user = 1;
 749     dc->props = i440fx_props;
 750 }
 751
 752 static const TypeInfo i440fx_pcihost_info = {
 753     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 754     .parent        = TYPE_PCI_HOST_BRIDGE,
 755     .instance_size = sizeof(I440FXState),
 756     .instance_init = i440fx_pcihost_initfn,
 757     .class_init    = i440fx_pcihost_class_init,
 758 };
 759
 760 static void i440fx_register_types(void)
 761 {
 762     type_register_static(&i440fx_info);
 763     type_register_static(&piix3_info);
 764     type_register_static(&piix3_xen_info);
 765     type_register_static(&i440fx_pcihost_info);
 766 }
 767
 768 type_init(i440fx_register_types)