hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen/xen.h"
  33 #include "hw/pci-host/pam.h"
  34 #include "sysemu/sysemu.h"
  35
  36 /*
  37  * I440FX chipset data sheet.
  38  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  39  */
  40
  41 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
  42 #define I440FX_PCI_HOST_BRIDGE(obj) \
  43     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  44
  45 typedef struct I440FXState {
  46     PCIHostState parent_obj;
  47 } I440FXState;
  48
  49 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  50 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  51 #define XEN_PIIX_NUM_PIRQS      128ULL
  52 #define PIIX_PIRQC              0x60
  53
  54 /*
  55  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  56  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  57  */
  58 #define RCR_IOPORT 0xcf9
  59
  60 typedef struct PIIX3State {
  61     PCIDevice dev;
  62
  63     /*
  64      * bitmap to track pic levels.
  65      * The pic level is the logical OR of all the PCI irqs mapped to it
  66      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  67      *
  68      * PIRQ is mapped to PIC pins, we track it by
  69      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  70      * pic_irq * PIIX_NUM_PIRQS + pirq
  71      */
  72 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  73 #error "unable to encode pic state in 64bit in pic_levels."
  74 #endif
  75     uint64_t pic_levels;
  76
  77     qemu_irq *pic;
  78
  79     /* This member isn't used. Just for save/load compatibility */
  80     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  81
  82     /* Reset Control Register contents */
  83     uint8_t rcr;
  84
  85     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  86     MemoryRegion rcr_mem;
  87 } PIIX3State;
  88
  89 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  90 #define I440FX_PCI_DEVICE(obj) \
  91     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
  92
  93 struct PCII440FXState {
  94     /*< private >*/
  95     PCIDevice parent_obj;
  96     /*< public >*/
  97
  98     MemoryRegion *system_memory;
  99     MemoryRegion *pci_address_space;
 100     MemoryRegion *ram_memory;
 101     MemoryRegion pci_hole;
 102     MemoryRegion pci_hole_64bit;
 103     PAMMemoryRegion pam_regions[13];
 104     MemoryRegion smram_region;
 105     uint8_t smm_enabled;
 106 };
 107
 108
 109 #define I440FX_PAM      0x59
 110 #define I440FX_PAM_SIZE 7
 111 #define I440FX_SMRAM    0x72
 112
 113 static void piix3_set_irq(void *opaque, int pirq, int level);
 114 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 115 static void piix3_write_config_xen(PCIDevice *dev,
 116                                uint32_t address, uint32_t val, int len);
 117
 118 /* return the global irq number corresponding to a given device irq
 119    pin. We could also use the bus number to have a more precise
 120    mapping. */
 121 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 122 {
 123     int slot_addend;
 124     slot_addend = (pci_dev->devfn >> 3) - 1;
 125     return (pci_intx + slot_addend) & 3;
 126 }
 127
 128 static void i440fx_update_memory_mappings(PCII440FXState *d)
 129 {
 130     int i;
 131     PCIDevice *pd = PCI_DEVICE(d);
 132
 133     memory_region_transaction_begin();
 134     for (i = 0; i < 13; i++) {
 135         pam_update(&d->pam_regions[i], i,
 136                    pd->config[I440FX_PAM + ((i + 1) / 2)]);
 137     }
 138     smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
 139     memory_region_transaction_commit();
 140 }
 141
 142 static void i440fx_set_smm(int val, void *arg)
 143 {
 144     PCII440FXState *d = arg;
 145     PCIDevice *pd = PCI_DEVICE(d);
 146
 147     memory_region_transaction_begin();
 148     smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
 149                   &d->smram_region);
 150     memory_region_transaction_commit();
 151 }
 152
 153
 154 static void i440fx_write_config(PCIDevice *dev,
 155                                 uint32_t address, uint32_t val, int len)
 156 {
 157     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 158
 159     /* XXX: implement SMRAM.D_LOCK */
 160     pci_default_write_config(dev, address, val, len);
 161     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 162         range_covers_byte(address, len, I440FX_SMRAM)) {
 163         i440fx_update_memory_mappings(d);
 164     }
 165 }
 166
 167 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 168 {
 169     PCII440FXState *d = opaque;
 170     PCIDevice *pd = PCI_DEVICE(d);
 171     int ret, i;
 172
 173     ret = pci_device_load(pd, f);
 174     if (ret < 0)
 175         return ret;
 176     i440fx_update_memory_mappings(d);
 177     qemu_get_8s(f, &d->smm_enabled);
 178
 179     if (version_id == 2) {
 180         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 181             qemu_get_be32(f); /* dummy load for compatibility */
 182         }
 183     }
 184
 185     return 0;
 186 }
 187
 188 static int i440fx_post_load(void *opaque, int version_id)
 189 {
 190     PCII440FXState *d = opaque;
 191
 192     i440fx_update_memory_mappings(d);
 193     return 0;
 194 }
 195
 196 static const VMStateDescription vmstate_i440fx = {
 197     .name = "I440FX",
 198     .version_id = 3,
 199     .minimum_version_id = 3,
 200     .minimum_version_id_old = 1,
 201     .load_state_old = i440fx_load_old,
 202     .post_load = i440fx_post_load,
 203     .fields      = (VMStateField []) {
 204         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 205         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 206         VMSTATE_END_OF_LIST()
 207     }
 208 };
 209
 210 static void i440fx_pcihost_initfn(Object *obj)
 211 {
 212     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 213
 214     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 215                           "pci-conf-idx", 4);
 216     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 217                           "pci-conf-data", 4);
 218 }
 219
 220 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 221 {
 222     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 223     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 224
 225     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 226     sysbus_init_ioports(sbd, 0xcf8, 4);
 227
 228     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 229     sysbus_init_ioports(sbd, 0xcfc, 4);
 230 }
 231
 232 static int i440fx_initfn(PCIDevice *dev)
 233 {
 234     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 235
 236     dev->config[I440FX_SMRAM] = 0x02;
 237
 238     cpu_smm_register(&i440fx_set_smm, d);
 239     return 0;
 240 }
 241
 242 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
 243                     int *piix3_devfn,
 244                     ISABus **isa_bus, qemu_irq *pic,
 245                     MemoryRegion *address_space_mem,
 246                     MemoryRegion *address_space_io,
 247                     ram_addr_t ram_size,
 248                     hwaddr pci_hole_start,
 249                     hwaddr pci_hole_size,
 250                     hwaddr pci_hole64_start,
 251                     hwaddr pci_hole64_size,
 252                     MemoryRegion *pci_address_space,
 253                     MemoryRegion *ram_memory)
 254 {
 255     DeviceState *dev;
 256     PCIBus *b;
 257     PCIDevice *d;
 258     PCIHostState *s;
 259     PIIX3State *piix3;
 260     PCII440FXState *f;
 261     unsigned i;
 262
 263     dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
 264     s = PCI_HOST_BRIDGE(dev);
 265     b = pci_bus_new(dev, NULL, pci_address_space,
 266                     address_space_io, 0, TYPE_PCI_BUS);
 267     s->bus = b;
 268     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 269     qdev_init_nofail(dev);
 270
 271     d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
 272     *pi440fx_state = I440FX_PCI_DEVICE(d);
 273     f = *pi440fx_state;
 274     f->system_memory = address_space_mem;
 275     f->pci_address_space = pci_address_space;
 276     f->ram_memory = ram_memory;
 277     memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space,
 278                              pci_hole_start, pci_hole_size);
 279     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 280     memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
 281                              f->pci_address_space,
 282                              pci_hole64_start, pci_hole64_size);
 283     if (pci_hole64_size) {
 284         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 285                                     &f->pci_hole_64bit);
 286     }
 287     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 288                              f->pci_address_space, 0xa0000, 0x20000);
 289     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 290                                         &f->smram_region, 1);
 291     memory_region_set_enabled(&f->smram_region, false);
 292     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 293              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 294     for (i = 0; i < 12; ++i) {
 295         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 296                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 297                  PAM_EXPAN_SIZE);
 298     }
 299
 300     /* Xen supports additional interrupt routes from the PCI devices to
 301      * the IOAPIC: the four pins of each PCI device on the bus are also
 302      * connected to the IOAPIC directly.
 303      * These additional routes can be discovered through ACPI. */
 304     if (xen_enabled()) {
 305         piix3 = DO_UPCAST(PIIX3State, dev,
 306                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 307         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 308                 piix3, XEN_PIIX_NUM_PIRQS);
 309     } else {
 310         piix3 = DO_UPCAST(PIIX3State, dev,
 311                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 312         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 313                 PIIX_NUM_PIRQS);
 314         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 315     }
 316     piix3->pic = pic;
 317     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 318
 319     *piix3_devfn = piix3->dev.devfn;
 320
 321     ram_size = ram_size / 8 / 1024 / 1024;
 322     if (ram_size > 255) {
 323         ram_size = 255;
 324     }
 325     d->config[0x57] = ram_size;
 326
 327     i440fx_update_memory_mappings(f);
 328
 329     return b;
 330 }
 331
 332 /* PIIX3 PCI to ISA bridge */
 333 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 334 {
 335     qemu_set_irq(piix3->pic[pic_irq],
 336                  !!(piix3->pic_levels &
 337                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 338                      (pic_irq * PIIX_NUM_PIRQS))));
 339 }
 340
 341 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 342 {
 343     int pic_irq;
 344     uint64_t mask;
 345
 346     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 347     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 348         return;
 349     }
 350
 351     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 352     piix3->pic_levels &= ~mask;
 353     piix3->pic_levels |= mask * !!level;
 354
 355     piix3_set_irq_pic(piix3, pic_irq);
 356 }
 357
 358 static void piix3_set_irq(void *opaque, int pirq, int level)
 359 {
 360     PIIX3State *piix3 = opaque;
 361     piix3_set_irq_level(piix3, pirq, level);
 362 }
 363
 364 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 365 {
 366     PIIX3State *piix3 = opaque;
 367     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 368     PCIINTxRoute route;
 369
 370     if (irq < PIIX_NUM_PIC_IRQS) {
 371         route.mode = PCI_INTX_ENABLED;
 372         route.irq = irq;
 373     } else {
 374         route.mode = PCI_INTX_DISABLED;
 375         route.irq = -1;
 376     }
 377     return route;
 378 }
 379
 380 /* irq routing is changed. so rebuild bitmap */
 381 static void piix3_update_irq_levels(PIIX3State *piix3)
 382 {
 383     int pirq;
 384
 385     piix3->pic_levels = 0;
 386     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 387         piix3_set_irq_level(piix3, pirq,
 388                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 389     }
 390 }
 391
 392 static void piix3_write_config(PCIDevice *dev,
 393                                uint32_t address, uint32_t val, int len)
 394 {
 395     pci_default_write_config(dev, address, val, len);
 396     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 397         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 398         int pic_irq;
 399
 400         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 401         piix3_update_irq_levels(piix3);
 402         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 403             piix3_set_irq_pic(piix3, pic_irq);
 404         }
 405     }
 406 }
 407
 408 static void piix3_write_config_xen(PCIDevice *dev,
 409                                uint32_t address, uint32_t val, int len)
 410 {
 411     xen_piix_pci_write_config_client(address, val, len);
 412     piix3_write_config(dev, address, val, len);
 413 }
 414
 415 static void piix3_reset(void *opaque)
 416 {
 417     PIIX3State *d = opaque;
 418     uint8_t *pci_conf = d->dev.config;
 419
 420     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 421     pci_conf[0x05] = 0x00;
 422     pci_conf[0x06] = 0x00;
 423     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 424     pci_conf[0x4c] = 0x4d;
 425     pci_conf[0x4e] = 0x03;
 426     pci_conf[0x4f] = 0x00;
 427     pci_conf[0x60] = 0x80;
 428     pci_conf[0x61] = 0x80;
 429     pci_conf[0x62] = 0x80;
 430     pci_conf[0x63] = 0x80;
 431     pci_conf[0x69] = 0x02;
 432     pci_conf[0x70] = 0x80;
 433     pci_conf[0x76] = 0x0c;
 434     pci_conf[0x77] = 0x0c;
 435     pci_conf[0x78] = 0x02;
 436     pci_conf[0x79] = 0x00;
 437     pci_conf[0x80] = 0x00;
 438     pci_conf[0x82] = 0x00;
 439     pci_conf[0xa0] = 0x08;
 440     pci_conf[0xa2] = 0x00;
 441     pci_conf[0xa3] = 0x00;
 442     pci_conf[0xa4] = 0x00;
 443     pci_conf[0xa5] = 0x00;
 444     pci_conf[0xa6] = 0x00;
 445     pci_conf[0xa7] = 0x00;
 446     pci_conf[0xa8] = 0x0f;
 447     pci_conf[0xaa] = 0x00;
 448     pci_conf[0xab] = 0x00;
 449     pci_conf[0xac] = 0x00;
 450     pci_conf[0xae] = 0x00;
 451
 452     d->pic_levels = 0;
 453     d->rcr = 0;
 454 }
 455
 456 static int piix3_post_load(void *opaque, int version_id)
 457 {
 458     PIIX3State *piix3 = opaque;
 459     piix3_update_irq_levels(piix3);
 460     return 0;
 461 }
 462
 463 static void piix3_pre_save(void *opaque)
 464 {
 465     int i;
 466     PIIX3State *piix3 = opaque;
 467
 468     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 469         piix3->pci_irq_levels_vmstate[i] =
 470             pci_bus_get_irq_level(piix3->dev.bus, i);
 471     }
 472 }
 473
 474 static bool piix3_rcr_needed(void *opaque)
 475 {
 476     PIIX3State *piix3 = opaque;
 477
 478     return (piix3->rcr != 0);
 479 }
 480
 481 static const VMStateDescription vmstate_piix3_rcr = {
 482     .name = "PIIX3/rcr",
 483     .version_id = 1,
 484     .minimum_version_id = 1,
 485     .fields = (VMStateField []) {
 486         VMSTATE_UINT8(rcr, PIIX3State),
 487         VMSTATE_END_OF_LIST()
 488     }
 489 };
 490
 491 static const VMStateDescription vmstate_piix3 = {
 492     .name = "PIIX3",
 493     .version_id = 3,
 494     .minimum_version_id = 2,
 495     .minimum_version_id_old = 2,
 496     .post_load = piix3_post_load,
 497     .pre_save = piix3_pre_save,
 498     .fields      = (VMStateField[]) {
 499         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 500         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 501                               PIIX_NUM_PIRQS, 3),
 502         VMSTATE_END_OF_LIST()
 503     },
 504     .subsections = (VMStateSubsection[]) {
 505         {
 506             .vmsd = &vmstate_piix3_rcr,
 507             .needed = piix3_rcr_needed,
 508         },
 509         { 0 }
 510     }
 511 };
 512
 513
 514 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 515 {
 516     PIIX3State *d = opaque;
 517
 518     if (val & 4) {
 519         qemu_system_reset_request();
 520         return;
 521     }
 522     d->rcr = val & 2; /* keep System Reset type only */
 523 }
 524
 525 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 526 {
 527     PIIX3State *d = opaque;
 528
 529     return d->rcr;
 530 }
 531
 532 static const MemoryRegionOps rcr_ops = {
 533     .read = rcr_read,
 534     .write = rcr_write,
 535     .endianness = DEVICE_LITTLE_ENDIAN
 536 };
 537
 538 static int piix3_initfn(PCIDevice *dev)
 539 {
 540     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 541
 542     isa_bus_new(DEVICE(d), pci_address_space_io(dev));
 543
 544     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 545                           "piix3-reset-control", 1);
 546     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 547                                         &d->rcr_mem, 1);
 548
 549     qemu_register_reset(piix3_reset, d);
 550     return 0;
 551 }
 552
 553 static void piix3_class_init(ObjectClass *klass, void *data)
 554 {
 555     DeviceClass *dc = DEVICE_CLASS(klass);
 556     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 557
 558     dc->desc        = "ISA bridge";
 559     dc->vmsd        = &vmstate_piix3;
 560     dc->no_user     = 1,
 561     k->no_hotplug   = 1;
 562     k->init         = piix3_initfn;
 563     k->config_write = piix3_write_config;
 564     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 565     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 566     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 567     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 568 }
 569
 570 static const TypeInfo piix3_info = {
 571     .name          = "PIIX3",
 572     .parent        = TYPE_PCI_DEVICE,
 573     .instance_size = sizeof(PIIX3State),
 574     .class_init    = piix3_class_init,
 575 };
 576
 577 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 578 {
 579     DeviceClass *dc = DEVICE_CLASS(klass);
 580     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 581
 582     dc->desc        = "ISA bridge";
 583     dc->vmsd        = &vmstate_piix3;
 584     dc->no_user     = 1;
 585     k->no_hotplug   = 1;
 586     k->init         = piix3_initfn;
 587     k->config_write = piix3_write_config_xen;
 588     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 589     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 590     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 591     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 592 };
 593
 594 static const TypeInfo piix3_xen_info = {
 595     .name          = "PIIX3-xen",
 596     .parent        = TYPE_PCI_DEVICE,
 597     .instance_size = sizeof(PIIX3State),
 598     .class_init    = piix3_xen_class_init,
 599 };
 600
 601 static void i440fx_class_init(ObjectClass *klass, void *data)
 602 {
 603     DeviceClass *dc = DEVICE_CLASS(klass);
 604     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 605
 606     k->no_hotplug = 1;
 607     k->init = i440fx_initfn;
 608     k->config_write = i440fx_write_config;
 609     k->vendor_id = PCI_VENDOR_ID_INTEL;
 610     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 611     k->revision = 0x02;
 612     k->class_id = PCI_CLASS_BRIDGE_HOST;
 613     dc->desc = "Host bridge";
 614     dc->no_user = 1;
 615     dc->vmsd = &vmstate_i440fx;
 616 }
 617
 618 static const TypeInfo i440fx_info = {
 619     .name          = TYPE_I440FX_PCI_DEVICE,
 620     .parent        = TYPE_PCI_DEVICE,
 621     .instance_size = sizeof(PCII440FXState),
 622     .class_init    = i440fx_class_init,
 623 };
 624
 625 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 626                                                 PCIBus *rootbus)
 627 {
 628     /* For backwards compat with old device paths */
 629     return "0000";
 630 }
 631
 632 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 633 {
 634     DeviceClass *dc = DEVICE_CLASS(klass);
 635     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 636
 637     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 638     dc->realize = i440fx_pcihost_realize;
 639     dc->fw_name = "pci";
 640     dc->no_user = 1;
 641 }
 642
 643 static const TypeInfo i440fx_pcihost_info = {
 644     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 645     .parent        = TYPE_PCI_HOST_BRIDGE,
 646     .instance_size = sizeof(I440FXState),
 647     .instance_init = i440fx_pcihost_initfn,
 648     .class_init    = i440fx_pcihost_class_init,
 649 };
 650
 651 static void i440fx_register_types(void)
 652 {
 653     type_register_static(&i440fx_info);
 654     type_register_static(&piix3_info);
 655     type_register_static(&piix3_xen_info);
 656     type_register_static(&i440fx_pcihost_info);
 657 }
 658
 659 type_init(i440fx_register_types)