hw/pci-host/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on piix_pci.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/pci-host/q35.h"
  32
  33 /****************************************************************************
  34  * Q35 host
  35  */
  36
  37 static int q35_host_init(SysBusDevice *dev)
  38 {
  39     PCIBus *b;
  40     PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
  41     Q35PCIHost *s = Q35_HOST_DEVICE(&dev->qdev);
  42
  43     memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci,
  44                           "pci-conf-idx", 4);
  45     sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  46     sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  47
  48     memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci,
  49                           "pci-conf-data", 4);
  50     sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  51     sysbus_init_ioports(&pci->busdev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  52
  53     if (pcie_host_init(&s->host) < 0) {
  54         return -1;
  55     }
  56     b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0",
  57                     s->mch.pci_address_space, s->mch.address_space_io,
  58                     0, TYPE_PCIE_BUS);
  59     s->host.pci.bus = b;
  60     qdev_set_parent_bus(DEVICE(&s->mch), BUS(b));
  61     qdev_init_nofail(DEVICE(&s->mch));
  62
  63     return 0;
  64 }
  65
  66 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
  67                                           PCIBus *rootbus)
  68 {
  69     /* For backwards compat with old device paths */
  70     return "0000";
  71 }
  72
  73 static Property mch_props[] = {
  74     DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
  75                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
  76     DEFINE_PROP_END_OF_LIST(),
  77 };
  78
  79 static void q35_host_class_init(ObjectClass *klass, void *data)
  80 {
  81     DeviceClass *dc = DEVICE_CLASS(klass);
  82     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
  83     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
  84
  85     hc->root_bus_path = q35_host_root_bus_path;
  86     k->init = q35_host_init;
  87     dc->props = mch_props;
  88     dc->fw_name = "pci";
  89 }
  90
  91 static void q35_host_initfn(Object *obj)
  92 {
  93     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  94
  95     object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
  96     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
  97     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
  98     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
  99 }
 100
 101 static const TypeInfo q35_host_info = {
 102     .name       = TYPE_Q35_HOST_DEVICE,
 103     .parent     = TYPE_PCIE_HOST_BRIDGE,
 104     .instance_size = sizeof(Q35PCIHost),
 105     .instance_init = q35_host_initfn,
 106     .class_init = q35_host_class_init,
 107 };
 108
 109 /****************************************************************************
 110  * MCH D0:F0
 111  */
 112
 113 /* PCIe MMCFG */
 114 static void mch_update_pciexbar(MCHPCIState *mch)
 115 {
 116     PCIDevice *pci_dev = &mch->d;
 117     BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
 118     DeviceState *qdev = bus->parent;
 119     Q35PCIHost *s = Q35_HOST_DEVICE(qdev);
 120
 121     uint64_t pciexbar;
 122     int enable;
 123     uint64_t addr;
 124     uint64_t addr_mask;
 125     uint32_t length;
 126
 127     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 128     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 129     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 130     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 131     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 132         length = 256 * 1024 * 1024;
 133         break;
 134     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 135         length = 128 * 1024 * 1024;
 136         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 137             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 138         break;
 139     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 140         length = 64 * 1024 * 1024;
 141         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 142         break;
 143     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 144     default:
 145         enable = 0;
 146         length = 0;
 147         abort();
 148         break;
 149     }
 150     addr = pciexbar & addr_mask;
 151     pcie_host_mmcfg_update(&s->host, enable, addr, length);
 152 }
 153
 154 /* PAM */
 155 static void mch_update_pam(MCHPCIState *mch)
 156 {
 157     int i;
 158
 159     memory_region_transaction_begin();
 160     for (i = 0; i < 13; i++) {
 161         pam_update(&mch->pam_regions[i], i,
 162                    mch->d.config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
 163     }
 164     memory_region_transaction_commit();
 165 }
 166
 167 /* SMRAM */
 168 static void mch_update_smram(MCHPCIState *mch)
 169 {
 170     memory_region_transaction_begin();
 171     smram_update(&mch->smram_region, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
 172                     mch->smm_enabled);
 173     memory_region_transaction_commit();
 174 }
 175
 176 static void mch_set_smm(int smm, void *arg)
 177 {
 178     MCHPCIState *mch = arg;
 179
 180     memory_region_transaction_begin();
 181     smram_set_smm(&mch->smm_enabled, smm, mch->d.config[MCH_HOST_BRDIGE_SMRAM],
 182                     &mch->smram_region);
 183     memory_region_transaction_commit();
 184 }
 185
 186 static void mch_write_config(PCIDevice *d,
 187                               uint32_t address, uint32_t val, int len)
 188 {
 189     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 190
 191     /* XXX: implement SMRAM.D_LOCK */
 192     pci_default_write_config(d, address, val, len);
 193
 194     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 195                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 196         mch_update_pam(mch);
 197     }
 198
 199     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 200                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 201         mch_update_pciexbar(mch);
 202     }
 203
 204     if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
 205                        MCH_HOST_BRDIGE_SMRAM_SIZE)) {
 206         mch_update_smram(mch);
 207     }
 208 }
 209
 210 static void mch_update(MCHPCIState *mch)
 211 {
 212     mch_update_pciexbar(mch);
 213     mch_update_pam(mch);
 214     mch_update_smram(mch);
 215 }
 216
 217 static int mch_post_load(void *opaque, int version_id)
 218 {
 219     MCHPCIState *mch = opaque;
 220     mch_update(mch);
 221     return 0;
 222 }
 223
 224 static const VMStateDescription vmstate_mch = {
 225     .name = "mch",
 226     .version_id = 1,
 227     .minimum_version_id = 1,
 228     .minimum_version_id_old = 1,
 229     .post_load = mch_post_load,
 230     .fields = (VMStateField []) {
 231         VMSTATE_PCI_DEVICE(d, MCHPCIState),
 232         VMSTATE_UINT8(smm_enabled, MCHPCIState),
 233         VMSTATE_END_OF_LIST()
 234     }
 235 };
 236
 237 static void mch_reset(DeviceState *qdev)
 238 {
 239     PCIDevice *d = PCI_DEVICE(qdev);
 240     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 241
 242     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 243                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 244
 245     d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 246
 247     mch_update(mch);
 248 }
 249
 250 static int mch_init(PCIDevice *d)
 251 {
 252     int i;
 253     hwaddr pci_hole64_size;
 254     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 255
 256     /* Leave enough space for the biggest MCFG BAR */
 257     /* TODO: this matches current bios behaviour, but
 258      * it's not a power of two, which means an MTRR
 259      * can't cover it exactly.
 260      */
 261     mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
 262         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
 263
 264     /* setup pci memory regions */
 265     memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
 266                              mch->pci_address_space,
 267                              mch->below_4g_mem_size,
 268                              0x100000000ULL - mch->below_4g_mem_size);
 269     memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
 270                                 &mch->pci_hole);
 271     pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
 272                        ((uint64_t)1 << 62));
 273     memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
 274                              mch->pci_address_space,
 275                              0x100000000ULL + mch->above_4g_mem_size,
 276                              pci_hole64_size);
 277     if (pci_hole64_size) {
 278         memory_region_add_subregion(mch->system_memory,
 279                                     0x100000000ULL + mch->above_4g_mem_size,
 280                                     &mch->pci_hole_64bit);
 281     }
 282     /* smram */
 283     cpu_smm_register(&mch_set_smm, mch);
 284     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
 285                              mch->pci_address_space, 0xa0000, 0x20000);
 286     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 287                                         &mch->smram_region, 1);
 288     memory_region_set_enabled(&mch->smram_region, false);
 289     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
 290              &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 291     for (i = 0; i < 12; ++i) {
 292         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
 293                  &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 294                  PAM_EXPAN_SIZE);
 295     }
 296     return 0;
 297 }
 298
 299 static void mch_class_init(ObjectClass *klass, void *data)
 300 {
 301     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 302     DeviceClass *dc = DEVICE_CLASS(klass);
 303
 304     k->init = mch_init;
 305     k->config_write = mch_write_config;
 306     dc->reset = mch_reset;
 307     dc->desc = "Host bridge";
 308     dc->vmsd = &vmstate_mch;
 309     k->vendor_id = PCI_VENDOR_ID_INTEL;
 310     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 311     k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
 312     k->class_id = PCI_CLASS_BRIDGE_HOST;
 313 }
 314
 315 static const TypeInfo mch_info = {
 316     .name = TYPE_MCH_PCI_DEVICE,
 317     .parent = TYPE_PCI_DEVICE,
 318     .instance_size = sizeof(MCHPCIState),
 319     .class_init = mch_class_init,
 320 };
 321
 322 static void q35_register(void)
 323 {
 324     type_register_static(&mch_info);
 325     type_register_static(&q35_host_info);
 326 }
 327
 328 type_init(q35_register);