hw/pci-host/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on piix_pci.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/pci-host/q35.h"
  32
  33 /****************************************************************************
  34  * Q35 host
  35  */
  36
  37 static void q35_host_realize(DeviceState *dev, Error **errp)
  38 {
  39     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  40     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
  41     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  42
  43     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  44     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  45
  46     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  47     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  48
  49     if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
  50         error_setg(errp, "failed to initialize pcie host");
  51         return;
  52     }
  53     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
  54                            s->mch.pci_address_space, s->mch.address_space_io,
  55                            0, TYPE_PCIE_BUS);
  56     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
  57     qdev_init_nofail(DEVICE(&s->mch));
  58 }
  59
  60 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
  61                                           PCIBus *rootbus)
  62 {
  63     /* For backwards compat with old device paths */
  64     return "0000";
  65 }
  66
  67 static Property mch_props[] = {
  68     DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
  69                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
  70     DEFINE_PROP_END_OF_LIST(),
  71 };
  72
  73 static void q35_host_class_init(ObjectClass *klass, void *data)
  74 {
  75     DeviceClass *dc = DEVICE_CLASS(klass);
  76     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
  77
  78     hc->root_bus_path = q35_host_root_bus_path;
  79     dc->realize = q35_host_realize;
  80     dc->props = mch_props;
  81     dc->fw_name = "pci";
  82 }
  83
  84 static void q35_host_initfn(Object *obj)
  85 {
  86     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  87     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
  88
  89     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
  90                           "pci-conf-idx", 4);
  91     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
  92                           "pci-conf-data", 4);
  93
  94     object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
  95     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
  96     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
  97     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
  98 }
  99
 100 static const TypeInfo q35_host_info = {
 101     .name       = TYPE_Q35_HOST_DEVICE,
 102     .parent     = TYPE_PCIE_HOST_BRIDGE,
 103     .instance_size = sizeof(Q35PCIHost),
 104     .instance_init = q35_host_initfn,
 105     .class_init = q35_host_class_init,
 106 };
 107
 108 /****************************************************************************
 109  * MCH D0:F0
 110  */
 111
 112 /* PCIe MMCFG */
 113 static void mch_update_pciexbar(MCHPCIState *mch)
 114 {
 115     PCIDevice *pci_dev = PCI_DEVICE(mch);
 116     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
 117     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
 118
 119     uint64_t pciexbar;
 120     int enable;
 121     uint64_t addr;
 122     uint64_t addr_mask;
 123     uint32_t length;
 124
 125     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 126     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 127     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 128     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 129     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 130         length = 256 * 1024 * 1024;
 131         break;
 132     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 133         length = 128 * 1024 * 1024;
 134         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 135             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 136         break;
 137     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 138         length = 64 * 1024 * 1024;
 139         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 140         break;
 141     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 142     default:
 143         enable = 0;
 144         length = 0;
 145         abort();
 146         break;
 147     }
 148     addr = pciexbar & addr_mask;
 149     pcie_host_mmcfg_update(pehb, enable, addr, length);
 150 }
 151
 152 /* PAM */
 153 static void mch_update_pam(MCHPCIState *mch)
 154 {
 155     PCIDevice *pd = PCI_DEVICE(mch);
 156     int i;
 157
 158     memory_region_transaction_begin();
 159     for (i = 0; i < 13; i++) {
 160         pam_update(&mch->pam_regions[i], i,
 161                    pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
 162     }
 163     memory_region_transaction_commit();
 164 }
 165
 166 /* SMRAM */
 167 static void mch_update_smram(MCHPCIState *mch)
 168 {
 169     PCIDevice *pd = PCI_DEVICE(mch);
 170
 171     memory_region_transaction_begin();
 172     smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
 173                     mch->smm_enabled);
 174     memory_region_transaction_commit();
 175 }
 176
 177 static void mch_set_smm(int smm, void *arg)
 178 {
 179     MCHPCIState *mch = arg;
 180     PCIDevice *pd = PCI_DEVICE(mch);
 181
 182     memory_region_transaction_begin();
 183     smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
 184                     &mch->smram_region);
 185     memory_region_transaction_commit();
 186 }
 187
 188 static void mch_write_config(PCIDevice *d,
 189                               uint32_t address, uint32_t val, int len)
 190 {
 191     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 192
 193     /* XXX: implement SMRAM.D_LOCK */
 194     pci_default_write_config(d, address, val, len);
 195
 196     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 197                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 198         mch_update_pam(mch);
 199     }
 200
 201     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 202                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 203         mch_update_pciexbar(mch);
 204     }
 205
 206     if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
 207                        MCH_HOST_BRDIGE_SMRAM_SIZE)) {
 208         mch_update_smram(mch);
 209     }
 210 }
 211
 212 static void mch_update(MCHPCIState *mch)
 213 {
 214     mch_update_pciexbar(mch);
 215     mch_update_pam(mch);
 216     mch_update_smram(mch);
 217 }
 218
 219 static int mch_post_load(void *opaque, int version_id)
 220 {
 221     MCHPCIState *mch = opaque;
 222     mch_update(mch);
 223     return 0;
 224 }
 225
 226 static const VMStateDescription vmstate_mch = {
 227     .name = "mch",
 228     .version_id = 1,
 229     .minimum_version_id = 1,
 230     .minimum_version_id_old = 1,
 231     .post_load = mch_post_load,
 232     .fields = (VMStateField []) {
 233         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
 234         VMSTATE_UINT8(smm_enabled, MCHPCIState),
 235         VMSTATE_END_OF_LIST()
 236     }
 237 };
 238
 239 static void mch_reset(DeviceState *qdev)
 240 {
 241     PCIDevice *d = PCI_DEVICE(qdev);
 242     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 243
 244     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 245                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 246
 247     d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 248
 249     mch_update(mch);
 250 }
 251
 252 static int mch_init(PCIDevice *d)
 253 {
 254     int i;
 255     hwaddr pci_hole64_size;
 256     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 257
 258     /* Leave enough space for the biggest MCFG BAR */
 259     /* TODO: this matches current bios behaviour, but
 260      * it's not a power of two, which means an MTRR
 261      * can't cover it exactly.
 262      */
 263     mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
 264         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
 265
 266     /* setup pci memory regions */
 267     memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
 268                              mch->pci_address_space,
 269                              mch->below_4g_mem_size,
 270                              0x100000000ULL - mch->below_4g_mem_size);
 271     memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
 272                                 &mch->pci_hole);
 273     pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
 274                        ((uint64_t)1 << 62));
 275     memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
 276                              mch->pci_address_space,
 277                              0x100000000ULL + mch->above_4g_mem_size,
 278                              pci_hole64_size);
 279     if (pci_hole64_size) {
 280         memory_region_add_subregion(mch->system_memory,
 281                                     0x100000000ULL + mch->above_4g_mem_size,
 282                                     &mch->pci_hole_64bit);
 283     }
 284     /* smram */
 285     cpu_smm_register(&mch_set_smm, mch);
 286     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
 287                              mch->pci_address_space, 0xa0000, 0x20000);
 288     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 289                                         &mch->smram_region, 1);
 290     memory_region_set_enabled(&mch->smram_region, false);
 291     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
 292              &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 293     for (i = 0; i < 12; ++i) {
 294         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
 295                  &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 296                  PAM_EXPAN_SIZE);
 297     }
 298     return 0;
 299 }
 300
 301 static void mch_class_init(ObjectClass *klass, void *data)
 302 {
 303     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 304     DeviceClass *dc = DEVICE_CLASS(klass);
 305
 306     k->init = mch_init;
 307     k->config_write = mch_write_config;
 308     dc->reset = mch_reset;
 309     dc->desc = "Host bridge";
 310     dc->vmsd = &vmstate_mch;
 311     k->vendor_id = PCI_VENDOR_ID_INTEL;
 312     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 313     k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
 314     k->class_id = PCI_CLASS_BRIDGE_HOST;
 315 }
 316
 317 static const TypeInfo mch_info = {
 318     .name = TYPE_MCH_PCI_DEVICE,
 319     .parent = TYPE_PCI_DEVICE,
 320     .instance_size = sizeof(MCHPCIState),
 321     .class_init = mch_class_init,
 322 };
 323
 324 static void q35_register(void)
 325 {
 326     type_register_static(&mch_info);
 327     type_register_static(&q35_host_info);
 328 }
 329
 330 type_init(q35_register);