hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "loader.h"
  30 #include "qemu-objects.h"
  31
  32 //#define DEBUG_PCI
  33 #ifdef DEBUG_PCI
  34 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  35 #else
  36 # define PCI_DPRINTF(format, ...)       do { } while (0)
  37 #endif
  38
  39 struct PCIBus {
  40     BusState qbus;
  41     int devfn_min;
  42     pci_set_irq_fn set_irq;
  43     pci_map_irq_fn map_irq;
  44     pci_hotplug_fn hotplug;
  45     DeviceState *hotplug_qdev;
  46     void *irq_opaque;
  47     PCIDevice *devices[256];
  48     PCIDevice *parent_dev;
  49     target_phys_addr_t mem_base;
  50
  51     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  52     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  53
  54     /* The bus IRQ state is the logical OR of the connected devices.
  55        Keep a count of the number of devices with raised IRQs.  */
  56     int nirq;
  57     int *irq_count;
  58 };
  59
  60 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  61 static char *pcibus_get_dev_path(DeviceState *dev);
  62
  63 static struct BusInfo pci_bus_info = {
  64     .name       = "PCI",
  65     .size       = sizeof(PCIBus),
  66     .print_dev  = pcibus_dev_print,
  67     .get_dev_path = pcibus_get_dev_path,
  68     .props      = (Property[]) {
  69         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  70         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
  71         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
  72         DEFINE_PROP_END_OF_LIST()
  73     }
  74 };
  75
  76 static void pci_update_mappings(PCIDevice *d);
  77 static void pci_set_irq(void *opaque, int irq_num, int level);
  78 static int pci_add_option_rom(PCIDevice *pdev);
  79
  80 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  81 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  82
  83 struct PCIHostBus {
  84     int domain;
  85     struct PCIBus *bus;
  86     QLIST_ENTRY(PCIHostBus) next;
  87 };
  88 static QLIST_HEAD(, PCIHostBus) host_buses;
  89
  90 static const VMStateDescription vmstate_pcibus = {
  91     .name = "PCIBUS",
  92     .version_id = 1,
  93     .minimum_version_id = 1,
  94     .minimum_version_id_old = 1,
  95     .fields      = (VMStateField []) {
  96         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  97         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  98         VMSTATE_END_OF_LIST()
  99     }
 100 };
 101
 102 static int pci_bar(PCIDevice *d, int reg)
 103 {
 104     uint8_t type;
 105
 106     if (reg != PCI_ROM_SLOT)
 107         return PCI_BASE_ADDRESS_0 + reg * 4;
 108
 109     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 110     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 111 }
 112
 113 static inline int pci_irq_state(PCIDevice *d, int irq_num)
 114 {
 115         return (d->irq_state >> irq_num) & 0x1;
 116 }
 117
 118 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 119 {
 120         d->irq_state &= ~(0x1 << irq_num);
 121         d->irq_state |= level << irq_num;
 122 }
 123
 124 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 125 {
 126     PCIBus *bus;
 127     for (;;) {
 128         bus = pci_dev->bus;
 129         irq_num = bus->map_irq(pci_dev, irq_num);
 130         if (bus->set_irq)
 131             break;
 132         pci_dev = bus->parent_dev;
 133     }
 134     bus->irq_count[irq_num] += change;
 135     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 136 }
 137
 138 /* Update interrupt status bit in config space on interrupt
 139  * state change. */
 140 static void pci_update_irq_status(PCIDevice *dev)
 141 {
 142     if (dev->irq_state) {
 143         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 144     } else {
 145         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 146     }
 147 }
 148
 149 static void pci_device_reset(PCIDevice *dev)
 150 {
 151     int r;
 152
 153     dev->irq_state = 0;
 154     pci_update_irq_status(dev);
 155     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 156                                   PCI_COMMAND_MASTER);
 157     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 158     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 159     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 160         if (!dev->io_regions[r].size) {
 161             continue;
 162         }
 163         pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
 164     }
 165     pci_update_mappings(dev);
 166 }
 167
 168 static void pci_bus_reset(void *opaque)
 169 {
 170     PCIBus *bus = opaque;
 171     int i;
 172
 173     for (i = 0; i < bus->nirq; i++) {
 174         bus->irq_count[i] = 0;
 175     }
 176     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 177         if (bus->devices[i]) {
 178             pci_device_reset(bus->devices[i]);
 179         }
 180     }
 181 }
 182
 183 static void pci_host_bus_register(int domain, PCIBus *bus)
 184 {
 185     struct PCIHostBus *host;
 186     host = qemu_mallocz(sizeof(*host));
 187     host->domain = domain;
 188     host->bus = bus;
 189     QLIST_INSERT_HEAD(&host_buses, host, next);
 190 }
 191
 192 PCIBus *pci_find_root_bus(int domain)
 193 {
 194     struct PCIHostBus *host;
 195
 196     QLIST_FOREACH(host, &host_buses, next) {
 197         if (host->domain == domain) {
 198             return host->bus;
 199         }
 200     }
 201
 202     return NULL;
 203 }
 204
 205 int pci_find_domain(const PCIBus *bus)
 206 {
 207     PCIDevice *d;
 208     struct PCIHostBus *host;
 209
 210     /* obtain root bus */
 211     while ((d = bus->parent_dev) != NULL) {
 212         bus = d->bus;
 213     }
 214
 215     QLIST_FOREACH(host, &host_buses, next) {
 216         if (host->bus == bus) {
 217             return host->domain;
 218         }
 219     }
 220
 221     abort();    /* should not be reached */
 222     return -1;
 223 }
 224
 225 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 226                          const char *name, int devfn_min)
 227 {
 228     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 229     bus->devfn_min = devfn_min;
 230
 231     /* host bridge */
 232     QLIST_INIT(&bus->child);
 233     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 234
 235     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
 236     qemu_register_reset(pci_bus_reset, bus);
 237 }
 238
 239 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 240 {
 241     PCIBus *bus;
 242
 243     bus = qemu_mallocz(sizeof(*bus));
 244     bus->qbus.qdev_allocated = 1;
 245     pci_bus_new_inplace(bus, parent, name, devfn_min);
 246     return bus;
 247 }
 248
 249 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 250                   void *irq_opaque, int nirq)
 251 {
 252     bus->set_irq = set_irq;
 253     bus->map_irq = map_irq;
 254     bus->irq_opaque = irq_opaque;
 255     bus->nirq = nirq;
 256     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 257 }
 258
 259 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
 260 {
 261     bus->qbus.allow_hotplug = 1;
 262     bus->hotplug = hotplug;
 263     bus->hotplug_qdev = qdev;
 264 }
 265
 266 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
 267 {
 268     bus->mem_base = base;
 269 }
 270
 271 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 272                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 273                          void *irq_opaque, int devfn_min, int nirq)
 274 {
 275     PCIBus *bus;
 276
 277     bus = pci_bus_new(parent, name, devfn_min);
 278     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 279     return bus;
 280 }
 281
 282 static void pci_register_secondary_bus(PCIBus *parent,
 283                                        PCIBus *bus,
 284                                        PCIDevice *dev,
 285                                        pci_map_irq_fn map_irq,
 286                                        const char *name)
 287 {
 288     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 289     bus->map_irq = map_irq;
 290     bus->parent_dev = dev;
 291
 292     QLIST_INIT(&bus->child);
 293     QLIST_INSERT_HEAD(&parent->child, bus, sibling);
 294 }
 295
 296 static void pci_unregister_secondary_bus(PCIBus *bus)
 297 {
 298     assert(QLIST_EMPTY(&bus->child));
 299     QLIST_REMOVE(bus, sibling);
 300 }
 301
 302 int pci_bus_num(PCIBus *s)
 303 {
 304     if (!s->parent_dev)
 305         return 0;       /* pci host bridge */
 306     return s->parent_dev->config[PCI_SECONDARY_BUS];
 307 }
 308
 309 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 310 {
 311     PCIDevice *s = container_of(pv, PCIDevice, config);
 312     uint8_t *config;
 313     int i;
 314
 315     assert(size == pci_config_size(s));
 316     config = qemu_malloc(size);
 317
 318     qemu_get_buffer(f, config, size);
 319     for (i = 0; i < size; ++i) {
 320         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 321             qemu_free(config);
 322             return -EINVAL;
 323         }
 324     }
 325     memcpy(s->config, config, size);
 326
 327     pci_update_mappings(s);
 328
 329     qemu_free(config);
 330     return 0;
 331 }
 332
 333 /* just put buffer */
 334 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 335 {
 336     const uint8_t **v = pv;
 337     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 338     qemu_put_buffer(f, *v, size);
 339 }
 340
 341 static VMStateInfo vmstate_info_pci_config = {
 342     .name = "pci config",
 343     .get  = get_pci_config_device,
 344     .put  = put_pci_config_device,
 345 };
 346
 347 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 348 {
 349     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 350     uint32_t irq_state[PCI_NUM_PINS];
 351     int i;
 352     for (i = 0; i < PCI_NUM_PINS; ++i) {
 353         irq_state[i] = qemu_get_be32(f);
 354         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 355             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 356                     irq_state[i]);
 357             return -EINVAL;
 358         }
 359     }
 360
 361     for (i = 0; i < PCI_NUM_PINS; ++i) {
 362         pci_set_irq_state(s, i, irq_state[i]);
 363     }
 364
 365     return 0;
 366 }
 367
 368 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 369 {
 370     int i;
 371     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
 372
 373     for (i = 0; i < PCI_NUM_PINS; ++i) {
 374         qemu_put_be32(f, pci_irq_state(s, i));
 375     }
 376 }
 377
 378 static VMStateInfo vmstate_info_pci_irq_state = {
 379     .name = "pci irq state",
 380     .get  = get_pci_irq_state,
 381     .put  = put_pci_irq_state,
 382 };
 383
 384 const VMStateDescription vmstate_pci_device = {
 385     .name = "PCIDevice",
 386     .version_id = 2,
 387     .minimum_version_id = 1,
 388     .minimum_version_id_old = 1,
 389     .fields      = (VMStateField []) {
 390         VMSTATE_INT32_LE(version_id, PCIDevice),
 391         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 392                                    vmstate_info_pci_config,
 393                                    PCI_CONFIG_SPACE_SIZE),
 394         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 395                                    vmstate_info_pci_irq_state,
 396                                    PCI_NUM_PINS * sizeof(int32_t)),
 397         VMSTATE_END_OF_LIST()
 398     }
 399 };
 400
 401 const VMStateDescription vmstate_pcie_device = {
 402     .name = "PCIDevice",
 403     .version_id = 2,
 404     .minimum_version_id = 1,
 405     .minimum_version_id_old = 1,
 406     .fields      = (VMStateField []) {
 407         VMSTATE_INT32_LE(version_id, PCIDevice),
 408         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 409                                    vmstate_info_pci_config,
 410                                    PCIE_CONFIG_SPACE_SIZE),
 411         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 412                                    vmstate_info_pci_irq_state,
 413                                    PCI_NUM_PINS * sizeof(int32_t)),
 414         VMSTATE_END_OF_LIST()
 415     }
 416 };
 417
 418 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 419 {
 420     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 421 }
 422
 423 void pci_device_save(PCIDevice *s, QEMUFile *f)
 424 {
 425     /* Clear interrupt status bit: it is implicit
 426      * in irq_state which we are saving.
 427      * This makes us compatible with old devices
 428      * which never set or clear this bit. */
 429     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 430     vmstate_save_state(f, pci_get_vmstate(s), s);
 431     /* Restore the interrupt status bit. */
 432     pci_update_irq_status(s);
 433 }
 434
 435 int pci_device_load(PCIDevice *s, QEMUFile *f)
 436 {
 437     int ret;
 438     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 439     /* Restore the interrupt status bit. */
 440     pci_update_irq_status(s);
 441     return ret;
 442 }
 443
 444 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
 445 {
 446     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
 447                  pci_default_sub_vendor_id);
 448     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
 449                  pci_default_sub_device_id);
 450 }
 451
 452 /*
 453  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 454  */
 455 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 456 {
 457     const char *p;
 458     char *e;
 459     unsigned long val;
 460     unsigned long dom = 0, bus = 0;
 461     unsigned slot = 0;
 462
 463     p = addr;
 464     val = strtoul(p, &e, 16);
 465     if (e == p)
 466         return -1;
 467     if (*e == ':') {
 468         bus = val;
 469         p = e + 1;
 470         val = strtoul(p, &e, 16);
 471         if (e == p)
 472             return -1;
 473         if (*e == ':') {
 474             dom = bus;
 475             bus = val;
 476             p = e + 1;
 477             val = strtoul(p, &e, 16);
 478             if (e == p)
 479                 return -1;
 480         }
 481     }
 482
 483     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 484         return -1;
 485
 486     slot = val;
 487
 488     if (*e)
 489         return -1;
 490
 491     /* Note: QEMU doesn't implement domains other than 0 */
 492     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 493         return -1;
 494
 495     *domp = dom;
 496     *busp = bus;
 497     *slotp = slot;
 498     return 0;
 499 }
 500
 501 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 502                      unsigned *slotp)
 503 {
 504     /* strip legacy tag */
 505     if (!strncmp(addr, "pci_addr=", 9)) {
 506         addr += 9;
 507     }
 508     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 509         monitor_printf(mon, "Invalid pci address\n");
 510         return -1;
 511     }
 512     return 0;
 513 }
 514
 515 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 516 {
 517     int dom, bus;
 518     unsigned slot;
 519
 520     if (!devaddr) {
 521         *devfnp = -1;
 522         return pci_find_bus(pci_find_root_bus(0), 0);
 523     }
 524
 525     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 526         return NULL;
 527     }
 528
 529     *devfnp = slot << 3;
 530     return pci_find_bus(pci_find_root_bus(dom), bus);
 531 }
 532
 533 static void pci_init_cmask(PCIDevice *dev)
 534 {
 535     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 536     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 537     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 538     dev->cmask[PCI_REVISION_ID] = 0xff;
 539     dev->cmask[PCI_CLASS_PROG] = 0xff;
 540     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 541     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 542     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 543 }
 544
 545 static void pci_init_wmask(PCIDevice *dev)
 546 {
 547     int config_size = pci_config_size(dev);
 548
 549     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 550     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 551     pci_set_word(dev->wmask + PCI_COMMAND,
 552                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 553                  PCI_COMMAND_INTX_DISABLE);
 554
 555     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 556            config_size - PCI_CONFIG_HEADER_SIZE);
 557 }
 558
 559 static void pci_init_wmask_bridge(PCIDevice *d)
 560 {
 561     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 562        PCI_SEC_LETENCY_TIMER */
 563     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 564
 565     /* base and limit */
 566     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 567     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 568     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 569                  PCI_MEMORY_RANGE_MASK & 0xffff);
 570     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 571                  PCI_MEMORY_RANGE_MASK & 0xffff);
 572     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 573                  PCI_PREF_RANGE_MASK & 0xffff);
 574     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 575                  PCI_PREF_RANGE_MASK & 0xffff);
 576
 577     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 578     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 579
 580     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 581 }
 582
 583 static void pci_config_alloc(PCIDevice *pci_dev)
 584 {
 585     int config_size = pci_config_size(pci_dev);
 586
 587     pci_dev->config = qemu_mallocz(config_size);
 588     pci_dev->cmask = qemu_mallocz(config_size);
 589     pci_dev->wmask = qemu_mallocz(config_size);
 590     pci_dev->used = qemu_mallocz(config_size);
 591 }
 592
 593 static void pci_config_free(PCIDevice *pci_dev)
 594 {
 595     qemu_free(pci_dev->config);
 596     qemu_free(pci_dev->cmask);
 597     qemu_free(pci_dev->wmask);
 598     qemu_free(pci_dev->used);
 599 }
 600
 601 /* -1 for devfn means auto assign */
 602 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 603                                          const char *name, int devfn,
 604                                          PCIConfigReadFunc *config_read,
 605                                          PCIConfigWriteFunc *config_write,
 606                                          uint8_t header_type)
 607 {
 608     if (devfn < 0) {
 609         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 610             devfn += 8) {
 611             if (!bus->devices[devfn])
 612                 goto found;
 613         }
 614         error_report("PCI: no slot/function available for %s, all in use", name);
 615         return NULL;
 616     found: ;
 617     } else if (bus->devices[devfn]) {
 618         error_report("PCI: slot %d function %d not available for %s, in use by %s",
 619                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
 620         return NULL;
 621     }
 622     pci_dev->bus = bus;
 623     pci_dev->devfn = devfn;
 624     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 625     pci_dev->irq_state = 0;
 626     pci_config_alloc(pci_dev);
 627
 628     header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 629     if (header_type == PCI_HEADER_TYPE_NORMAL) {
 630         pci_set_default_subsystem_id(pci_dev);
 631     }
 632     pci_init_cmask(pci_dev);
 633     pci_init_wmask(pci_dev);
 634     if (header_type == PCI_HEADER_TYPE_BRIDGE) {
 635         pci_init_wmask_bridge(pci_dev);
 636     }
 637
 638     if (!config_read)
 639         config_read = pci_default_read_config;
 640     if (!config_write)
 641         config_write = pci_default_write_config;
 642     pci_dev->config_read = config_read;
 643     pci_dev->config_write = config_write;
 644     bus->devices[devfn] = pci_dev;
 645     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 646     pci_dev->version_id = 2; /* Current pci device vmstate version */
 647     return pci_dev;
 648 }
 649
 650 static void do_pci_unregister_device(PCIDevice *pci_dev)
 651 {
 652     qemu_free_irqs(pci_dev->irq);
 653     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 654     pci_config_free(pci_dev);
 655 }
 656
 657 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 658                                int instance_size, int devfn,
 659                                PCIConfigReadFunc *config_read,
 660                                PCIConfigWriteFunc *config_write)
 661 {
 662     PCIDevice *pci_dev;
 663
 664     pci_dev = qemu_mallocz(instance_size);
 665     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 666                                      config_read, config_write,
 667                                      PCI_HEADER_TYPE_NORMAL);
 668     if (pci_dev == NULL) {
 669         hw_error("PCI: can't register device\n");
 670     }
 671     return pci_dev;
 672 }
 673
 674 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
 675                                           target_phys_addr_t addr)
 676 {
 677     return addr + bus->mem_base;
 678 }
 679
 680 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 681 {
 682     PCIIORegion *r;
 683     int i;
 684
 685     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 686         r = &pci_dev->io_regions[i];
 687         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 688             continue;
 689         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 690             isa_unassign_ioport(r->addr, r->filtered_size);
 691         } else {
 692             cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
 693                                                          r->addr),
 694                                          r->filtered_size,
 695                                          IO_MEM_UNASSIGNED);
 696         }
 697     }
 698 }
 699
 700 static int pci_unregister_device(DeviceState *dev)
 701 {
 702     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 703     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 704     int ret = 0;
 705
 706     if (info->exit)
 707         ret = info->exit(pci_dev);
 708     if (ret)
 709         return ret;
 710
 711     pci_unregister_io_regions(pci_dev);
 712     do_pci_unregister_device(pci_dev);
 713     return 0;
 714 }
 715
 716 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 717                             pcibus_t size, int type,
 718                             PCIMapIORegionFunc *map_func)
 719 {
 720     PCIIORegion *r;
 721     uint32_t addr;
 722     pcibus_t wmask;
 723
 724     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 725         return;
 726
 727     if (size & (size-1)) {
 728         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 729                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 730         exit(1);
 731     }
 732
 733     r = &pci_dev->io_regions[region_num];
 734     r->addr = PCI_BAR_UNMAPPED;
 735     r->size = size;
 736     r->filtered_size = size;
 737     r->type = type;
 738     r->map_func = map_func;
 739
 740     wmask = ~(size - 1);
 741     addr = pci_bar(pci_dev, region_num);
 742     if (region_num == PCI_ROM_SLOT) {
 743         /* ROM enable bit is writeable */
 744         wmask |= PCI_ROM_ADDRESS_ENABLE;
 745     }
 746     pci_set_long(pci_dev->config + addr, type);
 747     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 748         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 749         pci_set_quad(pci_dev->wmask + addr, wmask);
 750         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 751     } else {
 752         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 753         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 754     }
 755 }
 756
 757 static uint32_t pci_config_get_io_base(PCIDevice *d,
 758                                        uint32_t base, uint32_t base_upper16)
 759 {
 760     uint32_t val;
 761
 762     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
 763     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
 764         val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
 765     }
 766     return val;
 767 }
 768
 769 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
 770 {
 771     return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
 772         << 16;
 773 }
 774
 775 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
 776                                          uint32_t base, uint32_t upper)
 777 {
 778     pcibus_t tmp;
 779     pcibus_t val;
 780
 781     tmp = (pcibus_t)pci_get_word(d->config + base);
 782     val = (tmp & PCI_PREF_RANGE_MASK) << 16;
 783     if (tmp & PCI_PREF_RANGE_TYPE_64) {
 784         val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
 785     }
 786     return val;
 787 }
 788
 789 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
 790 {
 791     pcibus_t base;
 792     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 793         base = pci_config_get_io_base(bridge,
 794                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 795     } else {
 796         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 797             base = pci_config_get_pref_base(
 798                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 799         } else {
 800             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 801         }
 802     }
 803
 804     return base;
 805 }
 806
 807 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
 808 {
 809     pcibus_t limit;
 810     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 811         limit = pci_config_get_io_base(bridge,
 812                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 813         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 814     } else {
 815         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 816             limit = pci_config_get_pref_base(
 817                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 818         } else {
 819             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 820         }
 821         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 822     }
 823     return limit;
 824 }
 825
 826 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 827                               uint8_t type)
 828 {
 829     pcibus_t base = *addr;
 830     pcibus_t limit = *addr + *size - 1;
 831     PCIDevice *br;
 832
 833     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 834         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 835
 836         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 837             if (!(cmd & PCI_COMMAND_IO)) {
 838                 goto no_map;
 839             }
 840         } else {
 841             if (!(cmd & PCI_COMMAND_MEMORY)) {
 842                 goto no_map;
 843             }
 844         }
 845
 846         base = MAX(base, pci_bridge_get_base(br, type));
 847         limit = MIN(limit, pci_bridge_get_limit(br, type));
 848     }
 849
 850     if (base > limit) {
 851         goto no_map;
 852     }
 853     *addr = base;
 854     *size = limit - base + 1;
 855     return;
 856 no_map:
 857     *addr = PCI_BAR_UNMAPPED;
 858     *size = 0;
 859 }
 860
 861 static pcibus_t pci_bar_address(PCIDevice *d,
 862                                 int reg, uint8_t type, pcibus_t size)
 863 {
 864     pcibus_t new_addr, last_addr;
 865     int bar = pci_bar(d, reg);
 866     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 867
 868     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 869         if (!(cmd & PCI_COMMAND_IO)) {
 870             return PCI_BAR_UNMAPPED;
 871         }
 872         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 873         last_addr = new_addr + size - 1;
 874         /* NOTE: we have only 64K ioports on PC */
 875         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 876             return PCI_BAR_UNMAPPED;
 877         }
 878         return new_addr;
 879     }
 880
 881     if (!(cmd & PCI_COMMAND_MEMORY)) {
 882         return PCI_BAR_UNMAPPED;
 883     }
 884     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 885         new_addr = pci_get_quad(d->config + bar);
 886     } else {
 887         new_addr = pci_get_long(d->config + bar);
 888     }
 889     /* the ROM slot has a specific enable bit */
 890     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 891         return PCI_BAR_UNMAPPED;
 892     }
 893     new_addr &= ~(size - 1);
 894     last_addr = new_addr + size - 1;
 895     /* NOTE: we do not support wrapping */
 896     /* XXX: as we cannot support really dynamic
 897        mappings, we handle specific values as invalid
 898        mappings. */
 899     if (last_addr <= new_addr || new_addr == 0 ||
 900         last_addr == PCI_BAR_UNMAPPED) {
 901         return PCI_BAR_UNMAPPED;
 902     }
 903
 904     /* Now pcibus_t is 64bit.
 905      * Check if 32 bit BAR wraps around explicitly.
 906      * Without this, PC ide doesn't work well.
 907      * TODO: remove this work around.
 908      */
 909     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 910         return PCI_BAR_UNMAPPED;
 911     }
 912
 913     /*
 914      * OS is allowed to set BAR beyond its addressable
 915      * bits. For example, 32 bit OS can set 64bit bar
 916      * to >4G. Check it. TODO: we might need to support
 917      * it in the future for e.g. PAE.
 918      */
 919     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 920         return PCI_BAR_UNMAPPED;
 921     }
 922
 923     return new_addr;
 924 }
 925
 926 static void pci_update_mappings(PCIDevice *d)
 927 {
 928     PCIIORegion *r;
 929     int i;
 930     pcibus_t new_addr, filtered_size;
 931
 932     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 933         r = &d->io_regions[i];
 934
 935         /* this region isn't registered */
 936         if (!r->size)
 937             continue;
 938
 939         new_addr = pci_bar_address(d, i, r->type, r->size);
 940
 941         /* bridge filtering */
 942         filtered_size = r->size;
 943         if (new_addr != PCI_BAR_UNMAPPED) {
 944             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 945         }
 946
 947         /* This bar isn't changed */
 948         if (new_addr == r->addr && filtered_size == r->filtered_size)
 949             continue;
 950
 951         /* now do the real mapping */
 952         if (r->addr != PCI_BAR_UNMAPPED) {
 953             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 954                 int class;
 955                 /* NOTE: specific hack for IDE in PC case:
 956                    only one byte must be mapped. */
 957                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 958                 if (class == 0x0101 && r->size == 4) {
 959                     isa_unassign_ioport(r->addr + 2, 1);
 960                 } else {
 961                     isa_unassign_ioport(r->addr, r->filtered_size);
 962                 }
 963             } else {
 964                 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
 965                                              r->filtered_size,
 966                                              IO_MEM_UNASSIGNED);
 967                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 968             }
 969         }
 970         r->addr = new_addr;
 971         r->filtered_size = filtered_size;
 972         if (r->addr != PCI_BAR_UNMAPPED) {
 973             /*
 974              * TODO: currently almost all the map funcions assumes
 975              * filtered_size == size and addr & ~(size - 1) == addr.
 976              * However with bridge filtering, they aren't always true.
 977              * Teach them such cases, such that filtered_size < size and
 978              * addr & (size - 1) != 0.
 979              */
 980             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 981                 r->map_func(d, i, r->addr, r->filtered_size, r->type);
 982             } else {
 983                 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
 984                             r->filtered_size, r->type);
 985             }
 986         }
 987     }
 988 }
 989
 990 static inline int pci_irq_disabled(PCIDevice *d)
 991 {
 992     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
 993 }
 994
 995 /* Called after interrupt disabled field update in config space,
 996  * assert/deassert interrupts if necessary.
 997  * Gets original interrupt disable bit value (before update). */
 998 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
 999 {
1000     int i, disabled = pci_irq_disabled(d);
1001     if (disabled == was_irq_disabled)
1002         return;
1003     for (i = 0; i < PCI_NUM_PINS; ++i) {
1004         int state = pci_irq_state(d, i);
1005         pci_change_irq_level(d, i, disabled ? -state : state);
1006     }
1007 }
1008
1009 uint32_t pci_default_read_config(PCIDevice *d,
1010                                  uint32_t address, int len)
1011 {
1012     uint32_t val = 0;
1013     assert(len == 1 || len == 2 || len == 4);
1014     len = MIN(len, pci_config_size(d) - address);
1015     memcpy(&val, d->config + address, len);
1016     return le32_to_cpu(val);
1017 }
1018
1019 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1020 {
1021     int i, was_irq_disabled = pci_irq_disabled(d);
1022     uint32_t config_size = pci_config_size(d);
1023
1024     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1025         uint8_t wmask = d->wmask[addr + i];
1026         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1027     }
1028     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1029         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1030         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1031         range_covers_byte(addr, l, PCI_COMMAND))
1032         pci_update_mappings(d);
1033
1034     if (range_covers_byte(addr, l, PCI_COMMAND))
1035         pci_update_irq_disabled(d, was_irq_disabled);
1036 }
1037
1038 /***********************************************************/
1039 /* generic PCI irq support */
1040
1041 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1042 static void pci_set_irq(void *opaque, int irq_num, int level)
1043 {
1044     PCIDevice *pci_dev = opaque;
1045     int change;
1046
1047     change = level - pci_irq_state(pci_dev, irq_num);
1048     if (!change)
1049         return;
1050
1051     pci_set_irq_state(pci_dev, irq_num, level);
1052     pci_update_irq_status(pci_dev);
1053     if (pci_irq_disabled(pci_dev))
1054         return;
1055     pci_change_irq_level(pci_dev, irq_num, change);
1056 }
1057
1058 /***********************************************************/
1059 /* monitor info on PCI */
1060
1061 typedef struct {
1062     uint16_t class;
1063     const char *desc;
1064 } pci_class_desc;
1065
1066 static const pci_class_desc pci_class_descriptions[] =
1067 {
1068     { 0x0100, "SCSI controller"},
1069     { 0x0101, "IDE controller"},
1070     { 0x0102, "Floppy controller"},
1071     { 0x0103, "IPI controller"},
1072     { 0x0104, "RAID controller"},
1073     { 0x0106, "SATA controller"},
1074     { 0x0107, "SAS controller"},
1075     { 0x0180, "Storage controller"},
1076     { 0x0200, "Ethernet controller"},
1077     { 0x0201, "Token Ring controller"},
1078     { 0x0202, "FDDI controller"},
1079     { 0x0203, "ATM controller"},
1080     { 0x0280, "Network controller"},
1081     { 0x0300, "VGA controller"},
1082     { 0x0301, "XGA controller"},
1083     { 0x0302, "3D controller"},
1084     { 0x0380, "Display controller"},
1085     { 0x0400, "Video controller"},
1086     { 0x0401, "Audio controller"},
1087     { 0x0402, "Phone"},
1088     { 0x0480, "Multimedia controller"},
1089     { 0x0500, "RAM controller"},
1090     { 0x0501, "Flash controller"},
1091     { 0x0580, "Memory controller"},
1092     { 0x0600, "Host bridge"},
1093     { 0x0601, "ISA bridge"},
1094     { 0x0602, "EISA bridge"},
1095     { 0x0603, "MC bridge"},
1096     { 0x0604, "PCI bridge"},
1097     { 0x0605, "PCMCIA bridge"},
1098     { 0x0606, "NUBUS bridge"},
1099     { 0x0607, "CARDBUS bridge"},
1100     { 0x0608, "RACEWAY bridge"},
1101     { 0x0680, "Bridge"},
1102     { 0x0c03, "USB controller"},
1103     { 0, NULL}
1104 };
1105
1106 static void pci_for_each_device_under_bus(PCIBus *bus,
1107                                           void (*fn)(PCIBus *b, PCIDevice *d))
1108 {
1109     PCIDevice *d;
1110     int devfn;
1111
1112     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1113         d = bus->devices[devfn];
1114         if (d) {
1115             fn(bus, d);
1116         }
1117     }
1118 }
1119
1120 void pci_for_each_device(PCIBus *bus, int bus_num,
1121                          void (*fn)(PCIBus *b, PCIDevice *d))
1122 {
1123     bus = pci_find_bus(bus, bus_num);
1124
1125     if (bus) {
1126         pci_for_each_device_under_bus(bus, fn);
1127     }
1128 }
1129
1130 static void pci_device_print(Monitor *mon, QDict *device)
1131 {
1132     QDict *qdict;
1133     QListEntry *entry;
1134     uint64_t addr, size;
1135
1136     monitor_printf(mon, "  Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1137     monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1138                         qdict_get_int(device, "slot"),
1139                         qdict_get_int(device, "function"));
1140     monitor_printf(mon, "    ");
1141
1142     qdict = qdict_get_qdict(device, "class_info");
1143     if (qdict_haskey(qdict, "desc")) {
1144         monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1145     } else {
1146         monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1147     }
1148
1149     qdict = qdict_get_qdict(device, "id");
1150     monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1151                         qdict_get_int(qdict, "device"),
1152                         qdict_get_int(qdict, "vendor"));
1153
1154     if (qdict_haskey(device, "irq")) {
1155         monitor_printf(mon, "      IRQ %" PRId64 ".\n",
1156                             qdict_get_int(device, "irq"));
1157     }
1158
1159     if (qdict_haskey(device, "pci_bridge")) {
1160         QDict *info;
1161
1162         qdict = qdict_get_qdict(device, "pci_bridge");
1163
1164         info = qdict_get_qdict(qdict, "bus");
1165         monitor_printf(mon, "      BUS %" PRId64 ".\n",
1166                             qdict_get_int(info, "number"));
1167         monitor_printf(mon, "      secondary bus %" PRId64 ".\n",
1168                             qdict_get_int(info, "secondary"));
1169         monitor_printf(mon, "      subordinate bus %" PRId64 ".\n",
1170                             qdict_get_int(info, "subordinate"));
1171
1172         info = qdict_get_qdict(qdict, "io_range");
1173         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1174                        qdict_get_int(info, "base"),
1175                        qdict_get_int(info, "limit"));
1176
1177         info = qdict_get_qdict(qdict, "memory_range");
1178         monitor_printf(mon,
1179                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1180                        qdict_get_int(info, "base"),
1181                        qdict_get_int(info, "limit"));
1182
1183         info = qdict_get_qdict(qdict, "prefetchable_range");
1184         monitor_printf(mon, "      prefetchable memory range "
1185                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1186                        qdict_get_int(info, "base"),
1187         qdict_get_int(info, "limit"));
1188     }
1189
1190     QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1191         qdict = qobject_to_qdict(qlist_entry_obj(entry));
1192         monitor_printf(mon, "      BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1193
1194         addr = qdict_get_int(qdict, "address");
1195         size = qdict_get_int(qdict, "size");
1196
1197         if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1198             monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1199                                 " [0x%04"FMT_PCIBUS"].\n",
1200                                 addr, addr + size - 1);
1201         } else {
1202             monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1203                                " [0x%08"FMT_PCIBUS"].\n",
1204                                 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1205                                 qdict_get_bool(qdict, "prefetch") ?
1206                                 " prefetchable" : "", addr, addr + size - 1);
1207         }
1208     }
1209
1210     monitor_printf(mon, "      id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1211
1212     if (qdict_haskey(device, "pci_bridge")) {
1213         qdict = qdict_get_qdict(device, "pci_bridge");
1214         if (qdict_haskey(qdict, "devices")) {
1215             QListEntry *dev;
1216             QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1217                 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1218             }
1219         }
1220     }
1221 }
1222
1223 void do_pci_info_print(Monitor *mon, const QObject *data)
1224 {
1225     QListEntry *bus, *dev;
1226
1227     QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1228         QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1229         QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1230             pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1231         }
1232     }
1233 }
1234
1235 static QObject *pci_get_dev_class(const PCIDevice *dev)
1236 {
1237     int class;
1238     const pci_class_desc *desc;
1239
1240     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1241     desc = pci_class_descriptions;
1242     while (desc->desc && class != desc->class)
1243         desc++;
1244
1245     if (desc->desc) {
1246         return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1247                                   desc->desc, class);
1248     } else {
1249         return qobject_from_jsonf("{ 'class': %d }", class);
1250     }
1251 }
1252
1253 static QObject *pci_get_dev_id(const PCIDevice *dev)
1254 {
1255     return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1256                               pci_get_word(dev->config + PCI_VENDOR_ID),
1257                               pci_get_word(dev->config + PCI_DEVICE_ID));
1258 }
1259
1260 static QObject *pci_get_regions_list(const PCIDevice *dev)
1261 {
1262     int i;
1263     QList *regions_list;
1264
1265     regions_list = qlist_new();
1266
1267     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1268         QObject *obj;
1269         const PCIIORegion *r = &dev->io_regions[i];
1270
1271         if (!r->size) {
1272             continue;
1273         }
1274
1275         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1276             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1277                                      "'address': %" PRId64 ", "
1278                                      "'size': %" PRId64 " }",
1279                                      i, r->addr, r->size);
1280         } else {
1281             int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1282
1283             obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1284                                      "'mem_type_64': %i, 'prefetch': %i, "
1285                                      "'address': %" PRId64 ", "
1286                                      "'size': %" PRId64 " }",
1287                                      i, mem_type_64,
1288                                      r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1289                                      r->addr, r->size);
1290         }
1291
1292         qlist_append_obj(regions_list, obj);
1293     }
1294
1295     return QOBJECT(regions_list);
1296 }
1297
1298 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1299
1300 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1301 {
1302     uint8_t type;
1303     QObject *obj;
1304
1305     obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d,"                                       "'class_info': %p, 'id': %p, 'regions': %p,"
1306                               " 'qdev_id': %s }",
1307                               bus_num,
1308                               PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1309                               pci_get_dev_class(dev), pci_get_dev_id(dev),
1310                               pci_get_regions_list(dev),
1311                               dev->qdev.id ? dev->qdev.id : "");
1312
1313     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1314         QDict *qdict = qobject_to_qdict(obj);
1315         qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1316     }
1317
1318     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1319     if (type == PCI_HEADER_TYPE_BRIDGE) {
1320         QDict *qdict;
1321         QObject *pci_bridge;
1322
1323         pci_bridge = qobject_from_jsonf("{ 'bus': "
1324         "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1325         "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1326         "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1327         "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1328         dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1329         dev->config[PCI_SUBORDINATE_BUS],
1330         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1331         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1332         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1333         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1334         pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1335                                PCI_BASE_ADDRESS_MEM_PREFETCH),
1336         pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1337                                 PCI_BASE_ADDRESS_MEM_PREFETCH));
1338
1339         if (dev->config[PCI_SECONDARY_BUS] != 0) {
1340             PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1341
1342             if (child_bus) {
1343                 qdict = qobject_to_qdict(pci_bridge);
1344                 qdict_put_obj(qdict, "devices",
1345                               pci_get_devices_list(child_bus,
1346                                                    dev->config[PCI_SECONDARY_BUS]));
1347             }
1348         }
1349         qdict = qobject_to_qdict(obj);
1350         qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1351     }
1352
1353     return obj;
1354 }
1355
1356 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1357 {
1358     int devfn;
1359     PCIDevice *dev;
1360     QList *dev_list;
1361
1362     dev_list = qlist_new();
1363
1364     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1365         dev = bus->devices[devfn];
1366         if (dev) {
1367             qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1368         }
1369     }
1370
1371     return QOBJECT(dev_list);
1372 }
1373
1374 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1375 {
1376     bus = pci_find_bus(bus, bus_num);
1377     if (bus) {
1378         return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1379                                   bus_num, pci_get_devices_list(bus, bus_num));
1380     }
1381
1382     return NULL;
1383 }
1384
1385 void do_pci_info(Monitor *mon, QObject **ret_data)
1386 {
1387     QList *bus_list;
1388     struct PCIHostBus *host;
1389
1390     bus_list = qlist_new();
1391
1392     QLIST_FOREACH(host, &host_buses, next) {
1393         QObject *obj = pci_get_bus_dict(host->bus, 0);
1394         if (obj) {
1395             qlist_append_obj(bus_list, obj);
1396         }
1397     }
1398
1399     *ret_data = QOBJECT(bus_list);
1400 }
1401
1402 static const char * const pci_nic_models[] = {
1403     "ne2k_pci",
1404     "i82551",
1405     "i82557b",
1406     "i82559er",
1407     "rtl8139",
1408     "e1000",
1409     "pcnet",
1410     "virtio",
1411     NULL
1412 };
1413
1414 static const char * const pci_nic_names[] = {
1415     "ne2k_pci",
1416     "i82551",
1417     "i82557b",
1418     "i82559er",
1419     "rtl8139",
1420     "e1000",
1421     "pcnet",
1422     "virtio-net-pci",
1423     NULL
1424 };
1425
1426 /* Initialize a PCI NIC.  */
1427 /* FIXME callers should check for failure, but don't */
1428 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1429                         const char *default_devaddr)
1430 {
1431     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1432     PCIBus *bus;
1433     int devfn;
1434     PCIDevice *pci_dev;
1435     DeviceState *dev;
1436     int i;
1437
1438     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1439     if (i < 0)
1440         return NULL;
1441
1442     bus = pci_get_bus_devfn(&devfn, devaddr);
1443     if (!bus) {
1444         error_report("Invalid PCI device address %s for device %s",
1445                      devaddr, pci_nic_names[i]);
1446         return NULL;
1447     }
1448
1449     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1450     dev = &pci_dev->qdev;
1451     qdev_set_nic_properties(dev, nd);
1452     if (qdev_init(dev) < 0)
1453         return NULL;
1454     return pci_dev;
1455 }
1456
1457 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1458                                const char *default_devaddr)
1459 {
1460     PCIDevice *res;
1461
1462     if (qemu_show_nic_models(nd->model, pci_nic_models))
1463         exit(0);
1464
1465     res = pci_nic_init(nd, default_model, default_devaddr);
1466     if (!res)
1467         exit(1);
1468     return res;
1469 }
1470
1471 typedef struct {
1472     PCIDevice dev;
1473     PCIBus bus;
1474     uint32_t vid;
1475     uint32_t did;
1476 } PCIBridge;
1477
1478
1479 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1480 {
1481     pci_update_mappings(d);
1482 }
1483
1484 static void pci_bridge_update_mappings(PCIBus *b)
1485 {
1486     PCIBus *child;
1487
1488     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1489
1490     QLIST_FOREACH(child, &b->child, sibling) {
1491         pci_bridge_update_mappings(child);
1492     }
1493 }
1494
1495 static void pci_bridge_write_config(PCIDevice *d,
1496                              uint32_t address, uint32_t val, int len)
1497 {
1498     pci_default_write_config(d, address, val, len);
1499
1500     if (/* io base/limit */
1501         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1502
1503         /* memory base/limit, prefetchable base/limit and
1504            io base/limit upper 16 */
1505         ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1506         pci_bridge_update_mappings(d->bus);
1507     }
1508 }
1509
1510 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1511 {
1512     PCIBus *sec;
1513
1514     if (!bus) {
1515         return NULL;
1516     }
1517
1518     if (pci_bus_num(bus) == bus_num) {
1519         return bus;
1520     }
1521
1522     /* try child bus */
1523     if (!bus->parent_dev /* host pci bridge */ ||
1524         (bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1525          bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1526         for (; bus; bus = sec) {
1527             QLIST_FOREACH(sec, &bus->child, sibling) {
1528                 assert(sec->parent_dev);
1529                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1530                     return sec;
1531                 }
1532                 if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
1533                     bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
1534                     break;
1535                 }
1536             }
1537         }
1538     }
1539
1540     return NULL;
1541 }
1542
1543 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1544 {
1545     bus = pci_find_bus(bus, bus_num);
1546
1547     if (!bus)
1548         return NULL;
1549
1550     return bus->devices[PCI_DEVFN(slot, function)];
1551 }
1552
1553 static int pci_bridge_initfn(PCIDevice *dev)
1554 {
1555     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1556
1557     pci_config_set_vendor_id(s->dev.config, s->vid);
1558     pci_config_set_device_id(s->dev.config, s->did);
1559
1560     pci_set_word(dev->config + PCI_STATUS,
1561                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1562     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1563     dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1564     pci_set_word(dev->config + PCI_SEC_STATUS,
1565                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1566     return 0;
1567 }
1568
1569 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1570 {
1571     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1572     PCIBus *bus = &s->bus;
1573     pci_unregister_secondary_bus(bus);
1574     return 0;
1575 }
1576
1577 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1578                         pci_map_irq_fn map_irq, const char *name)
1579 {
1580     PCIDevice *dev;
1581     PCIBridge *s;
1582
1583     dev = pci_create(bus, devfn, "pci-bridge");
1584     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1585     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1586     qdev_init_nofail(&dev->qdev);
1587
1588     s = DO_UPCAST(PCIBridge, dev, dev);
1589     pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1590     return &s->bus;
1591 }
1592
1593 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1594 {
1595     return bus->parent_dev;
1596 }
1597
1598 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1599 {
1600     PCIDevice *pci_dev = (PCIDevice *)qdev;
1601     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1602     PCIBus *bus;
1603     int devfn, rc;
1604
1605     /* initialize cap_present for pci_is_express() and pci_config_size() */
1606     if (info->is_express) {
1607         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1608     }
1609
1610     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1611     devfn = pci_dev->devfn;
1612     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1613                                      info->config_read, info->config_write,
1614                                      info->header_type);
1615     if (pci_dev == NULL)
1616         return -1;
1617     rc = info->init(pci_dev);
1618     if (rc != 0) {
1619         do_pci_unregister_device(pci_dev);
1620         return rc;
1621     }
1622
1623     /* rom loading */
1624     if (pci_dev->romfile == NULL && info->romfile != NULL)
1625         pci_dev->romfile = qemu_strdup(info->romfile);
1626     pci_add_option_rom(pci_dev);
1627
1628     if (qdev->hotplugged)
1629         bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
1630     return 0;
1631 }
1632
1633 static int pci_unplug_device(DeviceState *qdev)
1634 {
1635     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1636
1637     dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
1638     return 0;
1639 }
1640
1641 void pci_qdev_register(PCIDeviceInfo *info)
1642 {
1643     info->qdev.init = pci_qdev_init;
1644     info->qdev.unplug = pci_unplug_device;
1645     info->qdev.exit = pci_unregister_device;
1646     info->qdev.bus_info = &pci_bus_info;
1647     qdev_register(&info->qdev);
1648 }
1649
1650 void pci_qdev_register_many(PCIDeviceInfo *info)
1651 {
1652     while (info->qdev.name) {
1653         pci_qdev_register(info);
1654         info++;
1655     }
1656 }
1657
1658 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1659 {
1660     DeviceState *dev;
1661
1662     dev = qdev_create(&bus->qbus, name);
1663     qdev_prop_set_uint32(dev, "addr", devfn);
1664     return DO_UPCAST(PCIDevice, qdev, dev);
1665 }
1666
1667 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1668 {
1669     PCIDevice *dev = pci_create(bus, devfn, name);
1670     qdev_init_nofail(&dev->qdev);
1671     return dev;
1672 }
1673
1674 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1675 {
1676     int config_size = pci_config_size(pdev);
1677     int offset = PCI_CONFIG_HEADER_SIZE;
1678     int i;
1679     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1680         if (pdev->used[i])
1681             offset = i + 1;
1682         else if (i - offset + 1 == size)
1683             return offset;
1684     return 0;
1685 }
1686
1687 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1688                                         uint8_t *prev_p)
1689 {
1690     uint8_t next, prev;
1691
1692     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1693         return 0;
1694
1695     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1696          prev = next + PCI_CAP_LIST_NEXT)
1697         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1698             break;
1699
1700     if (prev_p)
1701         *prev_p = prev;
1702     return next;
1703 }
1704
1705 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1706 {
1707     cpu_register_physical_memory(addr, size, pdev->rom_offset);
1708 }
1709
1710 /* Add an option rom for the device */
1711 static int pci_add_option_rom(PCIDevice *pdev)
1712 {
1713     int size;
1714     char *path;
1715     void *ptr;
1716     char name[32];
1717
1718     if (!pdev->romfile)
1719         return 0;
1720     if (strlen(pdev->romfile) == 0)
1721         return 0;
1722
1723     if (!pdev->rom_bar) {
1724         /*
1725          * Load rom via fw_cfg instead of creating a rom bar,
1726          * for 0.11 compatibility.
1727          */
1728         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1729         if (class == 0x0300) {
1730             rom_add_vga(pdev->romfile);
1731         } else {
1732             rom_add_option(pdev->romfile);
1733         }
1734         return 0;
1735     }
1736
1737     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1738     if (path == NULL) {
1739         path = qemu_strdup(pdev->romfile);
1740     }
1741
1742     size = get_image_size(path);
1743     if (size < 0) {
1744         error_report("%s: failed to find romfile \"%s\"",
1745                      __FUNCTION__, pdev->romfile);
1746         return -1;
1747     }
1748     if (size & (size - 1)) {
1749         size = 1 << qemu_fls(size);
1750     }
1751
1752     if (pdev->qdev.info->vmsd)
1753         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1754     else
1755         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1756     pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1757
1758     ptr = qemu_get_ram_ptr(pdev->rom_offset);
1759     load_image(path, ptr);
1760     qemu_free(path);
1761
1762     pci_register_bar(pdev, PCI_ROM_SLOT, size,
1763                      0, pci_map_option_rom);
1764
1765     return 0;
1766 }
1767
1768 /* Reserve space and add capability to the linked list in pci config space */
1769 int pci_add_capability_at_offset(PCIDevice *pdev, uint8_t cap_id,
1770                                  uint8_t offset, uint8_t size)
1771 {
1772     uint8_t *config = pdev->config + offset;
1773     config[PCI_CAP_LIST_ID] = cap_id;
1774     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1775     pdev->config[PCI_CAPABILITY_LIST] = offset;
1776     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1777     memset(pdev->used + offset, 0xFF, size);
1778     /* Make capability read-only by default */
1779     memset(pdev->wmask + offset, 0, size);
1780     /* Check capability by default */
1781     memset(pdev->cmask + offset, 0xFF, size);
1782     return offset;
1783 }
1784
1785 /* Find and reserve space and add capability to the linked list
1786  * in pci config space */
1787 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1788 {
1789     uint8_t offset = pci_find_space(pdev, size);
1790     if (!offset) {
1791         return -ENOSPC;
1792     }
1793     return pci_add_capability_at_offset(pdev, cap_id, offset, size);
1794 }
1795
1796 /* Unlink capability from the pci config space. */
1797 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1798 {
1799     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1800     if (!offset)
1801         return;
1802     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1803     /* Make capability writeable again */
1804     memset(pdev->wmask + offset, 0xff, size);
1805     /* Clear cmask as device-specific registers can't be checked */
1806     memset(pdev->cmask + offset, 0, size);
1807     memset(pdev->used + offset, 0, size);
1808
1809     if (!pdev->config[PCI_CAPABILITY_LIST])
1810         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1811 }
1812
1813 /* Reserve space for capability at a known offset (to call after load). */
1814 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1815 {
1816     memset(pdev->used + offset, 0xff, size);
1817 }
1818
1819 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1820 {
1821     return pci_find_capability_list(pdev, cap_id, NULL);
1822 }
1823
1824 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1825 {
1826     PCIDevice *d = (PCIDevice *)dev;
1827     const pci_class_desc *desc;
1828     char ctxt[64];
1829     PCIIORegion *r;
1830     int i, class;
1831
1832     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1833     desc = pci_class_descriptions;
1834     while (desc->desc && class != desc->class)
1835         desc++;
1836     if (desc->desc) {
1837         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1838     } else {
1839         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1840     }
1841
1842     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1843                    "pci id %04x:%04x (sub %04x:%04x)\n",
1844                    indent, "", ctxt,
1845                    d->config[PCI_SECONDARY_BUS],
1846                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1847                    pci_get_word(d->config + PCI_VENDOR_ID),
1848                    pci_get_word(d->config + PCI_DEVICE_ID),
1849                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1850                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1851     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1852         r = &d->io_regions[i];
1853         if (!r->size)
1854             continue;
1855         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1856                        " [0x%"FMT_PCIBUS"]\n",
1857                        indent, "",
1858                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1859                        r->addr, r->addr + r->size - 1);
1860     }
1861 }
1862
1863 static char *pcibus_get_dev_path(DeviceState *dev)
1864 {
1865     PCIDevice *d = (PCIDevice *)dev;
1866     char path[16];
1867
1868     snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1869              pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1870              PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1871
1872     return strdup(path);
1873 }
1874
1875 static PCIDeviceInfo bridge_info = {
1876     .qdev.name    = "pci-bridge",
1877     .qdev.size    = sizeof(PCIBridge),
1878     .init         = pci_bridge_initfn,
1879     .exit         = pci_bridge_exitfn,
1880     .config_write = pci_bridge_write_config,
1881     .header_type  = PCI_HEADER_TYPE_BRIDGE,
1882     .qdev.props   = (Property[]) {
1883         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1884         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1885         DEFINE_PROP_END_OF_LIST(),
1886     }
1887 };
1888
1889 static void pci_register_devices(void)
1890 {
1891     pci_qdev_register(&bridge_info);
1892 }
1893
1894 device_init(pci_register_devices)