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pci: fold BAR mapping function into its caller
[qemu.git] / hw / pci.c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = qemu_mallocz(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name,
267 MemoryRegion *address_space_mem,
268 MemoryRegion *address_space_io,
269 uint8_t devfn_min)
270 {
271 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
272 assert(PCI_FUNC(devfn_min) == 0);
273 bus->devfn_min = devfn_min;
274 bus->address_space_mem = address_space_mem;
275 bus->address_space_io = address_space_io;
276
277 /* host bridge */
278 QLIST_INIT(&bus->child);
279 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
280
281 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
282 }
283
284 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
285 MemoryRegion *address_space_mem,
286 MemoryRegion *address_space_io,
287 uint8_t devfn_min)
288 {
289 PCIBus *bus;
290
291 bus = qemu_mallocz(sizeof(*bus));
292 bus->qbus.qdev_allocated = 1;
293 pci_bus_new_inplace(bus, parent, name, address_space_mem,
294 address_space_io, devfn_min);
295 return bus;
296 }
297
298 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
299 void *irq_opaque, int nirq)
300 {
301 bus->set_irq = set_irq;
302 bus->map_irq = map_irq;
303 bus->irq_opaque = irq_opaque;
304 bus->nirq = nirq;
305 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
306 }
307
308 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
309 {
310 bus->qbus.allow_hotplug = 1;
311 bus->hotplug = hotplug;
312 bus->hotplug_qdev = qdev;
313 }
314
315 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
316 {
317 bus->mem_base = base;
318 }
319
320 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
321 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
322 void *irq_opaque,
323 MemoryRegion *address_space_mem,
324 MemoryRegion *address_space_io,
325 uint8_t devfn_min, int nirq)
326 {
327 PCIBus *bus;
328
329 bus = pci_bus_new(parent, name, address_space_mem,
330 address_space_io, devfn_min);
331 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
332 return bus;
333 }
334
335 int pci_bus_num(PCIBus *s)
336 {
337 if (!s->parent_dev)
338 return 0; /* pci host bridge */
339 return s->parent_dev->config[PCI_SECONDARY_BUS];
340 }
341
342 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
343 {
344 PCIDevice *s = container_of(pv, PCIDevice, config);
345 uint8_t *config;
346 int i;
347
348 assert(size == pci_config_size(s));
349 config = qemu_malloc(size);
350
351 qemu_get_buffer(f, config, size);
352 for (i = 0; i < size; ++i) {
353 if ((config[i] ^ s->config[i]) &
354 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
355 qemu_free(config);
356 return -EINVAL;
357 }
358 }
359 memcpy(s->config, config, size);
360
361 pci_update_mappings(s);
362
363 qemu_free(config);
364 return 0;
365 }
366
367 /* just put buffer */
368 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
369 {
370 const uint8_t **v = pv;
371 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
372 qemu_put_buffer(f, *v, size);
373 }
374
375 static VMStateInfo vmstate_info_pci_config = {
376 .name = "pci config",
377 .get = get_pci_config_device,
378 .put = put_pci_config_device,
379 };
380
381 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
382 {
383 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
384 uint32_t irq_state[PCI_NUM_PINS];
385 int i;
386 for (i = 0; i < PCI_NUM_PINS; ++i) {
387 irq_state[i] = qemu_get_be32(f);
388 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
389 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
390 irq_state[i]);
391 return -EINVAL;
392 }
393 }
394
395 for (i = 0; i < PCI_NUM_PINS; ++i) {
396 pci_set_irq_state(s, i, irq_state[i]);
397 }
398
399 return 0;
400 }
401
402 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
403 {
404 int i;
405 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
406
407 for (i = 0; i < PCI_NUM_PINS; ++i) {
408 qemu_put_be32(f, pci_irq_state(s, i));
409 }
410 }
411
412 static VMStateInfo vmstate_info_pci_irq_state = {
413 .name = "pci irq state",
414 .get = get_pci_irq_state,
415 .put = put_pci_irq_state,
416 };
417
418 const VMStateDescription vmstate_pci_device = {
419 .name = "PCIDevice",
420 .version_id = 2,
421 .minimum_version_id = 1,
422 .minimum_version_id_old = 1,
423 .fields = (VMStateField []) {
424 VMSTATE_INT32_LE(version_id, PCIDevice),
425 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
426 vmstate_info_pci_config,
427 PCI_CONFIG_SPACE_SIZE),
428 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
429 vmstate_info_pci_irq_state,
430 PCI_NUM_PINS * sizeof(int32_t)),
431 VMSTATE_END_OF_LIST()
432 }
433 };
434
435 const VMStateDescription vmstate_pcie_device = {
436 .name = "PCIDevice",
437 .version_id = 2,
438 .minimum_version_id = 1,
439 .minimum_version_id_old = 1,
440 .fields = (VMStateField []) {
441 VMSTATE_INT32_LE(version_id, PCIDevice),
442 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
443 vmstate_info_pci_config,
444 PCIE_CONFIG_SPACE_SIZE),
445 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
446 vmstate_info_pci_irq_state,
447 PCI_NUM_PINS * sizeof(int32_t)),
448 VMSTATE_END_OF_LIST()
449 }
450 };
451
452 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
453 {
454 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
455 }
456
457 void pci_device_save(PCIDevice *s, QEMUFile *f)
458 {
459 /* Clear interrupt status bit: it is implicit
460 * in irq_state which we are saving.
461 * This makes us compatible with old devices
462 * which never set or clear this bit. */
463 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
464 vmstate_save_state(f, pci_get_vmstate(s), s);
465 /* Restore the interrupt status bit. */
466 pci_update_irq_status(s);
467 }
468
469 int pci_device_load(PCIDevice *s, QEMUFile *f)
470 {
471 int ret;
472 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
473 /* Restore the interrupt status bit. */
474 pci_update_irq_status(s);
475 return ret;
476 }
477
478 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
479 {
480 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
481 pci_default_sub_vendor_id);
482 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
483 pci_default_sub_device_id);
484 }
485
486 /*
487 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
488 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
489 */
490 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
491 unsigned int *slotp, unsigned int *funcp)
492 {
493 const char *p;
494 char *e;
495 unsigned long val;
496 unsigned long dom = 0, bus = 0;
497 unsigned int slot = 0;
498 unsigned int func = 0;
499
500 p = addr;
501 val = strtoul(p, &e, 16);
502 if (e == p)
503 return -1;
504 if (*e == ':') {
505 bus = val;
506 p = e + 1;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510 if (*e == ':') {
511 dom = bus;
512 bus = val;
513 p = e + 1;
514 val = strtoul(p, &e, 16);
515 if (e == p)
516 return -1;
517 }
518 }
519
520 slot = val;
521
522 if (funcp != NULL) {
523 if (*e != '.')
524 return -1;
525
526 p = e + 1;
527 val = strtoul(p, &e, 16);
528 if (e == p)
529 return -1;
530
531 func = val;
532 }
533
534 /* if funcp == NULL func is 0 */
535 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
536 return -1;
537
538 if (*e)
539 return -1;
540
541 /* Note: QEMU doesn't implement domains other than 0 */
542 if (!pci_find_bus(pci_find_root_bus(dom), bus))
543 return -1;
544
545 *domp = dom;
546 *busp = bus;
547 *slotp = slot;
548 if (funcp != NULL)
549 *funcp = func;
550 return 0;
551 }
552
553 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
554 unsigned *slotp)
555 {
556 /* strip legacy tag */
557 if (!strncmp(addr, "pci_addr=", 9)) {
558 addr += 9;
559 }
560 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
561 monitor_printf(mon, "Invalid pci address\n");
562 return -1;
563 }
564 return 0;
565 }
566
567 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
568 {
569 int dom, bus;
570 unsigned slot;
571
572 if (!devaddr) {
573 *devfnp = -1;
574 return pci_find_bus(pci_find_root_bus(0), 0);
575 }
576
577 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
578 return NULL;
579 }
580
581 *devfnp = PCI_DEVFN(slot, 0);
582 return pci_find_bus(pci_find_root_bus(dom), bus);
583 }
584
585 static void pci_init_cmask(PCIDevice *dev)
586 {
587 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
588 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
589 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
590 dev->cmask[PCI_REVISION_ID] = 0xff;
591 dev->cmask[PCI_CLASS_PROG] = 0xff;
592 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
593 dev->cmask[PCI_HEADER_TYPE] = 0xff;
594 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
595 }
596
597 static void pci_init_wmask(PCIDevice *dev)
598 {
599 int config_size = pci_config_size(dev);
600
601 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
602 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
603 pci_set_word(dev->wmask + PCI_COMMAND,
604 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
605 PCI_COMMAND_INTX_DISABLE);
606 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
607 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
608 }
609
610 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
611 config_size - PCI_CONFIG_HEADER_SIZE);
612 }
613
614 static void pci_init_w1cmask(PCIDevice *dev)
615 {
616 /*
617 * Note: It's okay to set w1cmask even for readonly bits as
618 * long as their value is hardwired to 0.
619 */
620 pci_set_word(dev->w1cmask + PCI_STATUS,
621 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
622 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
623 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
624 }
625
626 static void pci_init_wmask_bridge(PCIDevice *d)
627 {
628 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
629 PCI_SEC_LETENCY_TIMER */
630 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
631
632 /* base and limit */
633 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
634 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
635 pci_set_word(d->wmask + PCI_MEMORY_BASE,
636 PCI_MEMORY_RANGE_MASK & 0xffff);
637 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
638 PCI_MEMORY_RANGE_MASK & 0xffff);
639 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
640 PCI_PREF_RANGE_MASK & 0xffff);
641 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
642 PCI_PREF_RANGE_MASK & 0xffff);
643
644 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
645 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
646
647 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
648 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
649 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
650 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
651 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
652 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
653 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
654 PCI_BRIDGE_CTL_PARITY |
655 PCI_BRIDGE_CTL_SERR |
656 PCI_BRIDGE_CTL_ISA |
657 PCI_BRIDGE_CTL_VGA |
658 PCI_BRIDGE_CTL_VGA_16BIT |
659 PCI_BRIDGE_CTL_MASTER_ABORT |
660 PCI_BRIDGE_CTL_BUS_RESET |
661 PCI_BRIDGE_CTL_FAST_BACK |
662 PCI_BRIDGE_CTL_DISCARD |
663 PCI_BRIDGE_CTL_SEC_DISCARD |
664 PCI_BRIDGE_CTL_DISCARD_SERR);
665 /* Below does not do anything as we never set this bit, put here for
666 * completeness. */
667 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
668 PCI_BRIDGE_CTL_DISCARD_STATUS);
669 }
670
671 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
672 {
673 uint8_t slot = PCI_SLOT(dev->devfn);
674 uint8_t func;
675
676 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
677 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
678 }
679
680 /*
681 * multifunction bit is interpreted in two ways as follows.
682 * - all functions must set the bit to 1.
683 * Example: Intel X53
684 * - function 0 must set the bit, but the rest function (> 0)
685 * is allowed to leave the bit to 0.
686 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
687 *
688 * So OS (at least Linux) checks the bit of only function 0,
689 * and doesn't see the bit of function > 0.
690 *
691 * The below check allows both interpretation.
692 */
693 if (PCI_FUNC(dev->devfn)) {
694 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
695 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
696 /* function 0 should set multifunction bit */
697 error_report("PCI: single function device can't be populated "
698 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
699 return -1;
700 }
701 return 0;
702 }
703
704 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
705 return 0;
706 }
707 /* function 0 indicates single function, so function > 0 must be NULL */
708 for (func = 1; func < PCI_FUNC_MAX; ++func) {
709 if (bus->devices[PCI_DEVFN(slot, func)]) {
710 error_report("PCI: %x.0 indicates single function, "
711 "but %x.%x is already populated.",
712 slot, slot, func);
713 return -1;
714 }
715 }
716 return 0;
717 }
718
719 static void pci_config_alloc(PCIDevice *pci_dev)
720 {
721 int config_size = pci_config_size(pci_dev);
722
723 pci_dev->config = qemu_mallocz(config_size);
724 pci_dev->cmask = qemu_mallocz(config_size);
725 pci_dev->wmask = qemu_mallocz(config_size);
726 pci_dev->w1cmask = qemu_mallocz(config_size);
727 pci_dev->used = qemu_mallocz(config_size);
728 }
729
730 static void pci_config_free(PCIDevice *pci_dev)
731 {
732 qemu_free(pci_dev->config);
733 qemu_free(pci_dev->cmask);
734 qemu_free(pci_dev->wmask);
735 qemu_free(pci_dev->w1cmask);
736 qemu_free(pci_dev->used);
737 }
738
739 /* -1 for devfn means auto assign */
740 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
741 const char *name, int devfn,
742 const PCIDeviceInfo *info)
743 {
744 PCIConfigReadFunc *config_read = info->config_read;
745 PCIConfigWriteFunc *config_write = info->config_write;
746
747 if (devfn < 0) {
748 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
749 devfn += PCI_FUNC_MAX) {
750 if (!bus->devices[devfn])
751 goto found;
752 }
753 error_report("PCI: no slot/function available for %s, all in use", name);
754 return NULL;
755 found: ;
756 } else if (bus->devices[devfn]) {
757 error_report("PCI: slot %d function %d not available for %s, in use by %s",
758 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
759 return NULL;
760 }
761 pci_dev->bus = bus;
762 pci_dev->devfn = devfn;
763 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
764 pci_dev->irq_state = 0;
765 pci_config_alloc(pci_dev);
766
767 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
768 pci_config_set_device_id(pci_dev->config, info->device_id);
769 pci_config_set_revision(pci_dev->config, info->revision);
770 pci_config_set_class(pci_dev->config, info->class_id);
771
772 if (!info->is_bridge) {
773 if (info->subsystem_vendor_id || info->subsystem_id) {
774 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
775 info->subsystem_vendor_id);
776 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
777 info->subsystem_id);
778 } else {
779 pci_set_default_subsystem_id(pci_dev);
780 }
781 } else {
782 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
783 assert(!info->subsystem_vendor_id);
784 assert(!info->subsystem_id);
785 }
786 pci_init_cmask(pci_dev);
787 pci_init_wmask(pci_dev);
788 pci_init_w1cmask(pci_dev);
789 if (info->is_bridge) {
790 pci_init_wmask_bridge(pci_dev);
791 }
792 if (pci_init_multifunction(bus, pci_dev)) {
793 pci_config_free(pci_dev);
794 return NULL;
795 }
796
797 if (!config_read)
798 config_read = pci_default_read_config;
799 if (!config_write)
800 config_write = pci_default_write_config;
801 pci_dev->config_read = config_read;
802 pci_dev->config_write = config_write;
803 bus->devices[devfn] = pci_dev;
804 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
805 pci_dev->version_id = 2; /* Current pci device vmstate version */
806 return pci_dev;
807 }
808
809 static void do_pci_unregister_device(PCIDevice *pci_dev)
810 {
811 qemu_free_irqs(pci_dev->irq);
812 pci_dev->bus->devices[pci_dev->devfn] = NULL;
813 pci_config_free(pci_dev);
814 }
815
816 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
817 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
818 int instance_size, int devfn,
819 PCIConfigReadFunc *config_read,
820 PCIConfigWriteFunc *config_write)
821 {
822 PCIDevice *pci_dev;
823 PCIDeviceInfo info = {
824 .config_read = config_read,
825 .config_write = config_write,
826 };
827
828 pci_dev = qemu_mallocz(instance_size);
829 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
830 if (pci_dev == NULL) {
831 hw_error("PCI: can't register device\n");
832 }
833 return pci_dev;
834 }
835
836 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
837 target_phys_addr_t addr)
838 {
839 return addr + bus->mem_base;
840 }
841
842 static void pci_unregister_io_regions(PCIDevice *pci_dev)
843 {
844 PCIIORegion *r;
845 int i;
846
847 for(i = 0; i < PCI_NUM_REGIONS; i++) {
848 r = &pci_dev->io_regions[i];
849 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
850 continue;
851 if (r->memory) {
852 memory_region_del_subregion(r->address_space, r->memory);
853 } else {
854 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
855 isa_unassign_ioport(r->addr, r->filtered_size);
856 } else {
857 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
858 r->addr),
859 r->filtered_size,
860 IO_MEM_UNASSIGNED);
861 }
862 }
863 }
864 }
865
866 static int pci_unregister_device(DeviceState *dev)
867 {
868 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
869 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
870 int ret = 0;
871
872 if (info->exit)
873 ret = info->exit(pci_dev);
874 if (ret)
875 return ret;
876
877 pci_unregister_io_regions(pci_dev);
878 pci_del_option_rom(pci_dev);
879 qemu_free(pci_dev->romfile);
880 do_pci_unregister_device(pci_dev);
881 return 0;
882 }
883
884 void pci_register_bar_region(PCIDevice *pci_dev, int region_num,
885 uint8_t type, MemoryRegion *memory)
886 {
887 PCIIORegion *r;
888 uint32_t addr;
889 uint64_t wmask;
890 pcibus_t size = memory_region_size(memory);
891
892 assert(region_num >= 0);
893 assert(region_num < PCI_NUM_REGIONS);
894 if (size & (size-1)) {
895 fprintf(stderr, "ERROR: PCI region size must be pow2 "
896 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
897 exit(1);
898 }
899
900 r = &pci_dev->io_regions[region_num];
901 r->addr = PCI_BAR_UNMAPPED;
902 r->size = size;
903 r->filtered_size = size;
904 r->type = type;
905 r->memory = NULL;
906
907 wmask = ~(size - 1);
908 addr = pci_bar(pci_dev, region_num);
909 if (region_num == PCI_ROM_SLOT) {
910 /* ROM enable bit is writable */
911 wmask |= PCI_ROM_ADDRESS_ENABLE;
912 }
913 pci_set_long(pci_dev->config + addr, type);
914 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
915 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
916 pci_set_quad(pci_dev->wmask + addr, wmask);
917 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
918 } else {
919 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
920 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
921 }
922 pci_dev->io_regions[region_num].memory = memory;
923 pci_dev->io_regions[region_num].address_space
924 = type & PCI_BASE_ADDRESS_SPACE_IO
925 ? pci_dev->bus->address_space_io
926 : pci_dev->bus->address_space_mem;
927 }
928
929 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
930 {
931 return pci_dev->io_regions[region_num].addr;
932 }
933
934 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
935 uint8_t type)
936 {
937 pcibus_t base = *addr;
938 pcibus_t limit = *addr + *size - 1;
939 PCIDevice *br;
940
941 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
942 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
943
944 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
945 if (!(cmd & PCI_COMMAND_IO)) {
946 goto no_map;
947 }
948 } else {
949 if (!(cmd & PCI_COMMAND_MEMORY)) {
950 goto no_map;
951 }
952 }
953
954 base = MAX(base, pci_bridge_get_base(br, type));
955 limit = MIN(limit, pci_bridge_get_limit(br, type));
956 }
957
958 if (base > limit) {
959 goto no_map;
960 }
961 *addr = base;
962 *size = limit - base + 1;
963 return;
964 no_map:
965 *addr = PCI_BAR_UNMAPPED;
966 *size = 0;
967 }
968
969 static pcibus_t pci_bar_address(PCIDevice *d,
970 int reg, uint8_t type, pcibus_t size)
971 {
972 pcibus_t new_addr, last_addr;
973 int bar = pci_bar(d, reg);
974 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
975
976 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
977 if (!(cmd & PCI_COMMAND_IO)) {
978 return PCI_BAR_UNMAPPED;
979 }
980 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
981 last_addr = new_addr + size - 1;
982 /* NOTE: we have only 64K ioports on PC */
983 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
984 return PCI_BAR_UNMAPPED;
985 }
986 return new_addr;
987 }
988
989 if (!(cmd & PCI_COMMAND_MEMORY)) {
990 return PCI_BAR_UNMAPPED;
991 }
992 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
993 new_addr = pci_get_quad(d->config + bar);
994 } else {
995 new_addr = pci_get_long(d->config + bar);
996 }
997 /* the ROM slot has a specific enable bit */
998 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
999 return PCI_BAR_UNMAPPED;
1000 }
1001 new_addr &= ~(size - 1);
1002 last_addr = new_addr + size - 1;
1003 /* NOTE: we do not support wrapping */
1004 /* XXX: as we cannot support really dynamic
1005 mappings, we handle specific values as invalid
1006 mappings. */
1007 if (last_addr <= new_addr || new_addr == 0 ||
1008 last_addr == PCI_BAR_UNMAPPED) {
1009 return PCI_BAR_UNMAPPED;
1010 }
1011
1012 /* Now pcibus_t is 64bit.
1013 * Check if 32 bit BAR wraps around explicitly.
1014 * Without this, PC ide doesn't work well.
1015 * TODO: remove this work around.
1016 */
1017 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1018 return PCI_BAR_UNMAPPED;
1019 }
1020
1021 /*
1022 * OS is allowed to set BAR beyond its addressable
1023 * bits. For example, 32 bit OS can set 64bit bar
1024 * to >4G. Check it. TODO: we might need to support
1025 * it in the future for e.g. PAE.
1026 */
1027 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
1028 return PCI_BAR_UNMAPPED;
1029 }
1030
1031 return new_addr;
1032 }
1033
1034 static void pci_update_mappings(PCIDevice *d)
1035 {
1036 PCIIORegion *r;
1037 int i;
1038 pcibus_t new_addr, filtered_size;
1039
1040 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1041 r = &d->io_regions[i];
1042
1043 /* this region isn't registered */
1044 if (!r->size)
1045 continue;
1046
1047 new_addr = pci_bar_address(d, i, r->type, r->size);
1048
1049 /* bridge filtering */
1050 filtered_size = r->size;
1051 if (new_addr != PCI_BAR_UNMAPPED) {
1052 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
1053 }
1054
1055 /* This bar isn't changed */
1056 if (new_addr == r->addr && filtered_size == r->filtered_size)
1057 continue;
1058
1059 /* now do the real mapping */
1060 if (r->addr != PCI_BAR_UNMAPPED) {
1061 if (r->memory) {
1062 memory_region_del_subregion(r->address_space, r->memory);
1063 } else if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1064 int class;
1065 /* NOTE: specific hack for IDE in PC case:
1066 only one byte must be mapped. */
1067 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1068 if (class == 0x0101 && r->size == 4) {
1069 isa_unassign_ioport(r->addr + 2, 1);
1070 } else {
1071 isa_unassign_ioport(r->addr, r->filtered_size);
1072 }
1073 } else {
1074 cpu_register_physical_memory(pci_to_cpu_addr(d->bus,
1075 r->addr),
1076 r->filtered_size,
1077 IO_MEM_UNASSIGNED);
1078 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1079 }
1080 }
1081 r->addr = new_addr;
1082 r->filtered_size = filtered_size;
1083 if (r->addr != PCI_BAR_UNMAPPED) {
1084 /*
1085 * TODO: currently almost all the map funcions assumes
1086 * filtered_size == size and addr & ~(size - 1) == addr.
1087 * However with bridge filtering, they aren't always true.
1088 * Teach them such cases, such that filtered_size < size and
1089 * addr & (size - 1) != 0.
1090 */
1091 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1092 memory_region_add_subregion_overlap(r->address_space,
1093 r->addr,
1094 r->memory,
1095 1);
1096 } else {
1097 memory_region_add_subregion_overlap(r->address_space,
1098 pci_to_cpu_addr(d->bus,
1099 r->addr),
1100 r->memory,
1101 1);
1102 }
1103 }
1104 }
1105 }
1106
1107 static inline int pci_irq_disabled(PCIDevice *d)
1108 {
1109 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1110 }
1111
1112 /* Called after interrupt disabled field update in config space,
1113 * assert/deassert interrupts if necessary.
1114 * Gets original interrupt disable bit value (before update). */
1115 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1116 {
1117 int i, disabled = pci_irq_disabled(d);
1118 if (disabled == was_irq_disabled)
1119 return;
1120 for (i = 0; i < PCI_NUM_PINS; ++i) {
1121 int state = pci_irq_state(d, i);
1122 pci_change_irq_level(d, i, disabled ? -state : state);
1123 }
1124 }
1125
1126 uint32_t pci_default_read_config(PCIDevice *d,
1127 uint32_t address, int len)
1128 {
1129 uint32_t val = 0;
1130
1131 memcpy(&val, d->config + address, len);
1132 return le32_to_cpu(val);
1133 }
1134
1135 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1136 {
1137 int i, was_irq_disabled = pci_irq_disabled(d);
1138
1139 for (i = 0; i < l; val >>= 8, ++i) {
1140 uint8_t wmask = d->wmask[addr + i];
1141 uint8_t w1cmask = d->w1cmask[addr + i];
1142 assert(!(wmask & w1cmask));
1143 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1144 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1145 }
1146 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1147 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1148 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1149 range_covers_byte(addr, l, PCI_COMMAND))
1150 pci_update_mappings(d);
1151
1152 if (range_covers_byte(addr, l, PCI_COMMAND))
1153 pci_update_irq_disabled(d, was_irq_disabled);
1154 }
1155
1156 /***********************************************************/
1157 /* generic PCI irq support */
1158
1159 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1160 static void pci_set_irq(void *opaque, int irq_num, int level)
1161 {
1162 PCIDevice *pci_dev = opaque;
1163 int change;
1164
1165 change = level - pci_irq_state(pci_dev, irq_num);
1166 if (!change)
1167 return;
1168
1169 pci_set_irq_state(pci_dev, irq_num, level);
1170 pci_update_irq_status(pci_dev);
1171 if (pci_irq_disabled(pci_dev))
1172 return;
1173 pci_change_irq_level(pci_dev, irq_num, change);
1174 }
1175
1176 /***********************************************************/
1177 /* monitor info on PCI */
1178
1179 typedef struct {
1180 uint16_t class;
1181 const char *desc;
1182 const char *fw_name;
1183 uint16_t fw_ign_bits;
1184 } pci_class_desc;
1185
1186 static const pci_class_desc pci_class_descriptions[] =
1187 {
1188 { 0x0001, "VGA controller", "display"},
1189 { 0x0100, "SCSI controller", "scsi"},
1190 { 0x0101, "IDE controller", "ide"},
1191 { 0x0102, "Floppy controller", "fdc"},
1192 { 0x0103, "IPI controller", "ipi"},
1193 { 0x0104, "RAID controller", "raid"},
1194 { 0x0106, "SATA controller"},
1195 { 0x0107, "SAS controller"},
1196 { 0x0180, "Storage controller"},
1197 { 0x0200, "Ethernet controller", "ethernet"},
1198 { 0x0201, "Token Ring controller", "token-ring"},
1199 { 0x0202, "FDDI controller", "fddi"},
1200 { 0x0203, "ATM controller", "atm"},
1201 { 0x0280, "Network controller"},
1202 { 0x0300, "VGA controller", "display", 0x00ff},
1203 { 0x0301, "XGA controller"},
1204 { 0x0302, "3D controller"},
1205 { 0x0380, "Display controller"},
1206 { 0x0400, "Video controller", "video"},
1207 { 0x0401, "Audio controller", "sound"},
1208 { 0x0402, "Phone"},
1209 { 0x0403, "Audio controller", "sound"},
1210 { 0x0480, "Multimedia controller"},
1211 { 0x0500, "RAM controller", "memory"},
1212 { 0x0501, "Flash controller", "flash"},
1213 { 0x0580, "Memory controller"},
1214 { 0x0600, "Host bridge", "host"},
1215 { 0x0601, "ISA bridge", "isa"},
1216 { 0x0602, "EISA bridge", "eisa"},
1217 { 0x0603, "MC bridge", "mca"},
1218 { 0x0604, "PCI bridge", "pci"},
1219 { 0x0605, "PCMCIA bridge", "pcmcia"},
1220 { 0x0606, "NUBUS bridge", "nubus"},
1221 { 0x0607, "CARDBUS bridge", "cardbus"},
1222 { 0x0608, "RACEWAY bridge"},
1223 { 0x0680, "Bridge"},
1224 { 0x0700, "Serial port", "serial"},
1225 { 0x0701, "Parallel port", "parallel"},
1226 { 0x0800, "Interrupt controller", "interrupt-controller"},
1227 { 0x0801, "DMA controller", "dma-controller"},
1228 { 0x0802, "Timer", "timer"},
1229 { 0x0803, "RTC", "rtc"},
1230 { 0x0900, "Keyboard", "keyboard"},
1231 { 0x0901, "Pen", "pen"},
1232 { 0x0902, "Mouse", "mouse"},
1233 { 0x0A00, "Dock station", "dock", 0x00ff},
1234 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1235 { 0x0c00, "Fireware contorller", "fireware"},
1236 { 0x0c01, "Access bus controller", "access-bus"},
1237 { 0x0c02, "SSA controller", "ssa"},
1238 { 0x0c03, "USB controller", "usb"},
1239 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1240 { 0, NULL}
1241 };
1242
1243 static void pci_for_each_device_under_bus(PCIBus *bus,
1244 void (*fn)(PCIBus *b, PCIDevice *d))
1245 {
1246 PCIDevice *d;
1247 int devfn;
1248
1249 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1250 d = bus->devices[devfn];
1251 if (d) {
1252 fn(bus, d);
1253 }
1254 }
1255 }
1256
1257 void pci_for_each_device(PCIBus *bus, int bus_num,
1258 void (*fn)(PCIBus *b, PCIDevice *d))
1259 {
1260 bus = pci_find_bus(bus, bus_num);
1261
1262 if (bus) {
1263 pci_for_each_device_under_bus(bus, fn);
1264 }
1265 }
1266
1267 static void pci_device_print(Monitor *mon, QDict *device)
1268 {
1269 QDict *qdict;
1270 QListEntry *entry;
1271 uint64_t addr, size;
1272
1273 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1274 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1275 qdict_get_int(device, "slot"),
1276 qdict_get_int(device, "function"));
1277 monitor_printf(mon, " ");
1278
1279 qdict = qdict_get_qdict(device, "class_info");
1280 if (qdict_haskey(qdict, "desc")) {
1281 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1282 } else {
1283 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1284 }
1285
1286 qdict = qdict_get_qdict(device, "id");
1287 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1288 qdict_get_int(qdict, "device"),
1289 qdict_get_int(qdict, "vendor"));
1290
1291 if (qdict_haskey(device, "irq")) {
1292 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1293 qdict_get_int(device, "irq"));
1294 }
1295
1296 if (qdict_haskey(device, "pci_bridge")) {
1297 QDict *info;
1298
1299 qdict = qdict_get_qdict(device, "pci_bridge");
1300
1301 info = qdict_get_qdict(qdict, "bus");
1302 monitor_printf(mon, " BUS %" PRId64 ".\n",
1303 qdict_get_int(info, "number"));
1304 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1305 qdict_get_int(info, "secondary"));
1306 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1307 qdict_get_int(info, "subordinate"));
1308
1309 info = qdict_get_qdict(qdict, "io_range");
1310 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1311 qdict_get_int(info, "base"),
1312 qdict_get_int(info, "limit"));
1313
1314 info = qdict_get_qdict(qdict, "memory_range");
1315 monitor_printf(mon,
1316 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1317 qdict_get_int(info, "base"),
1318 qdict_get_int(info, "limit"));
1319
1320 info = qdict_get_qdict(qdict, "prefetchable_range");
1321 monitor_printf(mon, " prefetchable memory range "
1322 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1323 qdict_get_int(info, "base"),
1324 qdict_get_int(info, "limit"));
1325 }
1326
1327 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1328 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1329 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1330
1331 addr = qdict_get_int(qdict, "address");
1332 size = qdict_get_int(qdict, "size");
1333
1334 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1335 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1336 " [0x%04"FMT_PCIBUS"].\n",
1337 addr, addr + size - 1);
1338 } else {
1339 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1340 " [0x%08"FMT_PCIBUS"].\n",
1341 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1342 qdict_get_bool(qdict, "prefetch") ?
1343 " prefetchable" : "", addr, addr + size - 1);
1344 }
1345 }
1346
1347 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1348
1349 if (qdict_haskey(device, "pci_bridge")) {
1350 qdict = qdict_get_qdict(device, "pci_bridge");
1351 if (qdict_haskey(qdict, "devices")) {
1352 QListEntry *dev;
1353 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1354 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1355 }
1356 }
1357 }
1358 }
1359
1360 void do_pci_info_print(Monitor *mon, const QObject *data)
1361 {
1362 QListEntry *bus, *dev;
1363
1364 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1365 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1366 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1367 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1368 }
1369 }
1370 }
1371
1372 static QObject *pci_get_dev_class(const PCIDevice *dev)
1373 {
1374 int class;
1375 const pci_class_desc *desc;
1376
1377 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1378 desc = pci_class_descriptions;
1379 while (desc->desc && class != desc->class)
1380 desc++;
1381
1382 if (desc->desc) {
1383 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1384 desc->desc, class);
1385 } else {
1386 return qobject_from_jsonf("{ 'class': %d }", class);
1387 }
1388 }
1389
1390 static QObject *pci_get_dev_id(const PCIDevice *dev)
1391 {
1392 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1393 pci_get_word(dev->config + PCI_VENDOR_ID),
1394 pci_get_word(dev->config + PCI_DEVICE_ID));
1395 }
1396
1397 static QObject *pci_get_regions_list(const PCIDevice *dev)
1398 {
1399 int i;
1400 QList *regions_list;
1401
1402 regions_list = qlist_new();
1403
1404 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1405 QObject *obj;
1406 const PCIIORegion *r = &dev->io_regions[i];
1407
1408 if (!r->size) {
1409 continue;
1410 }
1411
1412 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1413 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1414 "'address': %" PRId64 ", "
1415 "'size': %" PRId64 " }",
1416 i, r->addr, r->size);
1417 } else {
1418 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1419
1420 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1421 "'mem_type_64': %i, 'prefetch': %i, "
1422 "'address': %" PRId64 ", "
1423 "'size': %" PRId64 " }",
1424 i, mem_type_64,
1425 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1426 r->addr, r->size);
1427 }
1428
1429 qlist_append_obj(regions_list, obj);
1430 }
1431
1432 return QOBJECT(regions_list);
1433 }
1434
1435 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1436
1437 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1438 {
1439 uint8_t type;
1440 QObject *obj;
1441
1442 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1443 " 'qdev_id': %s }",
1444 bus_num,
1445 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1446 pci_get_dev_class(dev), pci_get_dev_id(dev),
1447 pci_get_regions_list(dev),
1448 dev->qdev.id ? dev->qdev.id : "");
1449
1450 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1451 QDict *qdict = qobject_to_qdict(obj);
1452 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1453 }
1454
1455 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1456 if (type == PCI_HEADER_TYPE_BRIDGE) {
1457 QDict *qdict;
1458 QObject *pci_bridge;
1459
1460 pci_bridge = qobject_from_jsonf("{ 'bus': "
1461 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1462 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1463 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1464 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1465 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1466 dev->config[PCI_SUBORDINATE_BUS],
1467 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1468 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1469 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1470 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1471 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1472 PCI_BASE_ADDRESS_MEM_PREFETCH),
1473 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1474 PCI_BASE_ADDRESS_MEM_PREFETCH));
1475
1476 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1477 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1478
1479 if (child_bus) {
1480 qdict = qobject_to_qdict(pci_bridge);
1481 qdict_put_obj(qdict, "devices",
1482 pci_get_devices_list(child_bus,
1483 dev->config[PCI_SECONDARY_BUS]));
1484 }
1485 }
1486 qdict = qobject_to_qdict(obj);
1487 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1488 }
1489
1490 return obj;
1491 }
1492
1493 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1494 {
1495 int devfn;
1496 PCIDevice *dev;
1497 QList *dev_list;
1498
1499 dev_list = qlist_new();
1500
1501 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1502 dev = bus->devices[devfn];
1503 if (dev) {
1504 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1505 }
1506 }
1507
1508 return QOBJECT(dev_list);
1509 }
1510
1511 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1512 {
1513 bus = pci_find_bus(bus, bus_num);
1514 if (bus) {
1515 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1516 bus_num, pci_get_devices_list(bus, bus_num));
1517 }
1518
1519 return NULL;
1520 }
1521
1522 void do_pci_info(Monitor *mon, QObject **ret_data)
1523 {
1524 QList *bus_list;
1525 struct PCIHostBus *host;
1526
1527 bus_list = qlist_new();
1528
1529 QLIST_FOREACH(host, &host_buses, next) {
1530 QObject *obj = pci_get_bus_dict(host->bus, 0);
1531 if (obj) {
1532 qlist_append_obj(bus_list, obj);
1533 }
1534 }
1535
1536 *ret_data = QOBJECT(bus_list);
1537 }
1538
1539 static const char * const pci_nic_models[] = {
1540 "ne2k_pci",
1541 "i82551",
1542 "i82557b",
1543 "i82559er",
1544 "rtl8139",
1545 "e1000",
1546 "pcnet",
1547 "virtio",
1548 NULL
1549 };
1550
1551 static const char * const pci_nic_names[] = {
1552 "ne2k_pci",
1553 "i82551",
1554 "i82557b",
1555 "i82559er",
1556 "rtl8139",
1557 "e1000",
1558 "pcnet",
1559 "virtio-net-pci",
1560 NULL
1561 };
1562
1563 /* Initialize a PCI NIC. */
1564 /* FIXME callers should check for failure, but don't */
1565 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1566 const char *default_devaddr)
1567 {
1568 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1569 PCIBus *bus;
1570 int devfn;
1571 PCIDevice *pci_dev;
1572 DeviceState *dev;
1573 int i;
1574
1575 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1576 if (i < 0)
1577 return NULL;
1578
1579 bus = pci_get_bus_devfn(&devfn, devaddr);
1580 if (!bus) {
1581 error_report("Invalid PCI device address %s for device %s",
1582 devaddr, pci_nic_names[i]);
1583 return NULL;
1584 }
1585
1586 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1587 dev = &pci_dev->qdev;
1588 qdev_set_nic_properties(dev, nd);
1589 if (qdev_init(dev) < 0)
1590 return NULL;
1591 return pci_dev;
1592 }
1593
1594 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1595 const char *default_devaddr)
1596 {
1597 PCIDevice *res;
1598
1599 if (qemu_show_nic_models(nd->model, pci_nic_models))
1600 exit(0);
1601
1602 res = pci_nic_init(nd, default_model, default_devaddr);
1603 if (!res)
1604 exit(1);
1605 return res;
1606 }
1607
1608 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1609 {
1610 pci_update_mappings(d);
1611 }
1612
1613 void pci_bridge_update_mappings(PCIBus *b)
1614 {
1615 PCIBus *child;
1616
1617 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1618
1619 QLIST_FOREACH(child, &b->child, sibling) {
1620 pci_bridge_update_mappings(child);
1621 }
1622 }
1623
1624 /* Whether a given bus number is in range of the secondary
1625 * bus of the given bridge device. */
1626 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1627 {
1628 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1629 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1630 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1631 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1632 }
1633
1634 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1635 {
1636 PCIBus *sec;
1637
1638 if (!bus) {
1639 return NULL;
1640 }
1641
1642 if (pci_bus_num(bus) == bus_num) {
1643 return bus;
1644 }
1645
1646 /* Consider all bus numbers in range for the host pci bridge. */
1647 if (bus->parent_dev &&
1648 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1649 return NULL;
1650 }
1651
1652 /* try child bus */
1653 for (; bus; bus = sec) {
1654 QLIST_FOREACH(sec, &bus->child, sibling) {
1655 assert(sec->parent_dev);
1656 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1657 return sec;
1658 }
1659 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1660 break;
1661 }
1662 }
1663 }
1664
1665 return NULL;
1666 }
1667
1668 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1669 {
1670 bus = pci_find_bus(bus, bus_num);
1671
1672 if (!bus)
1673 return NULL;
1674
1675 return bus->devices[devfn];
1676 }
1677
1678 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1679 {
1680 PCIDevice *pci_dev = (PCIDevice *)qdev;
1681 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1682 PCIBus *bus;
1683 int rc;
1684 bool is_default_rom;
1685
1686 /* initialize cap_present for pci_is_express() and pci_config_size() */
1687 if (info->is_express) {
1688 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1689 }
1690
1691 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1692 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1693 pci_dev->devfn, info);
1694 if (pci_dev == NULL)
1695 return -1;
1696 if (qdev->hotplugged && info->no_hotplug) {
1697 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1698 do_pci_unregister_device(pci_dev);
1699 return -1;
1700 }
1701 if (info->init) {
1702 rc = info->init(pci_dev);
1703 if (rc != 0) {
1704 do_pci_unregister_device(pci_dev);
1705 return rc;
1706 }
1707 }
1708
1709 /* rom loading */
1710 is_default_rom = false;
1711 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1712 pci_dev->romfile = qemu_strdup(info->romfile);
1713 is_default_rom = true;
1714 }
1715 pci_add_option_rom(pci_dev, is_default_rom);
1716
1717 if (bus->hotplug) {
1718 /* Let buses differentiate between hotplug and when device is
1719 * enabled during qemu machine creation. */
1720 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1721 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1722 PCI_COLDPLUG_ENABLED);
1723 if (rc != 0) {
1724 int r = pci_unregister_device(&pci_dev->qdev);
1725 assert(!r);
1726 return rc;
1727 }
1728 }
1729 return 0;
1730 }
1731
1732 static int pci_unplug_device(DeviceState *qdev)
1733 {
1734 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1735 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1736
1737 if (info->no_hotplug) {
1738 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1739 return -1;
1740 }
1741 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1742 PCI_HOTPLUG_DISABLED);
1743 }
1744
1745 void pci_qdev_register(PCIDeviceInfo *info)
1746 {
1747 info->qdev.init = pci_qdev_init;
1748 info->qdev.unplug = pci_unplug_device;
1749 info->qdev.exit = pci_unregister_device;
1750 info->qdev.bus_info = &pci_bus_info;
1751 qdev_register(&info->qdev);
1752 }
1753
1754 void pci_qdev_register_many(PCIDeviceInfo *info)
1755 {
1756 while (info->qdev.name) {
1757 pci_qdev_register(info);
1758 info++;
1759 }
1760 }
1761
1762 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1763 const char *name)
1764 {
1765 DeviceState *dev;
1766
1767 dev = qdev_create(&bus->qbus, name);
1768 qdev_prop_set_uint32(dev, "addr", devfn);
1769 qdev_prop_set_bit(dev, "multifunction", multifunction);
1770 return DO_UPCAST(PCIDevice, qdev, dev);
1771 }
1772
1773 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1774 bool multifunction,
1775 const char *name)
1776 {
1777 DeviceState *dev;
1778
1779 dev = qdev_try_create(&bus->qbus, name);
1780 if (!dev) {
1781 return NULL;
1782 }
1783 qdev_prop_set_uint32(dev, "addr", devfn);
1784 qdev_prop_set_bit(dev, "multifunction", multifunction);
1785 return DO_UPCAST(PCIDevice, qdev, dev);
1786 }
1787
1788 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1789 bool multifunction,
1790 const char *name)
1791 {
1792 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1793 qdev_init_nofail(&dev->qdev);
1794 return dev;
1795 }
1796
1797 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1798 {
1799 return pci_create_multifunction(bus, devfn, false, name);
1800 }
1801
1802 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1803 {
1804 return pci_create_simple_multifunction(bus, devfn, false, name);
1805 }
1806
1807 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1808 {
1809 return pci_try_create_multifunction(bus, devfn, false, name);
1810 }
1811
1812 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1813 {
1814 int config_size = pci_config_size(pdev);
1815 int offset = PCI_CONFIG_HEADER_SIZE;
1816 int i;
1817 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1818 if (pdev->used[i])
1819 offset = i + 1;
1820 else if (i - offset + 1 == size)
1821 return offset;
1822 return 0;
1823 }
1824
1825 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1826 uint8_t *prev_p)
1827 {
1828 uint8_t next, prev;
1829
1830 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1831 return 0;
1832
1833 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1834 prev = next + PCI_CAP_LIST_NEXT)
1835 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1836 break;
1837
1838 if (prev_p)
1839 *prev_p = prev;
1840 return next;
1841 }
1842
1843 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1844 This is needed for an option rom which is used for more than one device. */
1845 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1846 {
1847 uint16_t vendor_id;
1848 uint16_t device_id;
1849 uint16_t rom_vendor_id;
1850 uint16_t rom_device_id;
1851 uint16_t rom_magic;
1852 uint16_t pcir_offset;
1853 uint8_t checksum;
1854
1855 /* Words in rom data are little endian (like in PCI configuration),
1856 so they can be read / written with pci_get_word / pci_set_word. */
1857
1858 /* Only a valid rom will be patched. */
1859 rom_magic = pci_get_word(ptr);
1860 if (rom_magic != 0xaa55) {
1861 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1862 return;
1863 }
1864 pcir_offset = pci_get_word(ptr + 0x18);
1865 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1866 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1867 return;
1868 }
1869
1870 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1871 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1872 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1873 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1874
1875 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1876 vendor_id, device_id, rom_vendor_id, rom_device_id);
1877
1878 checksum = ptr[6];
1879
1880 if (vendor_id != rom_vendor_id) {
1881 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1882 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1883 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1884 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1885 ptr[6] = checksum;
1886 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1887 }
1888
1889 if (device_id != rom_device_id) {
1890 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1891 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1892 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1893 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1894 ptr[6] = checksum;
1895 pci_set_word(ptr + pcir_offset + 6, device_id);
1896 }
1897 }
1898
1899 /* Add an option rom for the device */
1900 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1901 {
1902 int size;
1903 char *path;
1904 void *ptr;
1905 char name[32];
1906
1907 if (!pdev->romfile)
1908 return 0;
1909 if (strlen(pdev->romfile) == 0)
1910 return 0;
1911
1912 if (!pdev->rom_bar) {
1913 /*
1914 * Load rom via fw_cfg instead of creating a rom bar,
1915 * for 0.11 compatibility.
1916 */
1917 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1918 if (class == 0x0300) {
1919 rom_add_vga(pdev->romfile);
1920 } else {
1921 rom_add_option(pdev->romfile, -1);
1922 }
1923 return 0;
1924 }
1925
1926 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1927 if (path == NULL) {
1928 path = qemu_strdup(pdev->romfile);
1929 }
1930
1931 size = get_image_size(path);
1932 if (size < 0) {
1933 error_report("%s: failed to find romfile \"%s\"",
1934 __FUNCTION__, pdev->romfile);
1935 qemu_free(path);
1936 return -1;
1937 }
1938 if (size & (size - 1)) {
1939 size = 1 << qemu_fls(size);
1940 }
1941
1942 if (pdev->qdev.info->vmsd)
1943 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1944 else
1945 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1946 pdev->has_rom = true;
1947 memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
1948 ptr = memory_region_get_ram_ptr(&pdev->rom);
1949 load_image(path, ptr);
1950 qemu_free(path);
1951
1952 if (is_default_rom) {
1953 /* Only the default rom images will be patched (if needed). */
1954 pci_patch_ids(pdev, ptr, size);
1955 }
1956
1957 qemu_put_ram_ptr(ptr);
1958
1959 pci_register_bar_region(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1960
1961 return 0;
1962 }
1963
1964 static void pci_del_option_rom(PCIDevice *pdev)
1965 {
1966 if (!pdev->has_rom)
1967 return;
1968
1969 memory_region_destroy(&pdev->rom);
1970 pdev->has_rom = false;
1971 }
1972
1973 /*
1974 * if !offset
1975 * Reserve space and add capability to the linked list in pci config space
1976 *
1977 * if offset = 0,
1978 * Find and reserve space and add capability to the linked list
1979 * in pci config space */
1980 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1981 uint8_t offset, uint8_t size)
1982 {
1983 uint8_t *config;
1984 if (!offset) {
1985 offset = pci_find_space(pdev, size);
1986 if (!offset) {
1987 return -ENOSPC;
1988 }
1989 }
1990
1991 config = pdev->config + offset;
1992 config[PCI_CAP_LIST_ID] = cap_id;
1993 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1994 pdev->config[PCI_CAPABILITY_LIST] = offset;
1995 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1996 memset(pdev->used + offset, 0xFF, size);
1997 /* Make capability read-only by default */
1998 memset(pdev->wmask + offset, 0, size);
1999 /* Check capability by default */
2000 memset(pdev->cmask + offset, 0xFF, size);
2001 return offset;
2002 }
2003
2004 /* Unlink capability from the pci config space. */
2005 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2006 {
2007 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2008 if (!offset)
2009 return;
2010 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2011 /* Make capability writable again */
2012 memset(pdev->wmask + offset, 0xff, size);
2013 memset(pdev->w1cmask + offset, 0, size);
2014 /* Clear cmask as device-specific registers can't be checked */
2015 memset(pdev->cmask + offset, 0, size);
2016 memset(pdev->used + offset, 0, size);
2017
2018 if (!pdev->config[PCI_CAPABILITY_LIST])
2019 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2020 }
2021
2022 /* Reserve space for capability at a known offset (to call after load). */
2023 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
2024 {
2025 memset(pdev->used + offset, 0xff, size);
2026 }
2027
2028 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2029 {
2030 return pci_find_capability_list(pdev, cap_id, NULL);
2031 }
2032
2033 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2034 {
2035 PCIDevice *d = (PCIDevice *)dev;
2036 const pci_class_desc *desc;
2037 char ctxt[64];
2038 PCIIORegion *r;
2039 int i, class;
2040
2041 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2042 desc = pci_class_descriptions;
2043 while (desc->desc && class != desc->class)
2044 desc++;
2045 if (desc->desc) {
2046 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2047 } else {
2048 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2049 }
2050
2051 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2052 "pci id %04x:%04x (sub %04x:%04x)\n",
2053 indent, "", ctxt, pci_bus_num(d->bus),
2054 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2055 pci_get_word(d->config + PCI_VENDOR_ID),
2056 pci_get_word(d->config + PCI_DEVICE_ID),
2057 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2058 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2059 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2060 r = &d->io_regions[i];
2061 if (!r->size)
2062 continue;
2063 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2064 " [0x%"FMT_PCIBUS"]\n",
2065 indent, "",
2066 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2067 r->addr, r->addr + r->size - 1);
2068 }
2069 }
2070
2071 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2072 {
2073 PCIDevice *d = (PCIDevice *)dev;
2074 const char *name = NULL;
2075 const pci_class_desc *desc = pci_class_descriptions;
2076 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2077
2078 while (desc->desc &&
2079 (class & ~desc->fw_ign_bits) !=
2080 (desc->class & ~desc->fw_ign_bits)) {
2081 desc++;
2082 }
2083
2084 if (desc->desc) {
2085 name = desc->fw_name;
2086 }
2087
2088 if (name) {
2089 pstrcpy(buf, len, name);
2090 } else {
2091 snprintf(buf, len, "pci%04x,%04x",
2092 pci_get_word(d->config + PCI_VENDOR_ID),
2093 pci_get_word(d->config + PCI_DEVICE_ID));
2094 }
2095
2096 return buf;
2097 }
2098
2099 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2100 {
2101 PCIDevice *d = (PCIDevice *)dev;
2102 char path[50], name[33];
2103 int off;
2104
2105 off = snprintf(path, sizeof(path), "%s@%x",
2106 pci_dev_fw_name(dev, name, sizeof name),
2107 PCI_SLOT(d->devfn));
2108 if (PCI_FUNC(d->devfn))
2109 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2110 return strdup(path);
2111 }
2112
2113 static char *pcibus_get_dev_path(DeviceState *dev)
2114 {
2115 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2116 PCIDevice *t;
2117 int slot_depth;
2118 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2119 * 00 is added here to make this format compatible with
2120 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2121 * Slot.Function list specifies the slot and function numbers for all
2122 * devices on the path from root to the specific device. */
2123 char domain[] = "DDDD:00";
2124 char slot[] = ":SS.F";
2125 int domain_len = sizeof domain - 1 /* For '\0' */;
2126 int slot_len = sizeof slot - 1 /* For '\0' */;
2127 int path_len;
2128 char *path, *p;
2129 int s;
2130
2131 /* Calculate # of slots on path between device and root. */;
2132 slot_depth = 0;
2133 for (t = d; t; t = t->bus->parent_dev) {
2134 ++slot_depth;
2135 }
2136
2137 path_len = domain_len + slot_len * slot_depth;
2138
2139 /* Allocate memory, fill in the terminating null byte. */
2140 path = qemu_malloc(path_len + 1 /* For '\0' */);
2141 path[path_len] = '\0';
2142
2143 /* First field is the domain. */
2144 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2145 assert(s == domain_len);
2146 memcpy(path, domain, domain_len);
2147
2148 /* Fill in slot numbers. We walk up from device to root, so need to print
2149 * them in the reverse order, last to first. */
2150 p = path + path_len;
2151 for (t = d; t; t = t->bus->parent_dev) {
2152 p -= slot_len;
2153 s = snprintf(slot, sizeof slot, ":%02x.%x",
2154 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2155 assert(s == slot_len);
2156 memcpy(p, slot, slot_len);
2157 }
2158
2159 return path;
2160 }
2161
2162 static int pci_qdev_find_recursive(PCIBus *bus,
2163 const char *id, PCIDevice **pdev)
2164 {
2165 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2166 if (!qdev) {
2167 return -ENODEV;
2168 }
2169
2170 /* roughly check if given qdev is pci device */
2171 if (qdev->info->init == &pci_qdev_init &&
2172 qdev->parent_bus->info == &pci_bus_info) {
2173 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2174 return 0;
2175 }
2176 return -EINVAL;
2177 }
2178
2179 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2180 {
2181 struct PCIHostBus *host;
2182 int rc = -ENODEV;
2183
2184 QLIST_FOREACH(host, &host_buses, next) {
2185 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2186 if (!tmp) {
2187 rc = 0;
2188 break;
2189 }
2190 if (tmp != -ENODEV) {
2191 rc = tmp;
2192 }
2193 }
2194
2195 return rc;
2196 }
Qemu copy for testing