hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79
  80 #define FMT_PCIBUS                      PRIx64
  81
  82 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  83                                 uint32_t address, uint32_t data, int len);
  84 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, int len);
  86 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  87                                 pcibus_t addr, pcibus_t size, int type);
  88 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
  89
  90 typedef struct PCIIORegion {
  91     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  93     pcibus_t size;
  94     uint8_t type;
  95     MemoryRegion *memory;
  96     MemoryRegion *address_space;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129     /* Standard hot plug controller. */
 130 #define QEMU_PCI_SHPC_BITNR 5
 131     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 132 #define QEMU_PCI_SLOTID_BITNR 6
 133     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 134 };
 135
 136 #define TYPE_PCI_DEVICE "pci-device"
 137 #define PCI_DEVICE(obj) \
 138      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 139 #define PCI_DEVICE_CLASS(klass) \
 140      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 141 #define PCI_DEVICE_GET_CLASS(obj) \
 142      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 143
 144 typedef struct PCIINTxRoute {
 145     enum {
 146         PCI_INTX_ENABLED,
 147         PCI_INTX_INVERTED,
 148         PCI_INTX_DISABLED,
 149     } mode;
 150     int irq;
 151 } PCIINTxRoute;
 152
 153 typedef struct PCIDeviceClass {
 154     DeviceClass parent_class;
 155
 156     int (*init)(PCIDevice *dev);
 157     PCIUnregisterFunc *exit;
 158     PCIConfigReadFunc *config_read;
 159     PCIConfigWriteFunc *config_write;
 160
 161     uint16_t vendor_id;
 162     uint16_t device_id;
 163     uint8_t revision;
 164     uint16_t class_id;
 165     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 166     uint16_t subsystem_id;              /* only for header type = 0 */
 167
 168     /*
 169      * pci-to-pci bridge or normal device.
 170      * This doesn't mean pci host switch.
 171      * When card bus bridge is supported, this would be enhanced.
 172      */
 173     int is_bridge;
 174
 175     /* pcie stuff */
 176     int is_express;   /* is this device pci express? */
 177
 178     /* device isn't hot-pluggable */
 179     int no_hotplug;
 180
 181     /* rom bar */
 182     const char *romfile;
 183 } PCIDeviceClass;
 184
 185 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 186                                       MSIMessage msg);
 187 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 188
 189 struct PCIDevice {
 190     DeviceState qdev;
 191     /* PCI config space */
 192     uint8_t *config;
 193
 194     /* Used to enable config checks on load. Note that writable bits are
 195      * never checked even if set in cmask. */
 196     uint8_t *cmask;
 197
 198     /* Used to implement R/W bytes */
 199     uint8_t *wmask;
 200
 201     /* Used to implement RW1C(Write 1 to Clear) bytes */
 202     uint8_t *w1cmask;
 203
 204     /* Used to allocate config space for capabilities. */
 205     uint8_t *used;
 206
 207     /* the following fields are read only */
 208     PCIBus *bus;
 209     uint32_t devfn;
 210     char name[64];
 211     PCIIORegion io_regions[PCI_NUM_REGIONS];
 212
 213     /* do not access the following fields */
 214     PCIConfigReadFunc *config_read;
 215     PCIConfigWriteFunc *config_write;
 216
 217     /* IRQ objects for the INTA-INTD pins.  */
 218     qemu_irq *irq;
 219
 220     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 221     uint8_t irq_state;
 222
 223     /* Capability bits */
 224     uint32_t cap_present;
 225
 226     /* Offset of MSI-X capability in config space */
 227     uint8_t msix_cap;
 228
 229     /* MSI-X entries */
 230     int msix_entries_nr;
 231
 232     /* Space to store MSIX table & pending bit array */
 233     uint8_t *msix_table;
 234     uint8_t *msix_pba;
 235     /* MemoryRegion container for msix exclusive BAR setup */
 236     MemoryRegion msix_exclusive_bar;
 237     /* Memory Regions for MSIX table and pending bit entries. */
 238     MemoryRegion msix_table_mmio;
 239     MemoryRegion msix_pba_mmio;
 240     /* Reference-count for entries actually in use by driver. */
 241     unsigned *msix_entry_used;
 242     /* MSIX function mask set or MSIX disabled */
 243     bool msix_function_masked;
 244     /* Version id needed for VMState */
 245     int32_t version_id;
 246
 247     /* Offset of MSI capability in config space */
 248     uint8_t msi_cap;
 249
 250     /* PCI Express */
 251     PCIExpressDevice exp;
 252
 253     /* SHPC */
 254     SHPCDevice *shpc;
 255
 256     /* Location of option rom */
 257     char *romfile;
 258     bool has_rom;
 259     MemoryRegion rom;
 260     uint32_t rom_bar;
 261
 262     /* MSI-X notifiers */
 263     MSIVectorUseNotifier msix_vector_use_notifier;
 264     MSIVectorReleaseNotifier msix_vector_release_notifier;
 265 };
 266
 267 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 268                       uint8_t attr, MemoryRegion *memory);
 269 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 270
 271 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 272                        uint8_t offset, uint8_t size);
 273
 274 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 275
 276 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 277
 278
 279 uint32_t pci_default_read_config(PCIDevice *d,
 280                                  uint32_t address, int len);
 281 void pci_default_write_config(PCIDevice *d,
 282                               uint32_t address, uint32_t val, int len);
 283 void pci_device_save(PCIDevice *s, QEMUFile *f);
 284 int pci_device_load(PCIDevice *s, QEMUFile *f);
 285 MemoryRegion *pci_address_space(PCIDevice *dev);
 286 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 287
 288 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 289 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 290 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 291
 292 typedef enum {
 293     PCI_HOTPLUG_DISABLED,
 294     PCI_HOTPLUG_ENABLED,
 295     PCI_COLDPLUG_ENABLED,
 296 } PCIHotplugState;
 297
 298 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 299                               PCIHotplugState state);
 300 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 301                          const char *name,
 302                          MemoryRegion *address_space_mem,
 303                          MemoryRegion *address_space_io,
 304                          uint8_t devfn_min);
 305 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 306                     MemoryRegion *address_space_mem,
 307                     MemoryRegion *address_space_io,
 308                     uint8_t devfn_min);
 309 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 310                   void *irq_opaque, int nirq);
 311 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 312 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 313 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 314                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 315                          void *irq_opaque,
 316                          MemoryRegion *address_space_mem,
 317                          MemoryRegion *address_space_io,
 318                          uint8_t devfn_min, int nirq);
 319 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 320 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 321 void pci_device_reset(PCIDevice *dev);
 322 void pci_bus_reset(PCIBus *bus);
 323
 324 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 325                         const char *default_devaddr);
 326 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 327                                const char *default_devaddr);
 328 int pci_bus_num(PCIBus *s);
 329 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 330 PCIBus *pci_find_root_bus(int domain);
 331 int pci_find_domain(const PCIBus *bus);
 332 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 333 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 334 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 335
 336 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 337                      unsigned *slotp);
 338
 339 void pci_device_deassert_intx(PCIDevice *dev);
 340
 341 static inline void
 342 pci_set_byte(uint8_t *config, uint8_t val)
 343 {
 344     *config = val;
 345 }
 346
 347 static inline uint8_t
 348 pci_get_byte(const uint8_t *config)
 349 {
 350     return *config;
 351 }
 352
 353 static inline void
 354 pci_set_word(uint8_t *config, uint16_t val)
 355 {
 356     cpu_to_le16wu((uint16_t *)config, val);
 357 }
 358
 359 static inline uint16_t
 360 pci_get_word(const uint8_t *config)
 361 {
 362     return le16_to_cpupu((const uint16_t *)config);
 363 }
 364
 365 static inline void
 366 pci_set_long(uint8_t *config, uint32_t val)
 367 {
 368     cpu_to_le32wu((uint32_t *)config, val);
 369 }
 370
 371 static inline uint32_t
 372 pci_get_long(const uint8_t *config)
 373 {
 374     return le32_to_cpupu((const uint32_t *)config);
 375 }
 376
 377 static inline void
 378 pci_set_quad(uint8_t *config, uint64_t val)
 379 {
 380     cpu_to_le64w((uint64_t *)config, val);
 381 }
 382
 383 static inline uint64_t
 384 pci_get_quad(const uint8_t *config)
 385 {
 386     return le64_to_cpup((const uint64_t *)config);
 387 }
 388
 389 static inline void
 390 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 391 {
 392     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 393 }
 394
 395 static inline void
 396 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 397 {
 398     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 399 }
 400
 401 static inline void
 402 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 403 {
 404     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 405 }
 406
 407 static inline void
 408 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 409 {
 410     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 411 }
 412
 413 static inline void
 414 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 415 {
 416     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 417 }
 418
 419 static inline void
 420 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 421 {
 422     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 423 }
 424
 425 /*
 426  * helper functions to do bit mask operation on configuration space.
 427  * Just to set bit, use test-and-set and discard returned value.
 428  * Just to clear bit, use test-and-clear and discard returned value.
 429  * NOTE: They aren't atomic.
 430  */
 431 static inline uint8_t
 432 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 433 {
 434     uint8_t val = pci_get_byte(config);
 435     pci_set_byte(config, val & ~mask);
 436     return val & mask;
 437 }
 438
 439 static inline uint8_t
 440 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 441 {
 442     uint8_t val = pci_get_byte(config);
 443     pci_set_byte(config, val | mask);
 444     return val & mask;
 445 }
 446
 447 static inline uint16_t
 448 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 449 {
 450     uint16_t val = pci_get_word(config);
 451     pci_set_word(config, val & ~mask);
 452     return val & mask;
 453 }
 454
 455 static inline uint16_t
 456 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 457 {
 458     uint16_t val = pci_get_word(config);
 459     pci_set_word(config, val | mask);
 460     return val & mask;
 461 }
 462
 463 static inline uint32_t
 464 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 465 {
 466     uint32_t val = pci_get_long(config);
 467     pci_set_long(config, val & ~mask);
 468     return val & mask;
 469 }
 470
 471 static inline uint32_t
 472 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 473 {
 474     uint32_t val = pci_get_long(config);
 475     pci_set_long(config, val | mask);
 476     return val & mask;
 477 }
 478
 479 static inline uint64_t
 480 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 481 {
 482     uint64_t val = pci_get_quad(config);
 483     pci_set_quad(config, val & ~mask);
 484     return val & mask;
 485 }
 486
 487 static inline uint64_t
 488 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 489 {
 490     uint64_t val = pci_get_quad(config);
 491     pci_set_quad(config, val | mask);
 492     return val & mask;
 493 }
 494
 495 /* Access a register specified by a mask */
 496 static inline void
 497 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 498 {
 499     uint8_t val = pci_get_byte(config);
 500     uint8_t rval = reg << (ffs(mask) - 1);
 501     pci_set_byte(config, (~mask & val) | (mask & rval));
 502 }
 503
 504 static inline uint8_t
 505 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 506 {
 507     uint8_t val = pci_get_byte(config);
 508     return (val & mask) >> (ffs(mask) - 1);
 509 }
 510
 511 static inline void
 512 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 513 {
 514     uint16_t val = pci_get_word(config);
 515     uint16_t rval = reg << (ffs(mask) - 1);
 516     pci_set_word(config, (~mask & val) | (mask & rval));
 517 }
 518
 519 static inline uint16_t
 520 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 521 {
 522     uint16_t val = pci_get_word(config);
 523     return (val & mask) >> (ffs(mask) - 1);
 524 }
 525
 526 static inline void
 527 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 528 {
 529     uint32_t val = pci_get_long(config);
 530     uint32_t rval = reg << (ffs(mask) - 1);
 531     pci_set_long(config, (~mask & val) | (mask & rval));
 532 }
 533
 534 static inline uint32_t
 535 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 536 {
 537     uint32_t val = pci_get_long(config);
 538     return (val & mask) >> (ffs(mask) - 1);
 539 }
 540
 541 static inline void
 542 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 543 {
 544     uint64_t val = pci_get_quad(config);
 545     uint64_t rval = reg << (ffs(mask) - 1);
 546     pci_set_quad(config, (~mask & val) | (mask & rval));
 547 }
 548
 549 static inline uint64_t
 550 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 551 {
 552     uint64_t val = pci_get_quad(config);
 553     return (val & mask) >> (ffs(mask) - 1);
 554 }
 555
 556 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 557                                     const char *name);
 558 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 559                                            bool multifunction,
 560                                            const char *name);
 561 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 562 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 563
 564 static inline int pci_is_express(const PCIDevice *d)
 565 {
 566     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 567 }
 568
 569 static inline uint32_t pci_config_size(const PCIDevice *d)
 570 {
 571     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 572 }
 573
 574 /* DMA access functions */
 575 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 576                              void *buf, dma_addr_t len, DMADirection dir)
 577 {
 578     cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
 579     return 0;
 580 }
 581
 582 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 583                                void *buf, dma_addr_t len)
 584 {
 585     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 586 }
 587
 588 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 589                                 const void *buf, dma_addr_t len)
 590 {
 591     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 592 }
 593
 594 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 595     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 596                                                    dma_addr_t addr)     \
 597     {                                                                   \
 598         return ld##_l##_phys(addr);                                     \
 599     }                                                                   \
 600     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 601                           dma_addr_t addr, uint##_bits##_t val)         \
 602     {                                                                   \
 603         st##_s##_phys(addr, val);                                       \
 604     }
 605
 606 PCI_DMA_DEFINE_LDST(ub, b, 8);
 607 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 608 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 609 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 610 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 611 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 612 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 613
 614 #undef PCI_DMA_DEFINE_LDST
 615
 616 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 617                                 dma_addr_t *plen, DMADirection dir)
 618 {
 619     target_phys_addr_t len = *plen;
 620     void *buf;
 621
 622     buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
 623     *plen = len;
 624     return buf;
 625 }
 626
 627 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 628                                  DMADirection dir, dma_addr_t access_len)
 629 {
 630     cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
 631                               access_len);
 632 }
 633
 634 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 635                                        int alloc_hint)
 636 {
 637     qemu_sglist_init(qsg, alloc_hint);
 638 }
 639
 640 extern const VMStateDescription vmstate_pci_device;
 641
 642 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 643     .name       = (stringify(_field)),                               \
 644     .size       = sizeof(PCIDevice),                                 \
 645     .vmsd       = &vmstate_pci_device,                               \
 646     .flags      = VMS_STRUCT,                                        \
 647     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 648 }
 649
 650 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 651     .name       = (stringify(_field)),                               \
 652     .size       = sizeof(PCIDevice),                                 \
 653     .vmsd       = &vmstate_pci_device,                               \
 654     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 655     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 656 }
 657
 658 #endif