4 #include "qemu-common.h"
8 /* PCI includes legacy ISA access. */
13 extern target_phys_addr_t pci_mem_base
;
15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
17 #define PCI_FUNC(devfn) ((devfn) & 0x07)
19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
22 /* QEMU-specific Vendor and Device ID definitions */
25 #define PCI_DEVICE_ID_IBM_440GX 0x027f
26 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
28 /* Hitachi (0x1054) */
29 #define PCI_VENDOR_ID_HITACHI 0x1054
30 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
33 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
37 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
39 /* Realtek (0x10ec) */
40 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
43 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
45 /* Marvell (0x11ab) */
46 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
48 /* QEMU/Bochs VGA (0x1234) */
49 #define PCI_VENDOR_ID_QEMU 0x1234
50 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
53 #define PCI_VENDOR_ID_VMWARE 0x15ad
54 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
55 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
56 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
57 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
58 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
61 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
62 #define PCI_DEVICE_ID_INTEL_82557 0x1229
64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
65 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
67 #define PCI_SUBDEVICE_ID_QEMU 0x1100
69 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
70 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
71 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
74 typedef uint64_t pcibus_t
;
75 #define FMT_PCIBUS PRIx64
77 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
78 uint32_t address
, uint32_t data
, int len
);
79 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
80 uint32_t address
, int len
);
81 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
82 pcibus_t addr
, pcibus_t size
, int type
);
83 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
85 typedef struct PCIIORegion
{
86 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
87 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
89 pcibus_t filtered_size
;
91 PCIMapIORegionFunc
*map_func
;
94 #define PCI_ROM_SLOT 6
95 #define PCI_NUM_REGIONS 7
97 /* Declarations from linux/pci_regs.h */
98 #define PCI_VENDOR_ID 0x00 /* 16 bits */
99 #define PCI_DEVICE_ID 0x02 /* 16 bits */
100 #define PCI_COMMAND 0x04 /* 16 bits */
101 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
102 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
103 #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */
104 #define PCI_STATUS 0x06 /* 16 bits */
105 #define PCI_REVISION_ID 0x08 /* 8 bits */
106 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
107 #define PCI_CLASS_DEVICE 0x0a /* Device class */
108 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
109 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
110 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
111 #define PCI_HEADER_TYPE_NORMAL 0
112 #define PCI_HEADER_TYPE_BRIDGE 1
113 #define PCI_HEADER_TYPE_CARDBUS 2
114 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
115 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
116 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
117 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
118 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
119 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
120 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
121 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
122 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
123 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
124 #define PCI_IO_LIMIT 0x1d
125 #define PCI_IO_RANGE_TYPE_32 0x01
126 #define PCI_IO_RANGE_MASK (~0x0fUL)
127 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
128 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
129 #define PCI_MEMORY_LIMIT 0x22
130 #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
131 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
132 #define PCI_PREF_MEMORY_LIMIT 0x26
133 #define PCI_PREF_RANGE_MASK (~0x0fUL)
134 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
135 #define PCI_PREF_LIMIT_UPPER32 0x2c
136 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
137 #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
138 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
139 #define PCI_ROM_ADDRESS_ENABLE 0x01
140 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
141 #define PCI_IO_LIMIT_UPPER16 0x32
142 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
143 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
144 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
145 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
146 #define PCI_MIN_GNT 0x3e /* 8 bits */
147 #define PCI_BRIDGE_CONTROL 0x3e
148 #define PCI_MAX_LAT 0x3f /* 8 bits */
150 /* Capability lists */
151 #define PCI_CAP_LIST_ID 0 /* Capability ID */
152 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
154 #define PCI_REVISION 0x08 /* obsolete, use PCI_REVISION_ID */
155 #define PCI_SUBVENDOR_ID 0x2c /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
156 #define PCI_SUBDEVICE_ID 0x2e /* obsolete, use PCI_SUBSYSTEM_ID */
158 /* Bits in the PCI Status Register (PCI 2.3 spec) */
159 #define PCI_STATUS_RESERVED1 0x007
160 #define PCI_STATUS_INT_STATUS 0x008
161 #define PCI_STATUS_CAP_LIST 0x010
162 #define PCI_STATUS_66MHZ 0x020
163 #define PCI_STATUS_RESERVED2 0x040
164 #define PCI_STATUS_FAST_BACK 0x080
165 #define PCI_STATUS_DEVSEL 0x600
167 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
168 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
169 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
171 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
173 /* Bits in the PCI Command Register (PCI 2.3 spec) */
174 #define PCI_COMMAND_RESERVED 0xf800
176 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
178 /* Size of the standard PCI config header */
179 #define PCI_CONFIG_HEADER_SIZE 0x40
180 /* Size of the standard PCI config space */
181 #define PCI_CONFIG_SPACE_SIZE 0x100
182 /* Size of the standart PCIe config space: 4KB */
183 #define PCIE_CONFIG_SPACE_SIZE 0x1000
185 #define PCI_NUM_PINS 4 /* A-D */
187 /* Bits in cap_present field. */
189 QEMU_PCI_CAP_MSIX
= 0x1,
190 QEMU_PCI_CAP_EXPRESS
= 0x2,
195 /* PCI config space */
198 /* Used to enable config checks on load. Note that writeable bits are
199 * never checked even if set in cmask. */
202 /* Used to implement R/W bytes */
205 /* Used to allocate config space for capabilities. */
208 /* the following fields are read only */
212 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
214 /* do not access the following fields */
215 PCIConfigReadFunc
*config_read
;
216 PCIConfigWriteFunc
*config_write
;
218 /* IRQ objects for the INTA-INTD pins. */
221 /* Current IRQ levels. Used internally by the generic PCI code. */
222 int irq_state
[PCI_NUM_PINS
];
224 /* Capability bits */
225 uint32_t cap_present
;
227 /* Offset of MSI-X capability in config space */
233 /* Space to store MSIX table */
234 uint8_t *msix_table_page
;
235 /* MMIO index used to map MSIX table and pending bit entries. */
237 /* Reference-count for entries actually in use by driver. */
238 unsigned *msix_entry_used
;
239 /* Region including the MSI-X table */
240 uint32_t msix_bar_size
;
241 /* Version id needed for VMState */
245 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
246 int instance_size
, int devfn
,
247 PCIConfigReadFunc
*config_read
,
248 PCIConfigWriteFunc
*config_write
);
250 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
251 pcibus_t size
, int type
,
252 PCIMapIORegionFunc
*map_func
);
254 int pci_add_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
256 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
258 void pci_reserve_capability(PCIDevice
*pci_dev
, uint8_t offset
, uint8_t size
);
260 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
263 uint32_t pci_default_read_config(PCIDevice
*d
,
264 uint32_t address
, int len
);
265 void pci_default_write_config(PCIDevice
*d
,
266 uint32_t address
, uint32_t val
, int len
);
267 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
268 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
270 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
271 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
272 typedef int (*pci_hotplug_fn
)(PCIDevice
*pci_dev
, int state
);
273 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
274 const char *name
, int devfn_min
);
275 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
);
276 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
277 void *irq_opaque
, int nirq
);
278 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
);
279 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
280 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
281 void *irq_opaque
, int devfn_min
, int nirq
);
283 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
284 const char *default_devaddr
);
285 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
286 const char *default_devaddr
);
287 int pci_bus_num(PCIBus
*s
);
288 void pci_for_each_device(PCIBus
*bus
, int bus_num
, void (*fn
)(PCIBus
*bus
, PCIDevice
*d
));
289 PCIBus
*pci_find_root_bus(int domain
);
290 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
);
291 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
);
292 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
);
294 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
297 void pci_info(Monitor
*mon
);
298 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
299 pci_map_irq_fn map_irq
, const char *name
);
302 pci_set_byte(uint8_t *config
, uint8_t val
)
307 static inline uint8_t
308 pci_get_byte(uint8_t *config
)
314 pci_set_word(uint8_t *config
, uint16_t val
)
316 cpu_to_le16wu((uint16_t *)config
, val
);
319 static inline uint16_t
320 pci_get_word(uint8_t *config
)
322 return le16_to_cpupu((uint16_t *)config
);
326 pci_set_long(uint8_t *config
, uint32_t val
)
328 cpu_to_le32wu((uint32_t *)config
, val
);
331 static inline uint32_t
332 pci_get_long(uint8_t *config
)
334 return le32_to_cpupu((uint32_t *)config
);
338 pci_set_quad(uint8_t *config
, uint64_t val
)
340 cpu_to_le64w((uint64_t *)config
, val
);
343 static inline uint64_t
344 pci_get_quad(uint8_t *config
)
346 return le64_to_cpup((uint64_t *)config
);
350 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
352 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
356 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
358 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
362 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
364 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
367 typedef int (*pci_qdev_initfn
)(PCIDevice
*dev
);
370 pci_qdev_initfn init
;
371 PCIUnregisterFunc
*exit
;
372 PCIConfigReadFunc
*config_read
;
373 PCIConfigWriteFunc
*config_write
;
375 /* pci config header type */
379 int is_express
; /* is this device pci express? */
382 void pci_qdev_register(PCIDeviceInfo
*info
);
383 void pci_qdev_register_many(PCIDeviceInfo
*info
);
385 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
386 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
388 static inline int pci_is_express(PCIDevice
*d
)
390 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
393 static inline uint32_t pci_config_size(PCIDevice
*d
)
395 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;
398 /* These are not pci specific. Should move into a separate header.
399 * Only pci.c uses them, so keep them here for now.
402 /* Get last byte of a range from offset + length.
403 * Undefined for ranges that wrap around 0. */
404 static inline uint64_t range_get_last(uint64_t offset
, uint64_t len
)
406 return offset
+ len
- 1;
409 /* Check whether a given range covers a given byte. */
410 static inline int range_covers_byte(uint64_t offset
, uint64_t len
,
413 return offset
<= byte
&& byte
<= range_get_last(offset
, len
);
416 /* Check whether 2 given ranges overlap.
417 * Undefined if ranges that wrap around 0. */
418 static inline int ranges_overlap(uint64_t first1
, uint64_t len1
,
419 uint64_t first2
, uint64_t len2
)
421 uint64_t last1
= range_get_last(first1
, len1
);
422 uint64_t last2
= range_get_last(first2
, len2
);
424 return !(last2
< first1
|| last1
< first2
);