hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "isa.h"
  10
  11 /* PCI bus */
  12
  13 extern target_phys_addr_t pci_mem_base;
  14
  15 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  16 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  17 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  18
  19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20 #include "pci_ids.h"
  21
  22 /* QEMU-specific Vendor and Device ID definitions */
  23
  24 /* IBM (0x1014) */
  25 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  26 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28 /* Hitachi (0x1054) */
  29 #define PCI_VENDOR_ID_HITACHI            0x1054
  30 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32 /* Apple (0x106b) */
  33 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39 /* Realtek (0x10ec) */
  40 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42 /* Xilinx (0x10ee) */
  43 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45 /* Marvell (0x11ab) */
  46 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48 /* QEMU/Bochs VGA (0x1234) */
  49 #define PCI_VENDOR_ID_QEMU               0x1234
  50 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52 /* VMWare (0x15ad) */
  53 #define PCI_VENDOR_ID_VMWARE             0x15ad
  54 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60 /* Intel (0x8086) */
  61 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74 typedef uint64_t pcibus_t;
  75 #define FMT_PCIBUS                      PRIx64
  76
  77 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  78                                 uint32_t address, uint32_t data, int len);
  79 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  80                                    uint32_t address, int len);
  81 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  82                                 pcibus_t addr, pcibus_t size, int type);
  83 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  84
  85 typedef struct PCIIORegion {
  86     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  87 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  88     pcibus_t size;
  89     pcibus_t filtered_size;
  90     uint8_t type;
  91     PCIMapIORegionFunc *map_func;
  92 } PCIIORegion;
  93
  94 #define PCI_ROM_SLOT 6
  95 #define PCI_NUM_REGIONS 7
  96
  97 /* Declarations from linux/pci_regs.h */
  98 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  99 #define PCI_DEVICE_ID           0x02    /* 16 bits */
 100 #define PCI_COMMAND             0x04    /* 16 bits */
 101 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
 102 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
 103 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus master */
 104 #define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
 105 #define PCI_STATUS              0x06    /* 16 bits */
 106 #define  PCI_STATUS_INTERRUPT   0x08
 107 #define PCI_REVISION_ID         0x08    /* 8 bits  */
 108 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
 109 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
 110 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
 111 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
 112 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
 113 #define  PCI_HEADER_TYPE_NORMAL         0
 114 #define  PCI_HEADER_TYPE_BRIDGE         1
 115 #define  PCI_HEADER_TYPE_CARDBUS        2
 116 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 117 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
 118 #define  PCI_BASE_ADDRESS_SPACE_IO      0x01
 119 #define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
 120 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 121 #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
 122 #define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 123 #define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 124 #define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
 125 #define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
 126 #define PCI_IO_LIMIT            0x1d
 127 #define  PCI_IO_RANGE_TYPE_32   0x01
 128 #define  PCI_IO_RANGE_MASK      (~0x0fUL)
 129 #define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 130 #define PCI_MEMORY_BASE         0x20    /* Memory range behind */
 131 #define PCI_MEMORY_LIMIT        0x22
 132 #define  PCI_MEMORY_RANGE_MASK  (~0x0fUL)
 133 #define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
 134 #define PCI_PREF_MEMORY_LIMIT   0x26
 135 #define  PCI_PREF_RANGE_MASK    (~0x0fUL)
 136 #define  PCI_PREF_RANGE_TYPE_64 0x01
 137 #define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
 138 #define PCI_PREF_LIMIT_UPPER32  0x2c
 139 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */
 140 #define PCI_SUBSYSTEM_ID        0x2e    /* 16 bits */
 141 #define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
 142 #define  PCI_ROM_ADDRESS_ENABLE 0x01
 143 #define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
 144 #define PCI_IO_LIMIT_UPPER16    0x32
 145 #define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 146 #define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 147 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 148 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 149 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 150 #define PCI_BRIDGE_CONTROL      0x3e
 151 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 152
 153 /* Capability lists */
 154 #define PCI_CAP_LIST_ID         0       /* Capability ID */
 155 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 156
 157 #define PCI_REVISION            0x08    /* obsolete, use PCI_REVISION_ID */
 158 #define PCI_SUBVENDOR_ID        0x2c    /* obsolete, use PCI_SUBSYSTEM_VENDOR_ID */
 159 #define PCI_SUBDEVICE_ID        0x2e    /* obsolete, use PCI_SUBSYSTEM_ID */
 160
 161 /* Bits in the PCI Status Register (PCI 2.3 spec) */
 162 #define PCI_STATUS_RESERVED1    0x007
 163 #define PCI_STATUS_INT_STATUS   0x008
 164 #define PCI_STATUS_CAP_LIST     0x010
 165 #define PCI_STATUS_66MHZ        0x020
 166 #define PCI_STATUS_RESERVED2    0x040
 167 #define PCI_STATUS_FAST_BACK    0x080
 168 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
 169 #define PCI_STATUS_DEVSEL       0x600
 170
 171 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 172                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 173                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 174
 175 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 176
 177 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 178 #define PCI_COMMAND_RESERVED    0xf800
 179
 180 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 181
 182 /* Size of the standard PCI config header */
 183 #define PCI_CONFIG_HEADER_SIZE 0x40
 184 /* Size of the standard PCI config space */
 185 #define PCI_CONFIG_SPACE_SIZE 0x100
 186 /* Size of the standart PCIe config space: 4KB */
 187 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 188
 189 #define PCI_NUM_PINS 4 /* A-D */
 190
 191 /* Bits in cap_present field. */
 192 enum {
 193     QEMU_PCI_CAP_MSIX = 0x1,
 194     QEMU_PCI_CAP_EXPRESS = 0x2,
 195 };
 196
 197 struct PCIDevice {
 198     DeviceState qdev;
 199     /* PCI config space */
 200     uint8_t *config;
 201
 202     /* Used to enable config checks on load. Note that writeable bits are
 203      * never checked even if set in cmask. */
 204     uint8_t *cmask;
 205
 206     /* Used to implement R/W bytes */
 207     uint8_t *wmask;
 208
 209     /* Used to allocate config space for capabilities. */
 210     uint8_t *used;
 211
 212     /* the following fields are read only */
 213     PCIBus *bus;
 214     uint32_t devfn;
 215     char name[64];
 216     PCIIORegion io_regions[PCI_NUM_REGIONS];
 217
 218     /* do not access the following fields */
 219     PCIConfigReadFunc *config_read;
 220     PCIConfigWriteFunc *config_write;
 221
 222     /* IRQ objects for the INTA-INTD pins.  */
 223     qemu_irq *irq;
 224
 225     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 226     uint8_t irq_state;
 227
 228     /* Capability bits */
 229     uint32_t cap_present;
 230
 231     /* Offset of MSI-X capability in config space */
 232     uint8_t msix_cap;
 233
 234     /* MSI-X entries */
 235     int msix_entries_nr;
 236
 237     /* Space to store MSIX table */
 238     uint8_t *msix_table_page;
 239     /* MMIO index used to map MSIX table and pending bit entries. */
 240     int msix_mmio_index;
 241     /* Reference-count for entries actually in use by driver. */
 242     unsigned *msix_entry_used;
 243     /* Region including the MSI-X table */
 244     uint32_t msix_bar_size;
 245     /* Version id needed for VMState */
 246     int32_t version_id;
 247
 248     /* Location of option rom */
 249     char *romfile;
 250     ram_addr_t rom_offset;
 251 };
 252
 253 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 254                                int instance_size, int devfn,
 255                                PCIConfigReadFunc *config_read,
 256                                PCIConfigWriteFunc *config_write);
 257
 258 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 259                             pcibus_t size, int type,
 260                             PCIMapIORegionFunc *map_func);
 261
 262 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 263
 264 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 265
 266 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 267
 268 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 269
 270
 271 uint32_t pci_default_read_config(PCIDevice *d,
 272                                  uint32_t address, int len);
 273 void pci_default_write_config(PCIDevice *d,
 274                               uint32_t address, uint32_t val, int len);
 275 void pci_device_save(PCIDevice *s, QEMUFile *f);
 276 int pci_device_load(PCIDevice *s, QEMUFile *f);
 277
 278 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 279 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 280 typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state);
 281 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 282                          const char *name, int devfn_min);
 283 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 284 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 285                   void *irq_opaque, int nirq);
 286 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
 287 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 288                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 289                          void *irq_opaque, int devfn_min, int nirq);
 290
 291 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 292                         const char *default_devaddr);
 293 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 294                                const char *default_devaddr);
 295 int pci_bus_num(PCIBus *s);
 296 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 297 PCIBus *pci_find_root_bus(int domain);
 298 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 299 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 300 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 301
 302 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 303                      unsigned *slotp);
 304
 305 void pci_info(Monitor *mon);
 306 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 307                         pci_map_irq_fn map_irq, const char *name);
 308 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 309
 310 static inline void
 311 pci_set_byte(uint8_t *config, uint8_t val)
 312 {
 313     *config = val;
 314 }
 315
 316 static inline uint8_t
 317 pci_get_byte(uint8_t *config)
 318 {
 319     return *config;
 320 }
 321
 322 static inline void
 323 pci_set_word(uint8_t *config, uint16_t val)
 324 {
 325     cpu_to_le16wu((uint16_t *)config, val);
 326 }
 327
 328 static inline uint16_t
 329 pci_get_word(uint8_t *config)
 330 {
 331     return le16_to_cpupu((uint16_t *)config);
 332 }
 333
 334 static inline void
 335 pci_set_long(uint8_t *config, uint32_t val)
 336 {
 337     cpu_to_le32wu((uint32_t *)config, val);
 338 }
 339
 340 static inline uint32_t
 341 pci_get_long(uint8_t *config)
 342 {
 343     return le32_to_cpupu((uint32_t *)config);
 344 }
 345
 346 static inline void
 347 pci_set_quad(uint8_t *config, uint64_t val)
 348 {
 349     cpu_to_le64w((uint64_t *)config, val);
 350 }
 351
 352 static inline uint64_t
 353 pci_get_quad(uint8_t *config)
 354 {
 355     return le64_to_cpup((uint64_t *)config);
 356 }
 357
 358 static inline void
 359 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 360 {
 361     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 362 }
 363
 364 static inline void
 365 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 366 {
 367     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 368 }
 369
 370 static inline void
 371 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 372 {
 373     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 374 }
 375
 376 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 377 typedef struct {
 378     DeviceInfo qdev;
 379     pci_qdev_initfn init;
 380     PCIUnregisterFunc *exit;
 381     PCIConfigReadFunc *config_read;
 382     PCIConfigWriteFunc *config_write;
 383
 384     /* pci config header type */
 385     uint8_t header_type;
 386
 387     /* pcie stuff */
 388     int is_express;   /* is this device pci express? */
 389
 390     /* rom bar */
 391     const char *romfile;
 392 } PCIDeviceInfo;
 393
 394 void pci_qdev_register(PCIDeviceInfo *info);
 395 void pci_qdev_register_many(PCIDeviceInfo *info);
 396
 397 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 398 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 399
 400 static inline int pci_is_express(PCIDevice *d)
 401 {
 402     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 403 }
 404
 405 static inline uint32_t pci_config_size(PCIDevice *d)
 406 {
 407     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 408 }
 409
 410 /* These are not pci specific. Should move into a separate header.
 411  * Only pci.c uses them, so keep them here for now.
 412  */
 413
 414 /* Get last byte of a range from offset + length.
 415  * Undefined for ranges that wrap around 0. */
 416 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 417 {
 418     return offset + len - 1;
 419 }
 420
 421 /* Check whether a given range covers a given byte. */
 422 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 423                                     uint64_t byte)
 424 {
 425     return offset <= byte && byte <= range_get_last(offset, len);
 426 }
 427
 428 /* Check whether 2 given ranges overlap.
 429  * Undefined if ranges that wrap around 0. */
 430 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 431                                  uint64_t first2, uint64_t len2)
 432 {
 433     uint64_t last1 = range_get_last(first1, len1);
 434     uint64_t last2 = range_get_last(first2, len2);
 435
 436     return !(last2 < first1 || last1 < first2);
 437 }
 438
 439 #endif