hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 #include "pcie.h"
  13
  14 /* PCI bus */
  15
  16 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  17 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  18 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  19 #define PCI_SLOT_MAX            32
  20 #define PCI_FUNC_MAX            8
  21
  22 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  23 #include "pci_ids.h"
  24
  25 /* QEMU-specific Vendor and Device ID definitions */
  26
  27 /* IBM (0x1014) */
  28 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  29 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  30
  31 /* Hitachi (0x1054) */
  32 #define PCI_VENDOR_ID_HITACHI            0x1054
  33 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  34
  35 /* Apple (0x106b) */
  36 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  37 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  40 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  41
  42 /* Realtek (0x10ec) */
  43 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  44
  45 /* Xilinx (0x10ee) */
  46 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  47
  48 /* Marvell (0x11ab) */
  49 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  50
  51 /* QEMU/Bochs VGA (0x1234) */
  52 #define PCI_VENDOR_ID_QEMU               0x1234
  53 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  54
  55 /* VMWare (0x15ad) */
  56 #define PCI_VENDOR_ID_VMWARE             0x15ad
  57 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  58 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  59 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  60 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  61 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  62
  63 /* Intel (0x8086) */
  64 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  65 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  66 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  67
  68 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  69 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  70 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  71 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  72
  73 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  74 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  75 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  76 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  77
  78 #define FMT_PCIBUS                      PRIx64
  79
  80 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  81                                 uint32_t address, uint32_t data, int len);
  82 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  83                                    uint32_t address, int len);
  84 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  85                                 pcibus_t addr, pcibus_t size, int type);
  86 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  87
  88 typedef struct PCIIORegion {
  89     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  90 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  91     pcibus_t size;
  92     pcibus_t filtered_size;
  93     uint8_t type;
  94     PCIMapIORegionFunc *map_func;
  95 } PCIIORegion;
  96
  97 #define PCI_ROM_SLOT 6
  98 #define PCI_NUM_REGIONS 7
  99
 100 #include "pci_regs.h"
 101
 102 /* PCI HEADER_TYPE */
 103 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 104
 105 /* Size of the standard PCI config header */
 106 #define PCI_CONFIG_HEADER_SIZE 0x40
 107 /* Size of the standard PCI config space */
 108 #define PCI_CONFIG_SPACE_SIZE 0x100
 109 /* Size of the standart PCIe config space: 4KB */
 110 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 111
 112 #define PCI_NUM_PINS 4 /* A-D */
 113
 114 /* Bits in cap_present field. */
 115 enum {
 116     QEMU_PCI_CAP_MSI = 0x1,
 117     QEMU_PCI_CAP_MSIX = 0x2,
 118     QEMU_PCI_CAP_EXPRESS = 0x4,
 119
 120     /* multifunction capable device */
 121 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 122     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 123
 124     /* command register SERR bit enabled */
 125 #define QEMU_PCI_CAP_SERR_BITNR 4
 126     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 127 };
 128
 129 struct PCIDevice {
 130     DeviceState qdev;
 131     /* PCI config space */
 132     uint8_t *config;
 133
 134     /* Used to enable config checks on load. Note that writeable bits are
 135      * never checked even if set in cmask. */
 136     uint8_t *cmask;
 137
 138     /* Used to implement R/W bytes */
 139     uint8_t *wmask;
 140
 141     /* Used to implement RW1C(Write 1 to Clear) bytes */
 142     uint8_t *w1cmask;
 143
 144     /* Used to allocate config space for capabilities. */
 145     uint8_t *used;
 146
 147     /* the following fields are read only */
 148     PCIBus *bus;
 149     uint32_t devfn;
 150     char name[64];
 151     PCIIORegion io_regions[PCI_NUM_REGIONS];
 152
 153     /* do not access the following fields */
 154     PCIConfigReadFunc *config_read;
 155     PCIConfigWriteFunc *config_write;
 156
 157     /* IRQ objects for the INTA-INTD pins.  */
 158     qemu_irq *irq;
 159
 160     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 161     uint8_t irq_state;
 162
 163     /* Capability bits */
 164     uint32_t cap_present;
 165
 166     /* Offset of MSI-X capability in config space */
 167     uint8_t msix_cap;
 168
 169     /* MSI-X entries */
 170     int msix_entries_nr;
 171
 172     /* Space to store MSIX table */
 173     uint8_t *msix_table_page;
 174     /* MMIO index used to map MSIX table and pending bit entries. */
 175     int msix_mmio_index;
 176     /* Reference-count for entries actually in use by driver. */
 177     unsigned *msix_entry_used;
 178     /* Region including the MSI-X table */
 179     uint32_t msix_bar_size;
 180     /* Version id needed for VMState */
 181     int32_t version_id;
 182
 183     /* Offset of MSI capability in config space */
 184     uint8_t msi_cap;
 185
 186     /* PCI Express */
 187     PCIExpressDevice exp;
 188
 189     /* Location of option rom */
 190     char *romfile;
 191     ram_addr_t rom_offset;
 192     uint32_t rom_bar;
 193 };
 194
 195 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 196                                int instance_size, int devfn,
 197                                PCIConfigReadFunc *config_read,
 198                                PCIConfigWriteFunc *config_write);
 199
 200 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 201                             pcibus_t size, uint8_t type,
 202                             PCIMapIORegionFunc *map_func);
 203
 204 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 205                        uint8_t offset, uint8_t size);
 206
 207 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 208
 209 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 210
 211 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 212
 213
 214 uint32_t pci_default_read_config(PCIDevice *d,
 215                                  uint32_t address, int len);
 216 void pci_default_write_config(PCIDevice *d,
 217                               uint32_t address, uint32_t val, int len);
 218 void pci_device_save(PCIDevice *s, QEMUFile *f);
 219 int pci_device_load(PCIDevice *s, QEMUFile *f);
 220
 221 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 222 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 223
 224 typedef enum {
 225     PCI_HOTPLUG_DISABLED,
 226     PCI_HOTPLUG_ENABLED,
 227     PCI_COLDPLUG_ENABLED,
 228 } PCIHotplugState;
 229
 230 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 231                               PCIHotplugState state);
 232 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 233                          const char *name, uint8_t devfn_min);
 234 PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min);
 235 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 236                   void *irq_opaque, int nirq);
 237 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 238 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 239 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 240                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 241                          void *irq_opaque, uint8_t devfn_min, int nirq);
 242 void pci_device_reset(PCIDevice *dev);
 243 void pci_bus_reset(PCIBus *bus);
 244
 245 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 246
 247 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 248                         const char *default_devaddr);
 249 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 250                                const char *default_devaddr);
 251 int pci_bus_num(PCIBus *s);
 252 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 253 PCIBus *pci_find_root_bus(int domain);
 254 int pci_find_domain(const PCIBus *bus);
 255 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 256 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 257 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 258 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 259
 260 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 261                       unsigned int *slotp, unsigned int *funcp);
 262 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 263                      unsigned *slotp);
 264
 265 void do_pci_info_print(Monitor *mon, const QObject *data);
 266 void do_pci_info(Monitor *mon, QObject **ret_data);
 267 void pci_bridge_update_mappings(PCIBus *b);
 268
 269 void pci_device_deassert_intx(PCIDevice *dev);
 270
 271 static inline void
 272 pci_set_byte(uint8_t *config, uint8_t val)
 273 {
 274     *config = val;
 275 }
 276
 277 static inline uint8_t
 278 pci_get_byte(const uint8_t *config)
 279 {
 280     return *config;
 281 }
 282
 283 static inline void
 284 pci_set_word(uint8_t *config, uint16_t val)
 285 {
 286     cpu_to_le16wu((uint16_t *)config, val);
 287 }
 288
 289 static inline uint16_t
 290 pci_get_word(const uint8_t *config)
 291 {
 292     return le16_to_cpupu((const uint16_t *)config);
 293 }
 294
 295 static inline void
 296 pci_set_long(uint8_t *config, uint32_t val)
 297 {
 298     cpu_to_le32wu((uint32_t *)config, val);
 299 }
 300
 301 static inline uint32_t
 302 pci_get_long(const uint8_t *config)
 303 {
 304     return le32_to_cpupu((const uint32_t *)config);
 305 }
 306
 307 static inline void
 308 pci_set_quad(uint8_t *config, uint64_t val)
 309 {
 310     cpu_to_le64w((uint64_t *)config, val);
 311 }
 312
 313 static inline uint64_t
 314 pci_get_quad(const uint8_t *config)
 315 {
 316     return le64_to_cpup((const uint64_t *)config);
 317 }
 318
 319 static inline void
 320 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 321 {
 322     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 323 }
 324
 325 static inline void
 326 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 327 {
 328     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 329 }
 330
 331 static inline void
 332 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 333 {
 334     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 335 }
 336
 337 static inline void
 338 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 339 {
 340     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 341 }
 342
 343 static inline void
 344 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 345 {
 346     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 347 }
 348
 349 static inline void
 350 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 351 {
 352     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 353 }
 354
 355 /*
 356  * helper functions to do bit mask operation on configuration space.
 357  * Just to set bit, use test-and-set and discard returned value.
 358  * Just to clear bit, use test-and-clear and discard returned value.
 359  * NOTE: They aren't atomic.
 360  */
 361 static inline uint8_t
 362 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 363 {
 364     uint8_t val = pci_get_byte(config);
 365     pci_set_byte(config, val & ~mask);
 366     return val & mask;
 367 }
 368
 369 static inline uint8_t
 370 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 371 {
 372     uint8_t val = pci_get_byte(config);
 373     pci_set_byte(config, val | mask);
 374     return val & mask;
 375 }
 376
 377 static inline uint16_t
 378 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 379 {
 380     uint16_t val = pci_get_word(config);
 381     pci_set_word(config, val & ~mask);
 382     return val & mask;
 383 }
 384
 385 static inline uint16_t
 386 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 387 {
 388     uint16_t val = pci_get_word(config);
 389     pci_set_word(config, val | mask);
 390     return val & mask;
 391 }
 392
 393 static inline uint32_t
 394 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 395 {
 396     uint32_t val = pci_get_long(config);
 397     pci_set_long(config, val & ~mask);
 398     return val & mask;
 399 }
 400
 401 static inline uint32_t
 402 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 403 {
 404     uint32_t val = pci_get_long(config);
 405     pci_set_long(config, val | mask);
 406     return val & mask;
 407 }
 408
 409 static inline uint64_t
 410 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 411 {
 412     uint64_t val = pci_get_quad(config);
 413     pci_set_quad(config, val & ~mask);
 414     return val & mask;
 415 }
 416
 417 static inline uint64_t
 418 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 419 {
 420     uint64_t val = pci_get_quad(config);
 421     pci_set_quad(config, val | mask);
 422     return val & mask;
 423 }
 424
 425 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 426 typedef struct {
 427     DeviceInfo qdev;
 428     pci_qdev_initfn init;
 429     PCIUnregisterFunc *exit;
 430     PCIConfigReadFunc *config_read;
 431     PCIConfigWriteFunc *config_write;
 432
 433     /*
 434      * pci-to-pci bridge or normal device.
 435      * This doesn't mean pci host switch.
 436      * When card bus bridge is supported, this would be enhanced.
 437      */
 438     int is_bridge;
 439
 440     /* pcie stuff */
 441     int is_express;   /* is this device pci express? */
 442
 443     /* device isn't hot-pluggable */
 444     int no_hotplug;
 445
 446     /* rom bar */
 447     const char *romfile;
 448 } PCIDeviceInfo;
 449
 450 void pci_qdev_register(PCIDeviceInfo *info);
 451 void pci_qdev_register_many(PCIDeviceInfo *info);
 452
 453 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 454                                     const char *name);
 455 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 456                                            bool multifunction,
 457                                            const char *name);
 458 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
 459                                         bool multifunction,
 460                                         const char *name);
 461 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 462 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 463 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name);
 464
 465 static inline int pci_is_express(const PCIDevice *d)
 466 {
 467     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 468 }
 469
 470 static inline uint32_t pci_config_size(const PCIDevice *d)
 471 {
 472     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 473 }
 474
 475 #endif