hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5 #include "qobject.h"
   6
   7 #include "qdev.h"
   8
   9 /* PCI includes legacy ISA access.  */
  10 #include "isa.h"
  11
  12 /* PCI bus */
  13
  14 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  16 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  17 #define PCI_FUNC_MAX            8
  18
  19 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  20 #include "pci_ids.h"
  21
  22 /* QEMU-specific Vendor and Device ID definitions */
  23
  24 /* IBM (0x1014) */
  25 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  26 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  27
  28 /* Hitachi (0x1054) */
  29 #define PCI_VENDOR_ID_HITACHI            0x1054
  30 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  31
  32 /* Apple (0x106b) */
  33 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  35 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  36 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  37 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  38
  39 /* Realtek (0x10ec) */
  40 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  41
  42 /* Xilinx (0x10ee) */
  43 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  44
  45 /* Marvell (0x11ab) */
  46 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  47
  48 /* QEMU/Bochs VGA (0x1234) */
  49 #define PCI_VENDOR_ID_QEMU               0x1234
  50 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  51
  52 /* VMWare (0x15ad) */
  53 #define PCI_VENDOR_ID_VMWARE             0x15ad
  54 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  55 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  56 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  57 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  58 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  59
  60 /* Intel (0x8086) */
  61 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  62 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  63
  64 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  65 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  66 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  67 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  68
  69 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  70 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  71 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  72 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  73
  74 #define FMT_PCIBUS                      PRIx64
  75
  76 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  77                                 uint32_t address, uint32_t data, int len);
  78 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  79                                    uint32_t address, int len);
  80 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  81                                 pcibus_t addr, pcibus_t size, int type);
  82 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  83
  84 typedef struct PCIIORegion {
  85     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  86 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  87     pcibus_t size;
  88     pcibus_t filtered_size;
  89     uint8_t type;
  90     PCIMapIORegionFunc *map_func;
  91 } PCIIORegion;
  92
  93 #define PCI_ROM_SLOT 6
  94 #define PCI_NUM_REGIONS 7
  95
  96 #include "pci_regs.h"
  97
  98 /* PCI HEADER_TYPE */
  99 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 100
 101 /* Size of the standard PCI config header */
 102 #define PCI_CONFIG_HEADER_SIZE 0x40
 103 /* Size of the standard PCI config space */
 104 #define PCI_CONFIG_SPACE_SIZE 0x100
 105 /* Size of the standart PCIe config space: 4KB */
 106 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 107
 108 #define PCI_NUM_PINS 4 /* A-D */
 109
 110 /* Bits in cap_present field. */
 111 enum {
 112     QEMU_PCI_CAP_MSI = 0x1,
 113     QEMU_PCI_CAP_MSIX = 0x2,
 114     QEMU_PCI_CAP_EXPRESS = 0x4,
 115
 116     /* multifunction capable device */
 117 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 118     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 119 };
 120
 121 struct PCIDevice {
 122     DeviceState qdev;
 123     /* PCI config space */
 124     uint8_t *config;
 125
 126     /* Used to enable config checks on load. Note that writeable bits are
 127      * never checked even if set in cmask. */
 128     uint8_t *cmask;
 129
 130     /* Used to implement R/W bytes */
 131     uint8_t *wmask;
 132
 133     /* Used to implement RW1C(Write 1 to Clear) bytes */
 134     uint8_t *w1cmask;
 135
 136     /* Used to allocate config space for capabilities. */
 137     uint8_t *used;
 138
 139     /* the following fields are read only */
 140     PCIBus *bus;
 141     uint32_t devfn;
 142     char name[64];
 143     PCIIORegion io_regions[PCI_NUM_REGIONS];
 144
 145     /* do not access the following fields */
 146     PCIConfigReadFunc *config_read;
 147     PCIConfigWriteFunc *config_write;
 148
 149     /* IRQ objects for the INTA-INTD pins.  */
 150     qemu_irq *irq;
 151
 152     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 153     uint8_t irq_state;
 154
 155     /* Capability bits */
 156     uint32_t cap_present;
 157
 158     /* Offset of MSI-X capability in config space */
 159     uint8_t msix_cap;
 160
 161     /* MSI-X entries */
 162     int msix_entries_nr;
 163
 164     /* Space to store MSIX table */
 165     uint8_t *msix_table_page;
 166     /* MMIO index used to map MSIX table and pending bit entries. */
 167     int msix_mmio_index;
 168     /* Reference-count for entries actually in use by driver. */
 169     unsigned *msix_entry_used;
 170     /* Region including the MSI-X table */
 171     uint32_t msix_bar_size;
 172     /* Version id needed for VMState */
 173     int32_t version_id;
 174
 175     /* Offset of MSI capability in config space */
 176     uint8_t msi_cap;
 177
 178     /* Location of option rom */
 179     char *romfile;
 180     ram_addr_t rom_offset;
 181     uint32_t rom_bar;
 182 };
 183
 184 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 185                                int instance_size, int devfn,
 186                                PCIConfigReadFunc *config_read,
 187                                PCIConfigWriteFunc *config_write);
 188
 189 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 190                             pcibus_t size, uint8_t type,
 191                             PCIMapIORegionFunc *map_func);
 192
 193 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 194                        uint8_t offset, uint8_t size);
 195
 196 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 197
 198 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 199
 200 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 201
 202
 203 uint32_t pci_default_read_config(PCIDevice *d,
 204                                  uint32_t address, int len);
 205 void pci_default_write_config(PCIDevice *d,
 206                               uint32_t address, uint32_t val, int len);
 207 void pci_device_save(PCIDevice *s, QEMUFile *f);
 208 int pci_device_load(PCIDevice *s, QEMUFile *f);
 209
 210 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 211 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 212 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
 213 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 214                          const char *name, int devfn_min);
 215 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 216 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 217                   void *irq_opaque, int nirq);
 218 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 219 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 220                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 221                          void *irq_opaque, int devfn_min, int nirq);
 222
 223 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 224
 225 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 226                         const char *default_devaddr);
 227 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 228                                const char *default_devaddr);
 229 int pci_bus_num(PCIBus *s);
 230 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 231 PCIBus *pci_find_root_bus(int domain);
 232 int pci_find_domain(const PCIBus *bus);
 233 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 234 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 235 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 236
 237 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 238                       unsigned int *slotp, unsigned int *funcp);
 239 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 240                      unsigned *slotp);
 241
 242 void do_pci_info_print(Monitor *mon, const QObject *data);
 243 void do_pci_info(Monitor *mon, QObject **ret_data);
 244 void pci_bridge_update_mappings(PCIBus *b);
 245
 246 bool pci_msi_enabled(PCIDevice *dev);
 247 void pci_msi_notify(PCIDevice *dev, unsigned int vector);
 248
 249 static inline void
 250 pci_set_byte(uint8_t *config, uint8_t val)
 251 {
 252     *config = val;
 253 }
 254
 255 static inline uint8_t
 256 pci_get_byte(const uint8_t *config)
 257 {
 258     return *config;
 259 }
 260
 261 static inline void
 262 pci_set_word(uint8_t *config, uint16_t val)
 263 {
 264     cpu_to_le16wu((uint16_t *)config, val);
 265 }
 266
 267 static inline uint16_t
 268 pci_get_word(const uint8_t *config)
 269 {
 270     return le16_to_cpupu((const uint16_t *)config);
 271 }
 272
 273 static inline void
 274 pci_set_long(uint8_t *config, uint32_t val)
 275 {
 276     cpu_to_le32wu((uint32_t *)config, val);
 277 }
 278
 279 static inline uint32_t
 280 pci_get_long(const uint8_t *config)
 281 {
 282     return le32_to_cpupu((const uint32_t *)config);
 283 }
 284
 285 static inline void
 286 pci_set_quad(uint8_t *config, uint64_t val)
 287 {
 288     cpu_to_le64w((uint64_t *)config, val);
 289 }
 290
 291 static inline uint64_t
 292 pci_get_quad(const uint8_t *config)
 293 {
 294     return le64_to_cpup((const uint64_t *)config);
 295 }
 296
 297 static inline void
 298 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 299 {
 300     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 301 }
 302
 303 static inline void
 304 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 305 {
 306     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 307 }
 308
 309 static inline void
 310 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 311 {
 312     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 313 }
 314
 315 static inline void
 316 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 317 {
 318     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 319 }
 320
 321 static inline void
 322 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 323 {
 324     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 325 }
 326
 327 static inline void
 328 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 329 {
 330     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 331 }
 332
 333 /*
 334  * helper functions to do bit mask operation on configuration space.
 335  * Just to set bit, use test-and-set and discard returned value.
 336  * Just to clear bit, use test-and-clear and discard returned value.
 337  * NOTE: They aren't atomic.
 338  */
 339 static inline uint8_t
 340 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 341 {
 342     uint8_t val = pci_get_byte(config);
 343     pci_set_byte(config, val & ~mask);
 344     return val & mask;
 345 }
 346
 347 static inline uint8_t
 348 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 349 {
 350     uint8_t val = pci_get_byte(config);
 351     pci_set_byte(config, val | mask);
 352     return val & mask;
 353 }
 354
 355 static inline uint16_t
 356 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 357 {
 358     uint16_t val = pci_get_word(config);
 359     pci_set_word(config, val & ~mask);
 360     return val & mask;
 361 }
 362
 363 static inline uint16_t
 364 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 365 {
 366     uint16_t val = pci_get_word(config);
 367     pci_set_word(config, val | mask);
 368     return val & mask;
 369 }
 370
 371 static inline uint32_t
 372 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 373 {
 374     uint32_t val = pci_get_long(config);
 375     pci_set_long(config, val & ~mask);
 376     return val & mask;
 377 }
 378
 379 static inline uint32_t
 380 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 381 {
 382     uint32_t val = pci_get_long(config);
 383     pci_set_long(config, val | mask);
 384     return val & mask;
 385 }
 386
 387 static inline uint64_t
 388 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 389 {
 390     uint64_t val = pci_get_quad(config);
 391     pci_set_quad(config, val & ~mask);
 392     return val & mask;
 393 }
 394
 395 static inline uint64_t
 396 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 397 {
 398     uint64_t val = pci_get_quad(config);
 399     pci_set_quad(config, val | mask);
 400     return val & mask;
 401 }
 402
 403 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 404 typedef struct {
 405     DeviceInfo qdev;
 406     pci_qdev_initfn init;
 407     PCIUnregisterFunc *exit;
 408     PCIConfigReadFunc *config_read;
 409     PCIConfigWriteFunc *config_write;
 410
 411     /*
 412      * pci-to-pci bridge or normal device.
 413      * This doesn't mean pci host switch.
 414      * When card bus bridge is supported, this would be enhanced.
 415      */
 416     int is_bridge;
 417
 418     /* pcie stuff */
 419     int is_express;   /* is this device pci express? */
 420
 421     /* rom bar */
 422     const char *romfile;
 423 } PCIDeviceInfo;
 424
 425 void pci_qdev_register(PCIDeviceInfo *info);
 426 void pci_qdev_register_many(PCIDeviceInfo *info);
 427
 428 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 429                                     const char *name);
 430 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 431                                            bool multifunction,
 432                                            const char *name);
 433 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 434 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 435
 436 static inline int pci_is_express(const PCIDevice *d)
 437 {
 438     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 439 }
 440
 441 static inline uint32_t pci_config_size(const PCIDevice *d)
 442 {
 443     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 444 }
 445
 446 /* These are not pci specific. Should move into a separate header.
 447  * Only pci.c uses them, so keep them here for now.
 448  */
 449
 450 /* Get last byte of a range from offset + length.
 451  * Undefined for ranges that wrap around 0. */
 452 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 453 {
 454     return offset + len - 1;
 455 }
 456
 457 /* Check whether a given range covers a given byte. */
 458 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 459                                     uint64_t byte)
 460 {
 461     return offset <= byte && byte <= range_get_last(offset, len);
 462 }
 463
 464 /* Check whether 2 given ranges overlap.
 465  * Undefined if ranges that wrap around 0. */
 466 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 467                                  uint64_t first2, uint64_t len2)
 468 {
 469     uint64_t last1 = range_get_last(first1, len1);
 470     uint64_t last2 = range_get_last(first2, len2);
 471
 472     return !(last2 < first1 || last1 < first2);
 473 }
 474
 475 #endif