4 #include "qemu-common.h"
9 /* PCI includes legacy ISA access. */
16 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
18 #define PCI_FUNC(devfn) ((devfn) & 0x07)
19 #define PCI_FUNC_MAX 8
21 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 /* QEMU-specific Vendor and Device ID definitions */
27 #define PCI_DEVICE_ID_IBM_440GX 0x027f
28 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
30 /* Hitachi (0x1054) */
31 #define PCI_VENDOR_ID_HITACHI 0x1054
32 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
35 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
36 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
37 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
38 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
39 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
41 /* Realtek (0x10ec) */
42 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
45 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
47 /* Marvell (0x11ab) */
48 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
50 /* QEMU/Bochs VGA (0x1234) */
51 #define PCI_VENDOR_ID_QEMU 0x1234
52 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
55 #define PCI_VENDOR_ID_VMWARE 0x15ad
56 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
57 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
58 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
59 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
60 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
63 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
64 #define PCI_DEVICE_ID_INTEL_82557 0x1229
66 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
67 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
68 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
69 #define PCI_SUBDEVICE_ID_QEMU 0x1100
71 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
72 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
73 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
74 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
76 #define FMT_PCIBUS PRIx64
78 typedef void PCIConfigWriteFunc(PCIDevice
*pci_dev
,
79 uint32_t address
, uint32_t data
, int len
);
80 typedef uint32_t PCIConfigReadFunc(PCIDevice
*pci_dev
,
81 uint32_t address
, int len
);
82 typedef void PCIMapIORegionFunc(PCIDevice
*pci_dev
, int region_num
,
83 pcibus_t addr
, pcibus_t size
, int type
);
84 typedef int PCIUnregisterFunc(PCIDevice
*pci_dev
);
86 typedef struct PCIIORegion
{
87 pcibus_t addr
; /* current PCI mapping address. -1 means not mapped */
88 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
90 pcibus_t filtered_size
;
92 PCIMapIORegionFunc
*map_func
;
95 #define PCI_ROM_SLOT 6
96 #define PCI_NUM_REGIONS 7
100 /* PCI HEADER_TYPE */
101 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
103 /* Size of the standard PCI config header */
104 #define PCI_CONFIG_HEADER_SIZE 0x40
105 /* Size of the standard PCI config space */
106 #define PCI_CONFIG_SPACE_SIZE 0x100
107 /* Size of the standart PCIe config space: 4KB */
108 #define PCIE_CONFIG_SPACE_SIZE 0x1000
110 #define PCI_NUM_PINS 4 /* A-D */
112 /* Bits in cap_present field. */
114 QEMU_PCI_CAP_MSI
= 0x1,
115 QEMU_PCI_CAP_MSIX
= 0x2,
116 QEMU_PCI_CAP_EXPRESS
= 0x4,
118 /* multifunction capable device */
119 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
120 QEMU_PCI_CAP_MULTIFUNCTION
= (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR
),
122 /* command register SERR bit enabled */
123 #define QEMU_PCI_CAP_SERR_BITNR 4
124 QEMU_PCI_CAP_SERR
= (1 << QEMU_PCI_CAP_SERR_BITNR
),
129 /* PCI config space */
132 /* Used to enable config checks on load. Note that writeable bits are
133 * never checked even if set in cmask. */
136 /* Used to implement R/W bytes */
139 /* Used to implement RW1C(Write 1 to Clear) bytes */
142 /* Used to allocate config space for capabilities. */
145 /* the following fields are read only */
149 PCIIORegion io_regions
[PCI_NUM_REGIONS
];
151 /* do not access the following fields */
152 PCIConfigReadFunc
*config_read
;
153 PCIConfigWriteFunc
*config_write
;
155 /* IRQ objects for the INTA-INTD pins. */
158 /* Current IRQ levels. Used internally by the generic PCI code. */
161 /* Capability bits */
162 uint32_t cap_present
;
164 /* Offset of MSI-X capability in config space */
170 /* Space to store MSIX table */
171 uint8_t *msix_table_page
;
172 /* MMIO index used to map MSIX table and pending bit entries. */
174 /* Reference-count for entries actually in use by driver. */
175 unsigned *msix_entry_used
;
176 /* Region including the MSI-X table */
177 uint32_t msix_bar_size
;
178 /* Version id needed for VMState */
181 /* Offset of MSI capability in config space */
185 PCIExpressDevice exp
;
187 /* Location of option rom */
189 ram_addr_t rom_offset
;
193 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
194 int instance_size
, int devfn
,
195 PCIConfigReadFunc
*config_read
,
196 PCIConfigWriteFunc
*config_write
);
198 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
199 pcibus_t size
, uint8_t type
,
200 PCIMapIORegionFunc
*map_func
);
202 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
203 uint8_t offset
, uint8_t size
);
205 void pci_del_capability(PCIDevice
*pci_dev
, uint8_t cap_id
, uint8_t cap_size
);
207 void pci_reserve_capability(PCIDevice
*pci_dev
, uint8_t offset
, uint8_t size
);
209 uint8_t pci_find_capability(PCIDevice
*pci_dev
, uint8_t cap_id
);
212 uint32_t pci_default_read_config(PCIDevice
*d
,
213 uint32_t address
, int len
);
214 void pci_default_write_config(PCIDevice
*d
,
215 uint32_t address
, uint32_t val
, int len
);
216 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
);
217 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
);
219 typedef void (*pci_set_irq_fn
)(void *opaque
, int irq_num
, int level
);
220 typedef int (*pci_map_irq_fn
)(PCIDevice
*pci_dev
, int irq_num
);
223 PCI_HOTPLUG_DISABLED
,
225 PCI_COLDPLUG_ENABLED
,
228 typedef int (*pci_hotplug_fn
)(DeviceState
*qdev
, PCIDevice
*pci_dev
,
229 PCIHotplugState state
);
230 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
231 const char *name
, int devfn_min
);
232 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
);
233 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
234 void *irq_opaque
, int nirq
);
235 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*dev
);
236 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
237 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
238 void *irq_opaque
, int devfn_min
, int nirq
);
239 void pci_bus_reset(PCIBus
*bus
);
241 void pci_bus_set_mem_base(PCIBus
*bus
, target_phys_addr_t base
);
243 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
244 const char *default_devaddr
);
245 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
246 const char *default_devaddr
);
247 int pci_bus_num(PCIBus
*s
);
248 void pci_for_each_device(PCIBus
*bus
, int bus_num
, void (*fn
)(PCIBus
*bus
, PCIDevice
*d
));
249 PCIBus
*pci_find_root_bus(int domain
);
250 int pci_find_domain(const PCIBus
*bus
);
251 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
);
252 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, int slot
, int function
);
253 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
);
255 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
256 unsigned int *slotp
, unsigned int *funcp
);
257 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
260 void do_pci_info_print(Monitor
*mon
, const QObject
*data
);
261 void do_pci_info(Monitor
*mon
, QObject
**ret_data
);
262 void pci_bridge_update_mappings(PCIBus
*b
);
265 pci_set_byte(uint8_t *config
, uint8_t val
)
270 static inline uint8_t
271 pci_get_byte(const uint8_t *config
)
277 pci_set_word(uint8_t *config
, uint16_t val
)
279 cpu_to_le16wu((uint16_t *)config
, val
);
282 static inline uint16_t
283 pci_get_word(const uint8_t *config
)
285 return le16_to_cpupu((const uint16_t *)config
);
289 pci_set_long(uint8_t *config
, uint32_t val
)
291 cpu_to_le32wu((uint32_t *)config
, val
);
294 static inline uint32_t
295 pci_get_long(const uint8_t *config
)
297 return le32_to_cpupu((const uint32_t *)config
);
301 pci_set_quad(uint8_t *config
, uint64_t val
)
303 cpu_to_le64w((uint64_t *)config
, val
);
306 static inline uint64_t
307 pci_get_quad(const uint8_t *config
)
309 return le64_to_cpup((const uint64_t *)config
);
313 pci_config_set_vendor_id(uint8_t *pci_config
, uint16_t val
)
315 pci_set_word(&pci_config
[PCI_VENDOR_ID
], val
);
319 pci_config_set_device_id(uint8_t *pci_config
, uint16_t val
)
321 pci_set_word(&pci_config
[PCI_DEVICE_ID
], val
);
325 pci_config_set_revision(uint8_t *pci_config
, uint8_t val
)
327 pci_set_byte(&pci_config
[PCI_REVISION_ID
], val
);
331 pci_config_set_class(uint8_t *pci_config
, uint16_t val
)
333 pci_set_word(&pci_config
[PCI_CLASS_DEVICE
], val
);
337 pci_config_set_prog_interface(uint8_t *pci_config
, uint8_t val
)
339 pci_set_byte(&pci_config
[PCI_CLASS_PROG
], val
);
343 pci_config_set_interrupt_pin(uint8_t *pci_config
, uint8_t val
)
345 pci_set_byte(&pci_config
[PCI_INTERRUPT_PIN
], val
);
349 * helper functions to do bit mask operation on configuration space.
350 * Just to set bit, use test-and-set and discard returned value.
351 * Just to clear bit, use test-and-clear and discard returned value.
352 * NOTE: They aren't atomic.
354 static inline uint8_t
355 pci_byte_test_and_clear_mask(uint8_t *config
, uint8_t mask
)
357 uint8_t val
= pci_get_byte(config
);
358 pci_set_byte(config
, val
& ~mask
);
362 static inline uint8_t
363 pci_byte_test_and_set_mask(uint8_t *config
, uint8_t mask
)
365 uint8_t val
= pci_get_byte(config
);
366 pci_set_byte(config
, val
| mask
);
370 static inline uint16_t
371 pci_word_test_and_clear_mask(uint8_t *config
, uint16_t mask
)
373 uint16_t val
= pci_get_word(config
);
374 pci_set_word(config
, val
& ~mask
);
378 static inline uint16_t
379 pci_word_test_and_set_mask(uint8_t *config
, uint16_t mask
)
381 uint16_t val
= pci_get_word(config
);
382 pci_set_word(config
, val
| mask
);
386 static inline uint32_t
387 pci_long_test_and_clear_mask(uint8_t *config
, uint32_t mask
)
389 uint32_t val
= pci_get_long(config
);
390 pci_set_long(config
, val
& ~mask
);
394 static inline uint32_t
395 pci_long_test_and_set_mask(uint8_t *config
, uint32_t mask
)
397 uint32_t val
= pci_get_long(config
);
398 pci_set_long(config
, val
| mask
);
402 static inline uint64_t
403 pci_quad_test_and_clear_mask(uint8_t *config
, uint64_t mask
)
405 uint64_t val
= pci_get_quad(config
);
406 pci_set_quad(config
, val
& ~mask
);
410 static inline uint64_t
411 pci_quad_test_and_set_mask(uint8_t *config
, uint64_t mask
)
413 uint64_t val
= pci_get_quad(config
);
414 pci_set_quad(config
, val
| mask
);
418 typedef int (*pci_qdev_initfn
)(PCIDevice
*dev
);
421 pci_qdev_initfn init
;
422 PCIUnregisterFunc
*exit
;
423 PCIConfigReadFunc
*config_read
;
424 PCIConfigWriteFunc
*config_write
;
427 * pci-to-pci bridge or normal device.
428 * This doesn't mean pci host switch.
429 * When card bus bridge is supported, this would be enhanced.
434 int is_express
; /* is this device pci express? */
440 void pci_qdev_register(PCIDeviceInfo
*info
);
441 void pci_qdev_register_many(PCIDeviceInfo
*info
);
443 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
445 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
448 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
);
449 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
);
451 static inline int pci_is_express(const PCIDevice
*d
)
453 return d
->cap_present
& QEMU_PCI_CAP_EXPRESS
;
456 static inline uint32_t pci_config_size(const PCIDevice
*d
)
458 return pci_is_express(d
) ? PCIE_CONFIG_SPACE_SIZE
: PCI_CONFIG_SPACE_SIZE
;