hw/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "hw.h"
  40 #include "flash.h"
  41 #include "block/block.h"
  42 #include "qemu/timer.h"
  43 #include "exec/address-spaces.h"
  44 #include "qemu/host-utils.h"
  45 #include "sysbus.h"
  46
  47 #define PFLASH_BUG(fmt, ...) \
  48 do { \
  49     fprintf(stderr, "PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  50     exit(1); \
  51 } while(0)
  52
  53 /* #define PFLASH_DEBUG */
  54 #ifdef PFLASH_DEBUG
  55 #define DPRINTF(fmt, ...)                                   \
  56 do {                                                        \
  57     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  58 } while (0)
  59 #else
  60 #define DPRINTF(fmt, ...) do { } while (0)
  61 #endif
  62
  63 struct pflash_t {
  64     SysBusDevice busdev;
  65     BlockDriverState *bs;
  66     uint32_t nb_blocs;
  67     uint64_t sector_len;
  68     uint8_t width;
  69     uint8_t be;
  70     int wcycle; /* if 0, the flash is read normally */
  71     int bypass;
  72     int ro;
  73     uint8_t cmd;
  74     uint8_t status;
  75     uint16_t ident0;
  76     uint16_t ident1;
  77     uint16_t ident2;
  78     uint16_t ident3;
  79     uint8_t cfi_len;
  80     uint8_t cfi_table[0x52];
  81     hwaddr counter;
  82     unsigned int writeblock_size;
  83     QEMUTimer *timer;
  84     MemoryRegion mem;
  85     char *name;
  86     void *storage;
  87 };
  88
  89 static void pflash_timer (void *opaque)
  90 {
  91     pflash_t *pfl = opaque;
  92
  93     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  94     /* Reset flash */
  95     pfl->status ^= 0x80;
  96     if (pfl->bypass) {
  97         pfl->wcycle = 2;
  98     } else {
  99         memory_region_rom_device_set_readable(&pfl->mem, true);
 100         pfl->wcycle = 0;
 101     }
 102     pfl->cmd = 0;
 103 }
 104
 105 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
 106                              int width, int be)
 107 {
 108     hwaddr boff;
 109     uint32_t ret;
 110     uint8_t *p;
 111
 112     ret = -1;
 113     boff = offset & 0xFF; /* why this here ?? */
 114
 115     if (pfl->width == 2)
 116         boff = boff >> 1;
 117     else if (pfl->width == 4)
 118         boff = boff >> 2;
 119
 120 #if 0
 121     DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
 122             __func__, offset, pfl->cmd, width);
 123 #endif
 124     switch (pfl->cmd) {
 125     default:
 126         /* This should never happen : reset state & treat it as a read */
 127         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 128         pfl->wcycle = 0;
 129         pfl->cmd = 0;
 130         /* fall through to read code */
 131     case 0x00:
 132         /* Flash area read */
 133         p = pfl->storage;
 134         switch (width) {
 135         case 1:
 136             ret = p[offset];
 137             DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
 138                     __func__, offset, ret);
 139             break;
 140         case 2:
 141             if (be) {
 142                 ret = p[offset] << 8;
 143                 ret |= p[offset + 1];
 144             } else {
 145                 ret = p[offset];
 146                 ret |= p[offset + 1] << 8;
 147             }
 148             DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
 149                     __func__, offset, ret);
 150             break;
 151         case 4:
 152             if (be) {
 153                 ret = p[offset] << 24;
 154                 ret |= p[offset + 1] << 16;
 155                 ret |= p[offset + 2] << 8;
 156                 ret |= p[offset + 3];
 157             } else {
 158                 ret = p[offset];
 159                 ret |= p[offset + 1] << 8;
 160                 ret |= p[offset + 2] << 16;
 161                 ret |= p[offset + 3] << 24;
 162             }
 163             DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
 164                     __func__, offset, ret);
 165             break;
 166         default:
 167             DPRINTF("BUG in %s\n", __func__);
 168         }
 169
 170         break;
 171     case 0x10: /* Single byte program */
 172     case 0x20: /* Block erase */
 173     case 0x28: /* Block erase */
 174     case 0x40: /* single byte program */
 175     case 0x50: /* Clear status register */
 176     case 0x60: /* Block /un)lock */
 177     case 0x70: /* Status Register */
 178     case 0xe8: /* Write block */
 179         /* Status register read */
 180         ret = pfl->status;
 181         DPRINTF("%s: status %x\n", __func__, ret);
 182         break;
 183     case 0x90:
 184         switch (boff) {
 185         case 0:
 186             ret = pfl->ident0 << 8 | pfl->ident1;
 187             DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
 188             break;
 189         case 1:
 190             ret = pfl->ident2 << 8 | pfl->ident3;
 191             DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
 192             break;
 193         default:
 194             DPRINTF("%s: Read Device Information boff=%x\n", __func__,
 195                     (unsigned)boff);
 196             ret = 0;
 197             break;
 198         }
 199         break;
 200     case 0x98: /* Query mode */
 201         if (boff > pfl->cfi_len)
 202             ret = 0;
 203         else
 204             ret = pfl->cfi_table[boff];
 205         break;
 206     }
 207     return ret;
 208 }
 209
 210 /* update flash content on disk */
 211 static void pflash_update(pflash_t *pfl, int offset,
 212                           int size)
 213 {
 214     int offset_end;
 215     if (pfl->bs) {
 216         offset_end = offset + size;
 217         /* round to sectors */
 218         offset = offset >> 9;
 219         offset_end = (offset_end + 511) >> 9;
 220         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 221                    offset_end - offset);
 222     }
 223 }
 224
 225 static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
 226                                      uint32_t value, int width, int be)
 227 {
 228     uint8_t *p = pfl->storage;
 229
 230     DPRINTF("%s: block write offset " TARGET_FMT_plx
 231             " value %x counter " TARGET_FMT_plx "\n",
 232             __func__, offset, value, pfl->counter);
 233     switch (width) {
 234     case 1:
 235         p[offset] = value;
 236         break;
 237     case 2:
 238         if (be) {
 239             p[offset] = value >> 8;
 240             p[offset + 1] = value;
 241         } else {
 242             p[offset] = value;
 243             p[offset + 1] = value >> 8;
 244         }
 245         break;
 246     case 4:
 247         if (be) {
 248             p[offset] = value >> 24;
 249             p[offset + 1] = value >> 16;
 250             p[offset + 2] = value >> 8;
 251             p[offset + 3] = value;
 252         } else {
 253             p[offset] = value;
 254             p[offset + 1] = value >> 8;
 255             p[offset + 2] = value >> 16;
 256             p[offset + 3] = value >> 24;
 257         }
 258         break;
 259     }
 260
 261 }
 262
 263 static void pflash_write(pflash_t *pfl, hwaddr offset,
 264                          uint32_t value, int width, int be)
 265 {
 266     uint8_t *p;
 267     uint8_t cmd;
 268
 269     cmd = value;
 270
 271     DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
 272             __func__, offset, value, width, pfl->wcycle);
 273
 274     if (!pfl->wcycle) {
 275         /* Set the device in I/O access mode */
 276         memory_region_rom_device_set_readable(&pfl->mem, false);
 277     }
 278
 279     switch (pfl->wcycle) {
 280     case 0:
 281         /* read mode */
 282         switch (cmd) {
 283         case 0x00: /* ??? */
 284             goto reset_flash;
 285         case 0x10: /* Single Byte Program */
 286         case 0x40: /* Single Byte Program */
 287             DPRINTF("%s: Single Byte Program\n", __func__);
 288             break;
 289         case 0x20: /* Block erase */
 290             p = pfl->storage;
 291             offset &= ~(pfl->sector_len - 1);
 292
 293             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
 294                     __func__, offset, (unsigned)pfl->sector_len);
 295
 296             if (!pfl->ro) {
 297                 memset(p + offset, 0xff, pfl->sector_len);
 298                 pflash_update(pfl, offset, pfl->sector_len);
 299             } else {
 300                 pfl->status |= 0x20; /* Block erase error */
 301             }
 302             pfl->status |= 0x80; /* Ready! */
 303             break;
 304         case 0x50: /* Clear status bits */
 305             DPRINTF("%s: Clear status bits\n", __func__);
 306             pfl->status = 0x0;
 307             goto reset_flash;
 308         case 0x60: /* Block (un)lock */
 309             DPRINTF("%s: Block unlock\n", __func__);
 310             break;
 311         case 0x70: /* Status Register */
 312             DPRINTF("%s: Read status register\n", __func__);
 313             pfl->cmd = cmd;
 314             return;
 315         case 0x90: /* Read Device ID */
 316             DPRINTF("%s: Read Device information\n", __func__);
 317             pfl->cmd = cmd;
 318             return;
 319         case 0x98: /* CFI query */
 320             DPRINTF("%s: CFI query\n", __func__);
 321             break;
 322         case 0xe8: /* Write to buffer */
 323             DPRINTF("%s: Write to buffer\n", __func__);
 324             pfl->status |= 0x80; /* Ready! */
 325             break;
 326         case 0xf0: /* Probe for AMD flash */
 327             DPRINTF("%s: Probe for AMD flash\n", __func__);
 328             goto reset_flash;
 329         case 0xff: /* Read array mode */
 330             DPRINTF("%s: Read array mode\n", __func__);
 331             goto reset_flash;
 332         default:
 333             goto error_flash;
 334         }
 335         pfl->wcycle++;
 336         pfl->cmd = cmd;
 337         break;
 338     case 1:
 339         switch (pfl->cmd) {
 340         case 0x10: /* Single Byte Program */
 341         case 0x40: /* Single Byte Program */
 342             DPRINTF("%s: Single Byte Program\n", __func__);
 343             if (!pfl->ro) {
 344                 pflash_data_write(pfl, offset, value, width, be);
 345                 pflash_update(pfl, offset, width);
 346             } else {
 347                 pfl->status |= 0x10; /* Programming error */
 348             }
 349             pfl->status |= 0x80; /* Ready! */
 350             pfl->wcycle = 0;
 351         break;
 352         case 0x20: /* Block erase */
 353         case 0x28:
 354             if (cmd == 0xd0) { /* confirm */
 355                 pfl->wcycle = 0;
 356                 pfl->status |= 0x80;
 357             } else if (cmd == 0xff) { /* read array mode */
 358                 goto reset_flash;
 359             } else
 360                 goto error_flash;
 361
 362             break;
 363         case 0xe8:
 364             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 365             pfl->counter = value;
 366             pfl->wcycle++;
 367             break;
 368         case 0x60:
 369             if (cmd == 0xd0) {
 370                 pfl->wcycle = 0;
 371                 pfl->status |= 0x80;
 372             } else if (cmd == 0x01) {
 373                 pfl->wcycle = 0;
 374                 pfl->status |= 0x80;
 375             } else if (cmd == 0xff) {
 376                 goto reset_flash;
 377             } else {
 378                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 379                 goto reset_flash;
 380             }
 381             break;
 382         case 0x98:
 383             if (cmd == 0xff) {
 384                 goto reset_flash;
 385             } else {
 386                 DPRINTF("%s: leaving query mode\n", __func__);
 387             }
 388             break;
 389         default:
 390             goto error_flash;
 391         }
 392         break;
 393     case 2:
 394         switch (pfl->cmd) {
 395         case 0xe8: /* Block write */
 396             if (!pfl->ro) {
 397                 pflash_data_write(pfl, offset, value, width, be);
 398             } else {
 399                 pfl->status |= 0x10; /* Programming error */
 400             }
 401
 402             pfl->status |= 0x80;
 403
 404             if (!pfl->counter) {
 405                 hwaddr mask = pfl->writeblock_size - 1;
 406                 mask = ~mask;
 407
 408                 DPRINTF("%s: block write finished\n", __func__);
 409                 pfl->wcycle++;
 410                 if (!pfl->ro) {
 411                     /* Flush the entire write buffer onto backing storage.  */
 412                     pflash_update(pfl, offset & mask, pfl->writeblock_size);
 413                 } else {
 414                     pfl->status |= 0x10; /* Programming error */
 415                 }
 416             }
 417
 418             pfl->counter--;
 419             break;
 420         default:
 421             goto error_flash;
 422         }
 423         break;
 424     case 3: /* Confirm mode */
 425         switch (pfl->cmd) {
 426         case 0xe8: /* Block write */
 427             if (cmd == 0xd0) {
 428                 pfl->wcycle = 0;
 429                 pfl->status |= 0x80;
 430             } else {
 431                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 432                 PFLASH_BUG("Write block confirm");
 433                 goto reset_flash;
 434             }
 435             break;
 436         default:
 437             goto error_flash;
 438         }
 439         break;
 440     default:
 441         /* Should never happen */
 442         DPRINTF("%s: invalid write state\n",  __func__);
 443         goto reset_flash;
 444     }
 445     return;
 446
 447  error_flash:
 448     qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence "
 449                   "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)"
 450                   "\n", __func__, offset, pfl->wcycle, pfl->cmd, value);
 451
 452  reset_flash:
 453     memory_region_rom_device_set_readable(&pfl->mem, true);
 454
 455     pfl->bypass = 0;
 456     pfl->wcycle = 0;
 457     pfl->cmd = 0;
 458 }
 459
 460
 461 static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
 462 {
 463     return pflash_read(opaque, addr, 1, 1);
 464 }
 465
 466 static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
 467 {
 468     return pflash_read(opaque, addr, 1, 0);
 469 }
 470
 471 static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
 472 {
 473     pflash_t *pfl = opaque;
 474
 475     return pflash_read(pfl, addr, 2, 1);
 476 }
 477
 478 static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
 479 {
 480     pflash_t *pfl = opaque;
 481
 482     return pflash_read(pfl, addr, 2, 0);
 483 }
 484
 485 static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
 486 {
 487     pflash_t *pfl = opaque;
 488
 489     return pflash_read(pfl, addr, 4, 1);
 490 }
 491
 492 static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
 493 {
 494     pflash_t *pfl = opaque;
 495
 496     return pflash_read(pfl, addr, 4, 0);
 497 }
 498
 499 static void pflash_writeb_be(void *opaque, hwaddr addr,
 500                              uint32_t value)
 501 {
 502     pflash_write(opaque, addr, value, 1, 1);
 503 }
 504
 505 static void pflash_writeb_le(void *opaque, hwaddr addr,
 506                              uint32_t value)
 507 {
 508     pflash_write(opaque, addr, value, 1, 0);
 509 }
 510
 511 static void pflash_writew_be(void *opaque, hwaddr addr,
 512                              uint32_t value)
 513 {
 514     pflash_t *pfl = opaque;
 515
 516     pflash_write(pfl, addr, value, 2, 1);
 517 }
 518
 519 static void pflash_writew_le(void *opaque, hwaddr addr,
 520                              uint32_t value)
 521 {
 522     pflash_t *pfl = opaque;
 523
 524     pflash_write(pfl, addr, value, 2, 0);
 525 }
 526
 527 static void pflash_writel_be(void *opaque, hwaddr addr,
 528                              uint32_t value)
 529 {
 530     pflash_t *pfl = opaque;
 531
 532     pflash_write(pfl, addr, value, 4, 1);
 533 }
 534
 535 static void pflash_writel_le(void *opaque, hwaddr addr,
 536                              uint32_t value)
 537 {
 538     pflash_t *pfl = opaque;
 539
 540     pflash_write(pfl, addr, value, 4, 0);
 541 }
 542
 543 static const MemoryRegionOps pflash_cfi01_ops_be = {
 544     .old_mmio = {
 545         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 546         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 547     },
 548     .endianness = DEVICE_NATIVE_ENDIAN,
 549 };
 550
 551 static const MemoryRegionOps pflash_cfi01_ops_le = {
 552     .old_mmio = {
 553         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 554         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 555     },
 556     .endianness = DEVICE_NATIVE_ENDIAN,
 557 };
 558
 559 static int pflash_cfi01_init(SysBusDevice *dev)
 560 {
 561     pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev);
 562     uint64_t total_len;
 563     int ret;
 564
 565     total_len = pfl->sector_len * pfl->nb_blocs;
 566
 567     /* XXX: to be fixed */
 568 #if 0
 569     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 570         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 571         return NULL;
 572 #endif
 573
 574     memory_region_init_rom_device(
 575         &pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
 576         pfl->name, total_len);
 577     vmstate_register_ram(&pfl->mem, DEVICE(pfl));
 578     pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
 579     sysbus_init_mmio(dev, &pfl->mem);
 580
 581     if (pfl->bs) {
 582         /* read the initial flash content */
 583         ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 584
 585         if (ret < 0) {
 586             vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
 587             memory_region_destroy(&pfl->mem);
 588             return 1;
 589         }
 590     }
 591
 592     if (pfl->bs) {
 593         pfl->ro = bdrv_is_read_only(pfl->bs);
 594     } else {
 595         pfl->ro = 0;
 596     }
 597
 598     pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
 599     pfl->wcycle = 0;
 600     pfl->cmd = 0;
 601     pfl->status = 0;
 602     /* Hardcoded CFI table */
 603     pfl->cfi_len = 0x52;
 604     /* Standard "QRY" string */
 605     pfl->cfi_table[0x10] = 'Q';
 606     pfl->cfi_table[0x11] = 'R';
 607     pfl->cfi_table[0x12] = 'Y';
 608     /* Command set (Intel) */
 609     pfl->cfi_table[0x13] = 0x01;
 610     pfl->cfi_table[0x14] = 0x00;
 611     /* Primary extended table address (none) */
 612     pfl->cfi_table[0x15] = 0x31;
 613     pfl->cfi_table[0x16] = 0x00;
 614     /* Alternate command set (none) */
 615     pfl->cfi_table[0x17] = 0x00;
 616     pfl->cfi_table[0x18] = 0x00;
 617     /* Alternate extended table (none) */
 618     pfl->cfi_table[0x19] = 0x00;
 619     pfl->cfi_table[0x1A] = 0x00;
 620     /* Vcc min */
 621     pfl->cfi_table[0x1B] = 0x45;
 622     /* Vcc max */
 623     pfl->cfi_table[0x1C] = 0x55;
 624     /* Vpp min (no Vpp pin) */
 625     pfl->cfi_table[0x1D] = 0x00;
 626     /* Vpp max (no Vpp pin) */
 627     pfl->cfi_table[0x1E] = 0x00;
 628     /* Reserved */
 629     pfl->cfi_table[0x1F] = 0x07;
 630     /* Timeout for min size buffer write */
 631     pfl->cfi_table[0x20] = 0x07;
 632     /* Typical timeout for block erase */
 633     pfl->cfi_table[0x21] = 0x0a;
 634     /* Typical timeout for full chip erase (4096 ms) */
 635     pfl->cfi_table[0x22] = 0x00;
 636     /* Reserved */
 637     pfl->cfi_table[0x23] = 0x04;
 638     /* Max timeout for buffer write */
 639     pfl->cfi_table[0x24] = 0x04;
 640     /* Max timeout for block erase */
 641     pfl->cfi_table[0x25] = 0x04;
 642     /* Max timeout for chip erase */
 643     pfl->cfi_table[0x26] = 0x00;
 644     /* Device size */
 645     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 646     /* Flash device interface (8 & 16 bits) */
 647     pfl->cfi_table[0x28] = 0x02;
 648     pfl->cfi_table[0x29] = 0x00;
 649     /* Max number of bytes in multi-bytes write */
 650     if (pfl->width == 1) {
 651         pfl->cfi_table[0x2A] = 0x08;
 652     } else {
 653         pfl->cfi_table[0x2A] = 0x0B;
 654     }
 655     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 656
 657     pfl->cfi_table[0x2B] = 0x00;
 658     /* Number of erase block regions (uniform) */
 659     pfl->cfi_table[0x2C] = 0x01;
 660     /* Erase block region 1 */
 661     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 662     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 663     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 664     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 665
 666     /* Extended */
 667     pfl->cfi_table[0x31] = 'P';
 668     pfl->cfi_table[0x32] = 'R';
 669     pfl->cfi_table[0x33] = 'I';
 670
 671     pfl->cfi_table[0x34] = '1';
 672     pfl->cfi_table[0x35] = '0';
 673
 674     pfl->cfi_table[0x36] = 0x00;
 675     pfl->cfi_table[0x37] = 0x00;
 676     pfl->cfi_table[0x38] = 0x00;
 677     pfl->cfi_table[0x39] = 0x00;
 678
 679     pfl->cfi_table[0x3a] = 0x00;
 680
 681     pfl->cfi_table[0x3b] = 0x00;
 682     pfl->cfi_table[0x3c] = 0x00;
 683
 684     pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
 685
 686     return 0;
 687 }
 688
 689 static Property pflash_cfi01_properties[] = {
 690     DEFINE_PROP_DRIVE("drive", struct pflash_t, bs),
 691     DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
 692     DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0),
 693     DEFINE_PROP_UINT8("width", struct pflash_t, width, 0),
 694     DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
 695     DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
 696     DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
 697     DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
 698     DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
 699     DEFINE_PROP_STRING("name", struct pflash_t, name),
 700     DEFINE_PROP_END_OF_LIST(),
 701 };
 702
 703 static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
 704 {
 705     DeviceClass *dc = DEVICE_CLASS(klass);
 706     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 707
 708     k->init = pflash_cfi01_init;
 709     dc->props = pflash_cfi01_properties;
 710 }
 711
 712
 713 static const TypeInfo pflash_cfi01_info = {
 714     .name           = "cfi.pflash01",
 715     .parent         = TYPE_SYS_BUS_DEVICE,
 716     .instance_size  = sizeof(struct pflash_t),
 717     .class_init     = pflash_cfi01_class_init,
 718 };
 719
 720 static void pflash_cfi01_register_types(void)
 721 {
 722     type_register_static(&pflash_cfi01_info);
 723 }
 724
 725 type_init(pflash_cfi01_register_types)
 726
 727 pflash_t *pflash_cfi01_register(hwaddr base,
 728                                 DeviceState *qdev, const char *name,
 729                                 hwaddr size,
 730                                 BlockDriverState *bs,
 731                                 uint32_t sector_len, int nb_blocs, int width,
 732                                 uint16_t id0, uint16_t id1,
 733                                 uint16_t id2, uint16_t id3, int be)
 734 {
 735     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 736     SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
 737     pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev),
 738                                                     "cfi.pflash01");
 739
 740     if (bs && qdev_prop_set_drive(dev, "drive", bs)) {
 741         abort();
 742     }
 743     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
 744     qdev_prop_set_uint64(dev, "sector-length", sector_len);
 745     qdev_prop_set_uint8(dev, "width", width);
 746     qdev_prop_set_uint8(dev, "big-endian", !!be);
 747     qdev_prop_set_uint16(dev, "id0", id0);
 748     qdev_prop_set_uint16(dev, "id1", id1);
 749     qdev_prop_set_uint16(dev, "id2", id2);
 750     qdev_prop_set_uint16(dev, "id3", id3);
 751     qdev_prop_set_string(dev, "name", name);
 752     qdev_init_nofail(dev);
 753
 754     sysbus_mmio_map(busdev, 0, base);
 755     return pfl;
 756 }
 757
 758 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
 759 {
 760     return &fl->mem;
 761 }