hw/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "hw.h"
  40 #include "flash.h"
  41 #include "block.h"
  42 #include "qemu-timer.h"
  43 #include "exec-memory.h"
  44 #include "host-utils.h"
  45 #include "sysbus.h"
  46
  47 #define PFLASH_BUG(fmt, ...) \
  48 do { \
  49     printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  50     exit(1); \
  51 } while(0)
  52
  53 /* #define PFLASH_DEBUG */
  54 #ifdef PFLASH_DEBUG
  55 #define DPRINTF(fmt, ...)                          \
  56 do {                                               \
  57     printf("PFLASH: " fmt , ## __VA_ARGS__);       \
  58 } while (0)
  59 #else
  60 #define DPRINTF(fmt, ...) do { } while (0)
  61 #endif
  62
  63 struct pflash_t {
  64     SysBusDevice busdev;
  65     BlockDriverState *bs;
  66     uint32_t nb_blocs;
  67     uint64_t sector_len;
  68     uint8_t width;
  69     uint8_t be;
  70     int wcycle; /* if 0, the flash is read normally */
  71     int bypass;
  72     int ro;
  73     uint8_t cmd;
  74     uint8_t status;
  75     uint16_t ident0;
  76     uint16_t ident1;
  77     uint16_t ident2;
  78     uint16_t ident3;
  79     uint8_t cfi_len;
  80     uint8_t cfi_table[0x52];
  81     hwaddr counter;
  82     unsigned int writeblock_size;
  83     QEMUTimer *timer;
  84     MemoryRegion mem;
  85     char *name;
  86     void *storage;
  87 };
  88
  89 static void pflash_timer (void *opaque)
  90 {
  91     pflash_t *pfl = opaque;
  92
  93     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  94     /* Reset flash */
  95     pfl->status ^= 0x80;
  96     if (pfl->bypass) {
  97         pfl->wcycle = 2;
  98     } else {
  99         memory_region_rom_device_set_readable(&pfl->mem, true);
 100         pfl->wcycle = 0;
 101     }
 102     pfl->cmd = 0;
 103 }
 104
 105 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
 106                              int width, int be)
 107 {
 108     hwaddr boff;
 109     uint32_t ret;
 110     uint8_t *p;
 111
 112     ret = -1;
 113     boff = offset & 0xFF; /* why this here ?? */
 114
 115     if (pfl->width == 2)
 116         boff = boff >> 1;
 117     else if (pfl->width == 4)
 118         boff = boff >> 2;
 119
 120 #if 0
 121     DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
 122             __func__, offset, pfl->cmd, width);
 123 #endif
 124     switch (pfl->cmd) {
 125     case 0x00:
 126         /* Flash area read */
 127         p = pfl->storage;
 128         switch (width) {
 129         case 1:
 130             ret = p[offset];
 131             DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
 132                     __func__, offset, ret);
 133             break;
 134         case 2:
 135             if (be) {
 136                 ret = p[offset] << 8;
 137                 ret |= p[offset + 1];
 138             } else {
 139                 ret = p[offset];
 140                 ret |= p[offset + 1] << 8;
 141             }
 142             DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
 143                     __func__, offset, ret);
 144             break;
 145         case 4:
 146             if (be) {
 147                 ret = p[offset] << 24;
 148                 ret |= p[offset + 1] << 16;
 149                 ret |= p[offset + 2] << 8;
 150                 ret |= p[offset + 3];
 151             } else {
 152                 ret = p[offset];
 153                 ret |= p[offset + 1] << 8;
 154                 ret |= p[offset + 2] << 16;
 155                 ret |= p[offset + 3] << 24;
 156             }
 157             DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
 158                     __func__, offset, ret);
 159             break;
 160         default:
 161             DPRINTF("BUG in %s\n", __func__);
 162         }
 163
 164         break;
 165     case 0x20: /* Block erase */
 166     case 0x50: /* Clear status register */
 167     case 0x60: /* Block /un)lock */
 168     case 0x70: /* Status Register */
 169     case 0xe8: /* Write block */
 170         /* Status register read */
 171         ret = pfl->status;
 172         DPRINTF("%s: status %x\n", __func__, ret);
 173         break;
 174     case 0x90:
 175         switch (boff) {
 176         case 0:
 177             ret = pfl->ident0 << 8 | pfl->ident1;
 178             DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
 179             break;
 180         case 1:
 181             ret = pfl->ident2 << 8 | pfl->ident3;
 182             DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
 183             break;
 184         default:
 185             DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff);
 186             ret = 0;
 187             break;
 188         }
 189         break;
 190     case 0x98: /* Query mode */
 191         if (boff > pfl->cfi_len)
 192             ret = 0;
 193         else
 194             ret = pfl->cfi_table[boff];
 195         break;
 196     default:
 197         /* This should never happen : reset state & treat it as a read */
 198         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 199         pfl->wcycle = 0;
 200         pfl->cmd = 0;
 201     }
 202     return ret;
 203 }
 204
 205 /* update flash content on disk */
 206 static void pflash_update(pflash_t *pfl, int offset,
 207                           int size)
 208 {
 209     int offset_end;
 210     if (pfl->bs) {
 211         offset_end = offset + size;
 212         /* round to sectors */
 213         offset = offset >> 9;
 214         offset_end = (offset_end + 511) >> 9;
 215         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 216                    offset_end - offset);
 217     }
 218 }
 219
 220 static inline void pflash_data_write(pflash_t *pfl, hwaddr offset,
 221                                      uint32_t value, int width, int be)
 222 {
 223     uint8_t *p = pfl->storage;
 224
 225     DPRINTF("%s: block write offset " TARGET_FMT_plx
 226             " value %x counter " TARGET_FMT_plx "\n",
 227             __func__, offset, value, pfl->counter);
 228     switch (width) {
 229     case 1:
 230         p[offset] = value;
 231         break;
 232     case 2:
 233         if (be) {
 234             p[offset] = value >> 8;
 235             p[offset + 1] = value;
 236         } else {
 237             p[offset] = value;
 238             p[offset + 1] = value >> 8;
 239         }
 240         break;
 241     case 4:
 242         if (be) {
 243             p[offset] = value >> 24;
 244             p[offset + 1] = value >> 16;
 245             p[offset + 2] = value >> 8;
 246             p[offset + 3] = value;
 247         } else {
 248             p[offset] = value;
 249             p[offset + 1] = value >> 8;
 250             p[offset + 2] = value >> 16;
 251             p[offset + 3] = value >> 24;
 252         }
 253         break;
 254     }
 255
 256 }
 257
 258 static void pflash_write(pflash_t *pfl, hwaddr offset,
 259                          uint32_t value, int width, int be)
 260 {
 261     uint8_t *p;
 262     uint8_t cmd;
 263
 264     cmd = value;
 265
 266     DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
 267             __func__, offset, value, width, pfl->wcycle);
 268
 269     if (!pfl->wcycle) {
 270         /* Set the device in I/O access mode */
 271         memory_region_rom_device_set_readable(&pfl->mem, false);
 272     }
 273
 274     switch (pfl->wcycle) {
 275     case 0:
 276         /* read mode */
 277         switch (cmd) {
 278         case 0x00: /* ??? */
 279             goto reset_flash;
 280         case 0x10: /* Single Byte Program */
 281         case 0x40: /* Single Byte Program */
 282             DPRINTF("%s: Single Byte Program\n", __func__);
 283             break;
 284         case 0x20: /* Block erase */
 285             p = pfl->storage;
 286             offset &= ~(pfl->sector_len - 1);
 287
 288             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n",
 289                     __func__, offset, (unsigned)pfl->sector_len);
 290
 291             if (!pfl->ro) {
 292                 memset(p + offset, 0xff, pfl->sector_len);
 293                 pflash_update(pfl, offset, pfl->sector_len);
 294             } else {
 295                 pfl->status |= 0x20; /* Block erase error */
 296             }
 297             pfl->status |= 0x80; /* Ready! */
 298             break;
 299         case 0x50: /* Clear status bits */
 300             DPRINTF("%s: Clear status bits\n", __func__);
 301             pfl->status = 0x0;
 302             goto reset_flash;
 303         case 0x60: /* Block (un)lock */
 304             DPRINTF("%s: Block unlock\n", __func__);
 305             break;
 306         case 0x70: /* Status Register */
 307             DPRINTF("%s: Read status register\n", __func__);
 308             pfl->cmd = cmd;
 309             return;
 310         case 0x90: /* Read Device ID */
 311             DPRINTF("%s: Read Device information\n", __func__);
 312             pfl->cmd = cmd;
 313             return;
 314         case 0x98: /* CFI query */
 315             DPRINTF("%s: CFI query\n", __func__);
 316             break;
 317         case 0xe8: /* Write to buffer */
 318             DPRINTF("%s: Write to buffer\n", __func__);
 319             pfl->status |= 0x80; /* Ready! */
 320             break;
 321         case 0xff: /* Read array mode */
 322             DPRINTF("%s: Read array mode\n", __func__);
 323             goto reset_flash;
 324         default:
 325             goto error_flash;
 326         }
 327         pfl->wcycle++;
 328         pfl->cmd = cmd;
 329         break;
 330     case 1:
 331         switch (pfl->cmd) {
 332         case 0x10: /* Single Byte Program */
 333         case 0x40: /* Single Byte Program */
 334             DPRINTF("%s: Single Byte Program\n", __func__);
 335             if (!pfl->ro) {
 336                 pflash_data_write(pfl, offset, value, width, be);
 337                 pflash_update(pfl, offset, width);
 338             } else {
 339                 pfl->status |= 0x10; /* Programming error */
 340             }
 341             pfl->status |= 0x80; /* Ready! */
 342             pfl->wcycle = 0;
 343         break;
 344         case 0x20: /* Block erase */
 345         case 0x28:
 346             if (cmd == 0xd0) { /* confirm */
 347                 pfl->wcycle = 0;
 348                 pfl->status |= 0x80;
 349             } else if (cmd == 0xff) { /* read array mode */
 350                 goto reset_flash;
 351             } else
 352                 goto error_flash;
 353
 354             break;
 355         case 0xe8:
 356             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 357             pfl->counter = value;
 358             pfl->wcycle++;
 359             break;
 360         case 0x60:
 361             if (cmd == 0xd0) {
 362                 pfl->wcycle = 0;
 363                 pfl->status |= 0x80;
 364             } else if (cmd == 0x01) {
 365                 pfl->wcycle = 0;
 366                 pfl->status |= 0x80;
 367             } else if (cmd == 0xff) {
 368                 goto reset_flash;
 369             } else {
 370                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 371                 goto reset_flash;
 372             }
 373             break;
 374         case 0x98:
 375             if (cmd == 0xff) {
 376                 goto reset_flash;
 377             } else {
 378                 DPRINTF("%s: leaving query mode\n", __func__);
 379             }
 380             break;
 381         default:
 382             goto error_flash;
 383         }
 384         break;
 385     case 2:
 386         switch (pfl->cmd) {
 387         case 0xe8: /* Block write */
 388             if (!pfl->ro) {
 389                 pflash_data_write(pfl, offset, value, width, be);
 390             } else {
 391                 pfl->status |= 0x10; /* Programming error */
 392             }
 393
 394             pfl->status |= 0x80;
 395
 396             if (!pfl->counter) {
 397                 hwaddr mask = pfl->writeblock_size - 1;
 398                 mask = ~mask;
 399
 400                 DPRINTF("%s: block write finished\n", __func__);
 401                 pfl->wcycle++;
 402                 if (!pfl->ro) {
 403                     /* Flush the entire write buffer onto backing storage.  */
 404                     pflash_update(pfl, offset & mask, pfl->writeblock_size);
 405                 } else {
 406                     pfl->status |= 0x10; /* Programming error */
 407                 }
 408             }
 409
 410             pfl->counter--;
 411             break;
 412         default:
 413             goto error_flash;
 414         }
 415         break;
 416     case 3: /* Confirm mode */
 417         switch (pfl->cmd) {
 418         case 0xe8: /* Block write */
 419             if (cmd == 0xd0) {
 420                 pfl->wcycle = 0;
 421                 pfl->status |= 0x80;
 422             } else {
 423                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 424                 PFLASH_BUG("Write block confirm");
 425                 goto reset_flash;
 426             }
 427             break;
 428         default:
 429             goto error_flash;
 430         }
 431         break;
 432     default:
 433         /* Should never happen */
 434         DPRINTF("%s: invalid write state\n",  __func__);
 435         goto reset_flash;
 436     }
 437     return;
 438
 439  error_flash:
 440     printf("%s: Unimplemented flash cmd sequence "
 441            "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n",
 442            __func__, offset, pfl->wcycle, pfl->cmd, value);
 443
 444  reset_flash:
 445     memory_region_rom_device_set_readable(&pfl->mem, true);
 446
 447     pfl->bypass = 0;
 448     pfl->wcycle = 0;
 449     pfl->cmd = 0;
 450 }
 451
 452
 453 static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
 454 {
 455     return pflash_read(opaque, addr, 1, 1);
 456 }
 457
 458 static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
 459 {
 460     return pflash_read(opaque, addr, 1, 0);
 461 }
 462
 463 static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
 464 {
 465     pflash_t *pfl = opaque;
 466
 467     return pflash_read(pfl, addr, 2, 1);
 468 }
 469
 470 static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
 471 {
 472     pflash_t *pfl = opaque;
 473
 474     return pflash_read(pfl, addr, 2, 0);
 475 }
 476
 477 static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
 478 {
 479     pflash_t *pfl = opaque;
 480
 481     return pflash_read(pfl, addr, 4, 1);
 482 }
 483
 484 static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
 485 {
 486     pflash_t *pfl = opaque;
 487
 488     return pflash_read(pfl, addr, 4, 0);
 489 }
 490
 491 static void pflash_writeb_be(void *opaque, hwaddr addr,
 492                              uint32_t value)
 493 {
 494     pflash_write(opaque, addr, value, 1, 1);
 495 }
 496
 497 static void pflash_writeb_le(void *opaque, hwaddr addr,
 498                              uint32_t value)
 499 {
 500     pflash_write(opaque, addr, value, 1, 0);
 501 }
 502
 503 static void pflash_writew_be(void *opaque, hwaddr addr,
 504                              uint32_t value)
 505 {
 506     pflash_t *pfl = opaque;
 507
 508     pflash_write(pfl, addr, value, 2, 1);
 509 }
 510
 511 static void pflash_writew_le(void *opaque, hwaddr addr,
 512                              uint32_t value)
 513 {
 514     pflash_t *pfl = opaque;
 515
 516     pflash_write(pfl, addr, value, 2, 0);
 517 }
 518
 519 static void pflash_writel_be(void *opaque, hwaddr addr,
 520                              uint32_t value)
 521 {
 522     pflash_t *pfl = opaque;
 523
 524     pflash_write(pfl, addr, value, 4, 1);
 525 }
 526
 527 static void pflash_writel_le(void *opaque, hwaddr addr,
 528                              uint32_t value)
 529 {
 530     pflash_t *pfl = opaque;
 531
 532     pflash_write(pfl, addr, value, 4, 0);
 533 }
 534
 535 static const MemoryRegionOps pflash_cfi01_ops_be = {
 536     .old_mmio = {
 537         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 538         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 539     },
 540     .endianness = DEVICE_NATIVE_ENDIAN,
 541 };
 542
 543 static const MemoryRegionOps pflash_cfi01_ops_le = {
 544     .old_mmio = {
 545         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 546         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 547     },
 548     .endianness = DEVICE_NATIVE_ENDIAN,
 549 };
 550
 551 static int pflash_cfi01_init(SysBusDevice *dev)
 552 {
 553     pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev);
 554     uint64_t total_len;
 555     int ret;
 556
 557     total_len = pfl->sector_len * pfl->nb_blocs;
 558
 559     /* XXX: to be fixed */
 560 #if 0
 561     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 562         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 563         return NULL;
 564 #endif
 565
 566     memory_region_init_rom_device(
 567         &pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
 568         pfl->name, total_len);
 569     vmstate_register_ram(&pfl->mem, DEVICE(pfl));
 570     pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
 571     sysbus_init_mmio(dev, &pfl->mem);
 572
 573     if (pfl->bs) {
 574         /* read the initial flash content */
 575         ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 576
 577         if (ret < 0) {
 578             vmstate_unregister_ram(&pfl->mem, DEVICE(pfl));
 579             memory_region_destroy(&pfl->mem);
 580             return 1;
 581         }
 582     }
 583
 584     if (pfl->bs) {
 585         pfl->ro = bdrv_is_read_only(pfl->bs);
 586     } else {
 587         pfl->ro = 0;
 588     }
 589
 590     pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
 591     pfl->wcycle = 0;
 592     pfl->cmd = 0;
 593     pfl->status = 0;
 594     /* Hardcoded CFI table */
 595     pfl->cfi_len = 0x52;
 596     /* Standard "QRY" string */
 597     pfl->cfi_table[0x10] = 'Q';
 598     pfl->cfi_table[0x11] = 'R';
 599     pfl->cfi_table[0x12] = 'Y';
 600     /* Command set (Intel) */
 601     pfl->cfi_table[0x13] = 0x01;
 602     pfl->cfi_table[0x14] = 0x00;
 603     /* Primary extended table address (none) */
 604     pfl->cfi_table[0x15] = 0x31;
 605     pfl->cfi_table[0x16] = 0x00;
 606     /* Alternate command set (none) */
 607     pfl->cfi_table[0x17] = 0x00;
 608     pfl->cfi_table[0x18] = 0x00;
 609     /* Alternate extended table (none) */
 610     pfl->cfi_table[0x19] = 0x00;
 611     pfl->cfi_table[0x1A] = 0x00;
 612     /* Vcc min */
 613     pfl->cfi_table[0x1B] = 0x45;
 614     /* Vcc max */
 615     pfl->cfi_table[0x1C] = 0x55;
 616     /* Vpp min (no Vpp pin) */
 617     pfl->cfi_table[0x1D] = 0x00;
 618     /* Vpp max (no Vpp pin) */
 619     pfl->cfi_table[0x1E] = 0x00;
 620     /* Reserved */
 621     pfl->cfi_table[0x1F] = 0x07;
 622     /* Timeout for min size buffer write */
 623     pfl->cfi_table[0x20] = 0x07;
 624     /* Typical timeout for block erase */
 625     pfl->cfi_table[0x21] = 0x0a;
 626     /* Typical timeout for full chip erase (4096 ms) */
 627     pfl->cfi_table[0x22] = 0x00;
 628     /* Reserved */
 629     pfl->cfi_table[0x23] = 0x04;
 630     /* Max timeout for buffer write */
 631     pfl->cfi_table[0x24] = 0x04;
 632     /* Max timeout for block erase */
 633     pfl->cfi_table[0x25] = 0x04;
 634     /* Max timeout for chip erase */
 635     pfl->cfi_table[0x26] = 0x00;
 636     /* Device size */
 637     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 638     /* Flash device interface (8 & 16 bits) */
 639     pfl->cfi_table[0x28] = 0x02;
 640     pfl->cfi_table[0x29] = 0x00;
 641     /* Max number of bytes in multi-bytes write */
 642     if (pfl->width == 1) {
 643         pfl->cfi_table[0x2A] = 0x08;
 644     } else {
 645         pfl->cfi_table[0x2A] = 0x0B;
 646     }
 647     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 648
 649     pfl->cfi_table[0x2B] = 0x00;
 650     /* Number of erase block regions (uniform) */
 651     pfl->cfi_table[0x2C] = 0x01;
 652     /* Erase block region 1 */
 653     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 654     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 655     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 656     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 657
 658     /* Extended */
 659     pfl->cfi_table[0x31] = 'P';
 660     pfl->cfi_table[0x32] = 'R';
 661     pfl->cfi_table[0x33] = 'I';
 662
 663     pfl->cfi_table[0x34] = '1';
 664     pfl->cfi_table[0x35] = '0';
 665
 666     pfl->cfi_table[0x36] = 0x00;
 667     pfl->cfi_table[0x37] = 0x00;
 668     pfl->cfi_table[0x38] = 0x00;
 669     pfl->cfi_table[0x39] = 0x00;
 670
 671     pfl->cfi_table[0x3a] = 0x00;
 672
 673     pfl->cfi_table[0x3b] = 0x00;
 674     pfl->cfi_table[0x3c] = 0x00;
 675
 676     pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
 677
 678     return 0;
 679 }
 680
 681 static Property pflash_cfi01_properties[] = {
 682     DEFINE_PROP_DRIVE("drive", struct pflash_t, bs),
 683     DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
 684     DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0),
 685     DEFINE_PROP_UINT8("width", struct pflash_t, width, 0),
 686     DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
 687     DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
 688     DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
 689     DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
 690     DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
 691     DEFINE_PROP_STRING("name", struct pflash_t, name),
 692     DEFINE_PROP_END_OF_LIST(),
 693 };
 694
 695 static void pflash_cfi01_class_init(ObjectClass *klass, void *data)
 696 {
 697     DeviceClass *dc = DEVICE_CLASS(klass);
 698     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 699
 700     k->init = pflash_cfi01_init;
 701     dc->props = pflash_cfi01_properties;
 702 }
 703
 704
 705 static const TypeInfo pflash_cfi01_info = {
 706     .name           = "cfi.pflash01",
 707     .parent         = TYPE_SYS_BUS_DEVICE,
 708     .instance_size  = sizeof(struct pflash_t),
 709     .class_init     = pflash_cfi01_class_init,
 710 };
 711
 712 static void pflash_cfi01_register_types(void)
 713 {
 714     type_register_static(&pflash_cfi01_info);
 715 }
 716
 717 type_init(pflash_cfi01_register_types)
 718
 719 pflash_t *pflash_cfi01_register(hwaddr base,
 720                                 DeviceState *qdev, const char *name,
 721                                 hwaddr size,
 722                                 BlockDriverState *bs,
 723                                 uint32_t sector_len, int nb_blocs, int width,
 724                                 uint16_t id0, uint16_t id1,
 725                                 uint16_t id2, uint16_t id3, int be)
 726 {
 727     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 728     SysBusDevice *busdev = sysbus_from_qdev(dev);
 729     pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev),
 730                                                     "cfi.pflash01");
 731
 732     if (bs && qdev_prop_set_drive(dev, "drive", bs)) {
 733         abort();
 734     }
 735     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
 736     qdev_prop_set_uint64(dev, "sector-length", sector_len);
 737     qdev_prop_set_uint8(dev, "width", width);
 738     qdev_prop_set_uint8(dev, "big-endian", !!be);
 739     qdev_prop_set_uint16(dev, "id0", id0);
 740     qdev_prop_set_uint16(dev, "id1", id1);
 741     qdev_prop_set_uint16(dev, "id2", id2);
 742     qdev_prop_set_uint16(dev, "id3", id3);
 743     qdev_prop_set_string(dev, "name", name);
 744     qdev_init_nofail(dev);
 745
 746     sysbus_mmio_map(busdev, 0, base);
 747     return pfl;
 748 }
 749
 750 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
 751 {
 752     return &fl->mem;
 753 }