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git.proxmox.com Git - qemu.git/blob - hw/pflash_cfi02.c
2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
29 * - unlock bypass command
32 * It does not support flash interleaving.
33 * It does not implement boot blocs with reduced size
34 * It does not implement software data protection as found in many real chips
35 * It does not implement erase suspend/resume commands
36 * It does not implement multiple sectors erase
41 #include "qemu-timer.h"
44 //#define PFLASH_DEBUG
46 #define DPRINTF(fmt, args...) \
48 printf("PFLASH: " fmt , ##args); \
51 #define DPRINTF(fmt, args...) do { } while (0)
56 target_phys_addr_t base
;
60 int wcycle
; /* if 0, the flash is read normally */
66 uint16_t unlock_addr
[2];
68 uint8_t cfi_table
[0x52];
75 static void pflash_timer (void *opaque
)
77 pflash_t
*pfl
= opaque
;
79 DPRINTF("%s: command %02x done\n", __func__
, pfl
->cmd
);
85 cpu_register_physical_memory(pfl
->base
, pfl
->total_len
,
86 pfl
->off
| IO_MEM_ROMD
| pfl
->fl_mem
);
92 static uint32_t pflash_read (pflash_t
*pfl
, uint32_t offset
, int width
)
98 DPRINTF("%s: offset " TARGET_FMT_lx
"\n", __func__
, offset
);
101 boff
= offset
& 0xFF;
104 else if (pfl
->width
== 4)
108 /* This should never happen : reset state & treat it as a read*/
109 DPRINTF("%s: unknown command state: %x\n", __func__
, pfl
->cmd
);
113 /* We accept reads during second unlock sequence... */
116 /* Flash area read */
121 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
124 #if defined(TARGET_WORDS_BIGENDIAN)
125 ret
= p
[offset
] << 8;
126 ret
|= p
[offset
+ 1];
129 ret
|= p
[offset
+ 1] << 8;
131 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
134 #if defined(TARGET_WORDS_BIGENDIAN)
135 ret
= p
[offset
] << 24;
136 ret
|= p
[offset
+ 1] << 16;
137 ret
|= p
[offset
+ 2] << 8;
138 ret
|= p
[offset
+ 3];
141 ret
|= p
[offset
+ 1] << 8;
142 ret
|= p
[offset
+ 2] << 16;
143 ret
|= p
[offset
+ 3] << 24;
145 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
154 ret
= pfl
->ident
[boff
& 0x01];
157 ret
= 0x00; /* Pretend all sectors are unprotected */
161 if (pfl
->ident
[2 + (boff
& 0x01)] == (uint8_t)-1)
163 ret
= pfl
->ident
[2 + (boff
& 0x01)];
168 DPRINTF("%s: ID " TARGET_FMT_ld
" %x\n", __func__
, boff
, ret
);
173 /* Status register read */
175 DPRINTF("%s: status %x\n", __func__
, ret
);
181 if (boff
> pfl
->cfi_len
)
184 ret
= pfl
->cfi_table
[boff
];
191 /* update flash content on disk */
192 static void pflash_update(pflash_t
*pfl
, int offset
,
197 offset_end
= offset
+ size
;
198 /* round to sectors */
199 offset
= offset
>> 9;
200 offset_end
= (offset_end
+ 511) >> 9;
201 bdrv_write(pfl
->bs
, offset
, pfl
->storage
+ (offset
<< 9),
202 offset_end
- offset
);
206 static void pflash_write (pflash_t
*pfl
, uint32_t offset
, uint32_t value
,
213 /* WARNING: when the memory area is in ROMD mode, the offset is a
214 ram offset, not a physical address */
216 if (pfl
->cmd
!= 0xA0 && cmd
== 0xF0) {
218 DPRINTF("%s: flash reset asked (%02x %02x)\n",
219 __func__
, pfl
->cmd
, cmd
);
223 DPRINTF("%s: offset " TARGET_FMT_lx
" %08x %d %d\n", __func__
,
224 offset
, value
, width
, pfl
->wcycle
);
225 if (pfl
->wcycle
== 0)
226 offset
-= (uint32_t)(long)pfl
->storage
;
230 DPRINTF("%s: offset " TARGET_FMT_lx
" %08x %d\n", __func__
,
231 offset
, value
, width
);
232 /* Set the device in I/O access mode */
233 cpu_register_physical_memory(pfl
->base
, pfl
->total_len
, pfl
->fl_mem
);
234 boff
= offset
& (pfl
->sector_len
- 1);
237 else if (pfl
->width
== 4)
239 switch (pfl
->wcycle
) {
241 /* We're in read mode */
243 if (boff
== 0x55 && cmd
== 0x98) {
245 /* Enter CFI query mode */
250 if (boff
!= pfl
->unlock_addr
[0] || cmd
!= 0xAA) {
251 DPRINTF("%s: unlock0 failed " TARGET_FMT_lx
" %02x %04x\n",
252 __func__
, boff
, cmd
, pfl
->unlock_addr
[0]);
255 DPRINTF("%s: unlock sequence started\n", __func__
);
258 /* We started an unlock sequence */
260 if (boff
!= pfl
->unlock_addr
[1] || cmd
!= 0x55) {
261 DPRINTF("%s: unlock1 failed " TARGET_FMT_lx
" %02x\n", __func__
,
265 DPRINTF("%s: unlock sequence done\n", __func__
);
268 /* We finished an unlock sequence */
269 if (!pfl
->bypass
&& boff
!= pfl
->unlock_addr
[0]) {
270 DPRINTF("%s: command failed " TARGET_FMT_lx
" %02x\n", __func__
,
282 DPRINTF("%s: starting command %02x\n", __func__
, cmd
);
285 DPRINTF("%s: unknown command %02x\n", __func__
, cmd
);
292 /* We need another unlock sequence */
295 DPRINTF("%s: write data offset " TARGET_FMT_lx
" %08x %d\n",
296 __func__
, offset
, value
, width
);
301 pflash_update(pfl
, offset
, 1);
304 #if defined(TARGET_WORDS_BIGENDIAN)
305 p
[offset
] &= value
>> 8;
306 p
[offset
+ 1] &= value
;
309 p
[offset
+ 1] &= value
>> 8;
311 pflash_update(pfl
, offset
, 2);
314 #if defined(TARGET_WORDS_BIGENDIAN)
315 p
[offset
] &= value
>> 24;
316 p
[offset
+ 1] &= value
>> 16;
317 p
[offset
+ 2] &= value
>> 8;
318 p
[offset
+ 3] &= value
;
321 p
[offset
+ 1] &= value
>> 8;
322 p
[offset
+ 2] &= value
>> 16;
323 p
[offset
+ 3] &= value
>> 24;
325 pflash_update(pfl
, offset
, 4);
328 pfl
->status
= 0x00 | ~(value
& 0x80);
329 /* Let's pretend write is immediate */
334 if (pfl
->bypass
&& cmd
== 0x00) {
335 /* Unlock bypass reset */
338 /* We can enter CFI query mode from autoselect mode */
339 if (boff
== 0x55 && cmd
== 0x98)
343 DPRINTF("%s: invalid write for command %02x\n",
350 /* Ignore writes while flash data write is occuring */
351 /* As we suppose write is immediate, this should never happen */
356 /* Should never happen */
357 DPRINTF("%s: invalid command state %02x (wc 4)\n",
365 if (boff
!= pfl
->unlock_addr
[0]) {
366 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx
"\n",
371 DPRINTF("%s: start chip erase\n", __func__
);
372 memset(pfl
->storage
, 0xFF, pfl
->total_len
);
374 pflash_update(pfl
, 0, pfl
->total_len
);
375 /* Let's wait 5 seconds before chip erase is done */
376 qemu_mod_timer(pfl
->timer
,
377 qemu_get_clock(vm_clock
) + (ticks_per_sec
* 5));
382 offset
&= ~(pfl
->sector_len
- 1);
383 DPRINTF("%s: start sector erase at " TARGET_FMT_lx
"\n", __func__
,
385 memset(p
+ offset
, 0xFF, pfl
->sector_len
);
386 pflash_update(pfl
, offset
, pfl
->sector_len
);
388 /* Let's wait 1/2 second before sector erase is done */
389 qemu_mod_timer(pfl
->timer
,
390 qemu_get_clock(vm_clock
) + (ticks_per_sec
/ 2));
393 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__
, cmd
);
401 /* Ignore writes during chip erase */
404 /* Ignore writes during sector erase */
407 /* Should never happen */
408 DPRINTF("%s: invalid command state %02x (wc 6)\n",
413 case 7: /* Special value for CFI queries */
414 DPRINTF("%s: invalid write in CFI query mode\n", __func__
);
417 /* Should never happen */
418 DPRINTF("%s: invalid write state (wc 7)\n", __func__
);
427 cpu_register_physical_memory(pfl
->base
, pfl
->total_len
,
428 pfl
->off
| IO_MEM_ROMD
| pfl
->fl_mem
);
441 static uint32_t pflash_readb (void *opaque
, target_phys_addr_t addr
)
443 return pflash_read(opaque
, addr
, 1);
446 static uint32_t pflash_readw (void *opaque
, target_phys_addr_t addr
)
448 pflash_t
*pfl
= opaque
;
450 return pflash_read(pfl
, addr
, 2);
453 static uint32_t pflash_readl (void *opaque
, target_phys_addr_t addr
)
455 pflash_t
*pfl
= opaque
;
457 return pflash_read(pfl
, addr
, 4);
460 static void pflash_writeb (void *opaque
, target_phys_addr_t addr
,
463 pflash_write(opaque
, addr
, value
, 1);
466 static void pflash_writew (void *opaque
, target_phys_addr_t addr
,
469 pflash_t
*pfl
= opaque
;
471 pflash_write(pfl
, addr
, value
, 2);
474 static void pflash_writel (void *opaque
, target_phys_addr_t addr
,
477 pflash_t
*pfl
= opaque
;
479 pflash_write(pfl
, addr
, value
, 4);
482 static CPUWriteMemoryFunc
*pflash_write_ops
[] = {
488 static CPUReadMemoryFunc
*pflash_read_ops
[] = {
494 /* Count trailing zeroes of a 32 bits quantity */
495 static int ctz32 (uint32_t n
)
520 #if 0 /* This is not necessary as n is never 0 */
528 pflash_t
*pflash_cfi02_register(target_phys_addr_t base
, ram_addr_t off
,
529 BlockDriverState
*bs
, uint32_t sector_len
,
530 int nb_blocs
, int width
,
531 uint16_t id0
, uint16_t id1
,
532 uint16_t id2
, uint16_t id3
,
533 uint16_t unlock_addr0
, uint16_t unlock_addr1
)
538 total_len
= sector_len
* nb_blocs
;
539 /* XXX: to be fixed */
541 if (total_len
!= (8 * 1024 * 1024) && total_len
!= (16 * 1024 * 1024) &&
542 total_len
!= (32 * 1024 * 1024) && total_len
!= (64 * 1024 * 1024))
545 pfl
= qemu_mallocz(sizeof(pflash_t
));
548 pfl
->storage
= phys_ram_base
+ off
;
549 pfl
->fl_mem
= cpu_register_io_memory(0, pflash_read_ops
, pflash_write_ops
,
552 cpu_register_physical_memory(base
, total_len
,
553 off
| pfl
->fl_mem
| IO_MEM_ROMD
);
556 /* read the initial flash content */
557 bdrv_read(pfl
->bs
, 0, pfl
->storage
, total_len
>> 9);
559 #if 0 /* XXX: there should be a bit to set up read-only,
560 * the same way the hardware does (with WP pin).
566 pfl
->timer
= qemu_new_timer(vm_clock
, pflash_timer
, pfl
);
568 pfl
->sector_len
= sector_len
;
569 pfl
->total_len
= total_len
;
578 pfl
->unlock_addr
[0] = unlock_addr0
;
579 pfl
->unlock_addr
[1] = unlock_addr1
;
580 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
582 /* Standard "QRY" string */
583 pfl
->cfi_table
[0x10] = 'Q';
584 pfl
->cfi_table
[0x11] = 'R';
585 pfl
->cfi_table
[0x12] = 'Y';
586 /* Command set (AMD/Fujitsu) */
587 pfl
->cfi_table
[0x13] = 0x02;
588 pfl
->cfi_table
[0x14] = 0x00;
589 /* Primary extended table address (none) */
590 pfl
->cfi_table
[0x15] = 0x00;
591 pfl
->cfi_table
[0x16] = 0x00;
592 /* Alternate command set (none) */
593 pfl
->cfi_table
[0x17] = 0x00;
594 pfl
->cfi_table
[0x18] = 0x00;
595 /* Alternate extended table (none) */
596 pfl
->cfi_table
[0x19] = 0x00;
597 pfl
->cfi_table
[0x1A] = 0x00;
599 pfl
->cfi_table
[0x1B] = 0x27;
601 pfl
->cfi_table
[0x1C] = 0x36;
602 /* Vpp min (no Vpp pin) */
603 pfl
->cfi_table
[0x1D] = 0x00;
604 /* Vpp max (no Vpp pin) */
605 pfl
->cfi_table
[0x1E] = 0x00;
607 pfl
->cfi_table
[0x1F] = 0x07;
608 /* Timeout for min size buffer write (16 µs) */
609 pfl
->cfi_table
[0x20] = 0x04;
610 /* Typical timeout for block erase (512 ms) */
611 pfl
->cfi_table
[0x21] = 0x09;
612 /* Typical timeout for full chip erase (4096 ms) */
613 pfl
->cfi_table
[0x22] = 0x0C;
615 pfl
->cfi_table
[0x23] = 0x01;
616 /* Max timeout for buffer write */
617 pfl
->cfi_table
[0x24] = 0x04;
618 /* Max timeout for block erase */
619 pfl
->cfi_table
[0x25] = 0x0A;
620 /* Max timeout for chip erase */
621 pfl
->cfi_table
[0x26] = 0x0D;
623 pfl
->cfi_table
[0x27] = ctz32(total_len
) + 1;
624 /* Flash device interface (8 & 16 bits) */
625 pfl
->cfi_table
[0x28] = 0x02;
626 pfl
->cfi_table
[0x29] = 0x00;
627 /* Max number of bytes in multi-bytes write */
628 /* XXX: disable buffered write as it's not supported */
629 // pfl->cfi_table[0x2A] = 0x05;
630 pfl
->cfi_table
[0x2A] = 0x00;
631 pfl
->cfi_table
[0x2B] = 0x00;
632 /* Number of erase block regions (uniform) */
633 pfl
->cfi_table
[0x2C] = 0x01;
634 /* Erase block region 1 */
635 pfl
->cfi_table
[0x2D] = nb_blocs
- 1;
636 pfl
->cfi_table
[0x2E] = (nb_blocs
- 1) >> 8;
637 pfl
->cfi_table
[0x2F] = sector_len
>> 8;
638 pfl
->cfi_table
[0x30] = sector_len
>> 16;