hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci/pci.h"
  28 #include "pci/pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33 #include "pam.h"
  34
  35 /*
  36  * I440FX chipset data sheet.
  37  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  38  */
  39
  40 typedef struct I440FXState {
  41     PCIHostState parent_obj;
  42 } I440FXState;
  43
  44 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  45 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  46 #define XEN_PIIX_NUM_PIRQS      128ULL
  47 #define PIIX_PIRQC              0x60
  48
  49 typedef struct PIIX3State {
  50     PCIDevice dev;
  51
  52     /*
  53      * bitmap to track pic levels.
  54      * The pic level is the logical OR of all the PCI irqs mapped to it
  55      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  56      *
  57      * PIRQ is mapped to PIC pins, we track it by
  58      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  59      * pic_irq * PIIX_NUM_PIRQS + pirq
  60      */
  61 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  62 #error "unable to encode pic state in 64bit in pic_levels."
  63 #endif
  64     uint64_t pic_levels;
  65
  66     qemu_irq *pic;
  67
  68     /* This member isn't used. Just for save/load compatibility */
  69     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  70 } PIIX3State;
  71
  72 struct PCII440FXState {
  73     PCIDevice dev;
  74     MemoryRegion *system_memory;
  75     MemoryRegion *pci_address_space;
  76     MemoryRegion *ram_memory;
  77     MemoryRegion pci_hole;
  78     MemoryRegion pci_hole_64bit;
  79     PAMMemoryRegion pam_regions[13];
  80     MemoryRegion smram_region;
  81     uint8_t smm_enabled;
  82 };
  83
  84
  85 #define I440FX_PAM      0x59
  86 #define I440FX_PAM_SIZE 7
  87 #define I440FX_SMRAM    0x72
  88
  89 static void piix3_set_irq(void *opaque, int pirq, int level);
  90 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
  91 static void piix3_write_config_xen(PCIDevice *dev,
  92                                uint32_t address, uint32_t val, int len);
  93
  94 /* return the global irq number corresponding to a given device irq
  95    pin. We could also use the bus number to have a more precise
  96    mapping. */
  97 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  98 {
  99     int slot_addend;
 100     slot_addend = (pci_dev->devfn >> 3) - 1;
 101     return (pci_intx + slot_addend) & 3;
 102 }
 103
 104 static void i440fx_update_memory_mappings(PCII440FXState *d)
 105 {
 106     int i;
 107
 108     memory_region_transaction_begin();
 109     for (i = 0; i < 13; i++) {
 110         pam_update(&d->pam_regions[i], i,
 111                    d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
 112     }
 113     smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
 114     memory_region_transaction_commit();
 115 }
 116
 117 static void i440fx_set_smm(int val, void *arg)
 118 {
 119     PCII440FXState *d = arg;
 120
 121     memory_region_transaction_begin();
 122     smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
 123                   &d->smram_region);
 124     memory_region_transaction_commit();
 125 }
 126
 127
 128 static void i440fx_write_config(PCIDevice *dev,
 129                                 uint32_t address, uint32_t val, int len)
 130 {
 131     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 132
 133     /* XXX: implement SMRAM.D_LOCK */
 134     pci_default_write_config(dev, address, val, len);
 135     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 136         range_covers_byte(address, len, I440FX_SMRAM)) {
 137         i440fx_update_memory_mappings(d);
 138     }
 139 }
 140
 141 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 142 {
 143     PCII440FXState *d = opaque;
 144     int ret, i;
 145
 146     ret = pci_device_load(&d->dev, f);
 147     if (ret < 0)
 148         return ret;
 149     i440fx_update_memory_mappings(d);
 150     qemu_get_8s(f, &d->smm_enabled);
 151
 152     if (version_id == 2) {
 153         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 154             qemu_get_be32(f); /* dummy load for compatibility */
 155         }
 156     }
 157
 158     return 0;
 159 }
 160
 161 static int i440fx_post_load(void *opaque, int version_id)
 162 {
 163     PCII440FXState *d = opaque;
 164
 165     i440fx_update_memory_mappings(d);
 166     return 0;
 167 }
 168
 169 static const VMStateDescription vmstate_i440fx = {
 170     .name = "I440FX",
 171     .version_id = 3,
 172     .minimum_version_id = 3,
 173     .minimum_version_id_old = 1,
 174     .load_state_old = i440fx_load_old,
 175     .post_load = i440fx_post_load,
 176     .fields      = (VMStateField []) {
 177         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 178         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 179         VMSTATE_END_OF_LIST()
 180     }
 181 };
 182
 183 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 184 {
 185     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 186
 187     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 188                           "pci-conf-idx", 4);
 189     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 190     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 191
 192     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 193                           "pci-conf-data", 4);
 194     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 195     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 196
 197     return 0;
 198 }
 199
 200 static int i440fx_initfn(PCIDevice *dev)
 201 {
 202     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 203
 204     d->dev.config[I440FX_SMRAM] = 0x02;
 205
 206     cpu_smm_register(&i440fx_set_smm, d);
 207     return 0;
 208 }
 209
 210 static PCIBus *i440fx_common_init(const char *device_name,
 211                                   PCII440FXState **pi440fx_state,
 212                                   int *piix3_devfn,
 213                                   ISABus **isa_bus, qemu_irq *pic,
 214                                   MemoryRegion *address_space_mem,
 215                                   MemoryRegion *address_space_io,
 216                                   ram_addr_t ram_size,
 217                                   hwaddr pci_hole_start,
 218                                   hwaddr pci_hole_size,
 219                                   hwaddr pci_hole64_start,
 220                                   hwaddr pci_hole64_size,
 221                                   MemoryRegion *pci_address_space,
 222                                   MemoryRegion *ram_memory)
 223 {
 224     DeviceState *dev;
 225     PCIBus *b;
 226     PCIDevice *d;
 227     PCIHostState *s;
 228     PIIX3State *piix3;
 229     PCII440FXState *f;
 230     unsigned i;
 231
 232     dev = qdev_create(NULL, "i440FX-pcihost");
 233     s = PCI_HOST_BRIDGE(dev);
 234     s->address_space = address_space_mem;
 235     b = pci_bus_new(dev, NULL, pci_address_space,
 236                     address_space_io, 0);
 237     s->bus = b;
 238     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 239     qdev_init_nofail(dev);
 240
 241     d = pci_create_simple(b, 0, device_name);
 242     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 243     f = *pi440fx_state;
 244     f->system_memory = address_space_mem;
 245     f->pci_address_space = pci_address_space;
 246     f->ram_memory = ram_memory;
 247     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 248                              pci_hole_start, pci_hole_size);
 249     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 250     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 251                              f->pci_address_space,
 252                              pci_hole64_start, pci_hole64_size);
 253     if (pci_hole64_size) {
 254         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 255                                     &f->pci_hole_64bit);
 256     }
 257     memory_region_init_alias(&f->smram_region, "smram-region",
 258                              f->pci_address_space, 0xa0000, 0x20000);
 259     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 260                                         &f->smram_region, 1);
 261     memory_region_set_enabled(&f->smram_region, false);
 262     init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
 263              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 264     for (i = 0; i < 12; ++i) {
 265         init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
 266                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 267                  PAM_EXPAN_SIZE);
 268     }
 269
 270     /* Xen supports additional interrupt routes from the PCI devices to
 271      * the IOAPIC: the four pins of each PCI device on the bus are also
 272      * connected to the IOAPIC directly.
 273      * These additional routes can be discovered through ACPI. */
 274     if (xen_enabled()) {
 275         piix3 = DO_UPCAST(PIIX3State, dev,
 276                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 277         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 278                 piix3, XEN_PIIX_NUM_PIRQS);
 279     } else {
 280         piix3 = DO_UPCAST(PIIX3State, dev,
 281                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 282         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 283                 PIIX_NUM_PIRQS);
 284         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 285     }
 286     piix3->pic = pic;
 287     *isa_bus = DO_UPCAST(ISABus, qbus,
 288                          qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
 289
 290     *piix3_devfn = piix3->dev.devfn;
 291
 292     ram_size = ram_size / 8 / 1024 / 1024;
 293     if (ram_size > 255)
 294         ram_size = 255;
 295     (*pi440fx_state)->dev.config[0x57]=ram_size;
 296
 297     i440fx_update_memory_mappings(f);
 298
 299     return b;
 300 }
 301
 302 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 303                     ISABus **isa_bus, qemu_irq *pic,
 304                     MemoryRegion *address_space_mem,
 305                     MemoryRegion *address_space_io,
 306                     ram_addr_t ram_size,
 307                     hwaddr pci_hole_start,
 308                     hwaddr pci_hole_size,
 309                     hwaddr pci_hole64_start,
 310                     hwaddr pci_hole64_size,
 311                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 312
 313 {
 314     PCIBus *b;
 315
 316     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
 317                            address_space_mem, address_space_io, ram_size,
 318                            pci_hole_start, pci_hole_size,
 319                            pci_hole64_start, pci_hole64_size,
 320                            pci_memory, ram_memory);
 321     return b;
 322 }
 323
 324 /* PIIX3 PCI to ISA bridge */
 325 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 326 {
 327     qemu_set_irq(piix3->pic[pic_irq],
 328                  !!(piix3->pic_levels &
 329                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 330                      (pic_irq * PIIX_NUM_PIRQS))));
 331 }
 332
 333 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 334 {
 335     int pic_irq;
 336     uint64_t mask;
 337
 338     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 339     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 340         return;
 341     }
 342
 343     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 344     piix3->pic_levels &= ~mask;
 345     piix3->pic_levels |= mask * !!level;
 346
 347     piix3_set_irq_pic(piix3, pic_irq);
 348 }
 349
 350 static void piix3_set_irq(void *opaque, int pirq, int level)
 351 {
 352     PIIX3State *piix3 = opaque;
 353     piix3_set_irq_level(piix3, pirq, level);
 354 }
 355
 356 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 357 {
 358     PIIX3State *piix3 = opaque;
 359     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 360     PCIINTxRoute route;
 361
 362     if (irq < PIIX_NUM_PIC_IRQS) {
 363         route.mode = PCI_INTX_ENABLED;
 364         route.irq = irq;
 365     } else {
 366         route.mode = PCI_INTX_DISABLED;
 367         route.irq = -1;
 368     }
 369     return route;
 370 }
 371
 372 /* irq routing is changed. so rebuild bitmap */
 373 static void piix3_update_irq_levels(PIIX3State *piix3)
 374 {
 375     int pirq;
 376
 377     piix3->pic_levels = 0;
 378     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 379         piix3_set_irq_level(piix3, pirq,
 380                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 381     }
 382 }
 383
 384 static void piix3_write_config(PCIDevice *dev,
 385                                uint32_t address, uint32_t val, int len)
 386 {
 387     pci_default_write_config(dev, address, val, len);
 388     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 389         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 390         int pic_irq;
 391
 392         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 393         piix3_update_irq_levels(piix3);
 394         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 395             piix3_set_irq_pic(piix3, pic_irq);
 396         }
 397     }
 398 }
 399
 400 static void piix3_write_config_xen(PCIDevice *dev,
 401                                uint32_t address, uint32_t val, int len)
 402 {
 403     xen_piix_pci_write_config_client(address, val, len);
 404     piix3_write_config(dev, address, val, len);
 405 }
 406
 407 static void piix3_reset(void *opaque)
 408 {
 409     PIIX3State *d = opaque;
 410     uint8_t *pci_conf = d->dev.config;
 411
 412     pci_conf[0x04] = 0x07; // master, memory and I/O
 413     pci_conf[0x05] = 0x00;
 414     pci_conf[0x06] = 0x00;
 415     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 416     pci_conf[0x4c] = 0x4d;
 417     pci_conf[0x4e] = 0x03;
 418     pci_conf[0x4f] = 0x00;
 419     pci_conf[0x60] = 0x80;
 420     pci_conf[0x61] = 0x80;
 421     pci_conf[0x62] = 0x80;
 422     pci_conf[0x63] = 0x80;
 423     pci_conf[0x69] = 0x02;
 424     pci_conf[0x70] = 0x80;
 425     pci_conf[0x76] = 0x0c;
 426     pci_conf[0x77] = 0x0c;
 427     pci_conf[0x78] = 0x02;
 428     pci_conf[0x79] = 0x00;
 429     pci_conf[0x80] = 0x00;
 430     pci_conf[0x82] = 0x00;
 431     pci_conf[0xa0] = 0x08;
 432     pci_conf[0xa2] = 0x00;
 433     pci_conf[0xa3] = 0x00;
 434     pci_conf[0xa4] = 0x00;
 435     pci_conf[0xa5] = 0x00;
 436     pci_conf[0xa6] = 0x00;
 437     pci_conf[0xa7] = 0x00;
 438     pci_conf[0xa8] = 0x0f;
 439     pci_conf[0xaa] = 0x00;
 440     pci_conf[0xab] = 0x00;
 441     pci_conf[0xac] = 0x00;
 442     pci_conf[0xae] = 0x00;
 443
 444     d->pic_levels = 0;
 445 }
 446
 447 static int piix3_post_load(void *opaque, int version_id)
 448 {
 449     PIIX3State *piix3 = opaque;
 450     piix3_update_irq_levels(piix3);
 451     return 0;
 452 }
 453
 454 static void piix3_pre_save(void *opaque)
 455 {
 456     int i;
 457     PIIX3State *piix3 = opaque;
 458
 459     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 460         piix3->pci_irq_levels_vmstate[i] =
 461             pci_bus_get_irq_level(piix3->dev.bus, i);
 462     }
 463 }
 464
 465 static const VMStateDescription vmstate_piix3 = {
 466     .name = "PIIX3",
 467     .version_id = 3,
 468     .minimum_version_id = 2,
 469     .minimum_version_id_old = 2,
 470     .post_load = piix3_post_load,
 471     .pre_save = piix3_pre_save,
 472     .fields      = (VMStateField []) {
 473         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 474         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 475                               PIIX_NUM_PIRQS, 3),
 476         VMSTATE_END_OF_LIST()
 477     }
 478 };
 479
 480 static int piix3_initfn(PCIDevice *dev)
 481 {
 482     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 483
 484     isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
 485     qemu_register_reset(piix3_reset, d);
 486     return 0;
 487 }
 488
 489 static void piix3_class_init(ObjectClass *klass, void *data)
 490 {
 491     DeviceClass *dc = DEVICE_CLASS(klass);
 492     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 493
 494     dc->desc        = "ISA bridge";
 495     dc->vmsd        = &vmstate_piix3;
 496     dc->no_user     = 1,
 497     k->no_hotplug   = 1;
 498     k->init         = piix3_initfn;
 499     k->config_write = piix3_write_config;
 500     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 501     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 502     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 503 }
 504
 505 static const TypeInfo piix3_info = {
 506     .name          = "PIIX3",
 507     .parent        = TYPE_PCI_DEVICE,
 508     .instance_size = sizeof(PIIX3State),
 509     .class_init    = piix3_class_init,
 510 };
 511
 512 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 513 {
 514     DeviceClass *dc = DEVICE_CLASS(klass);
 515     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 516
 517     dc->desc        = "ISA bridge";
 518     dc->vmsd        = &vmstate_piix3;
 519     dc->no_user     = 1;
 520     k->no_hotplug   = 1;
 521     k->init         = piix3_initfn;
 522     k->config_write = piix3_write_config_xen;
 523     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 524     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 525     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 526 };
 527
 528 static const TypeInfo piix3_xen_info = {
 529     .name          = "PIIX3-xen",
 530     .parent        = TYPE_PCI_DEVICE,
 531     .instance_size = sizeof(PIIX3State),
 532     .class_init    = piix3_xen_class_init,
 533 };
 534
 535 static void i440fx_class_init(ObjectClass *klass, void *data)
 536 {
 537     DeviceClass *dc = DEVICE_CLASS(klass);
 538     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 539
 540     k->no_hotplug = 1;
 541     k->init = i440fx_initfn;
 542     k->config_write = i440fx_write_config;
 543     k->vendor_id = PCI_VENDOR_ID_INTEL;
 544     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 545     k->revision = 0x02;
 546     k->class_id = PCI_CLASS_BRIDGE_HOST;
 547     dc->desc = "Host bridge";
 548     dc->no_user = 1;
 549     dc->vmsd = &vmstate_i440fx;
 550 }
 551
 552 static const TypeInfo i440fx_info = {
 553     .name          = "i440FX",
 554     .parent        = TYPE_PCI_DEVICE,
 555     .instance_size = sizeof(PCII440FXState),
 556     .class_init    = i440fx_class_init,
 557 };
 558
 559 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 560 {
 561     DeviceClass *dc = DEVICE_CLASS(klass);
 562     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 563
 564     k->init = i440fx_pcihost_initfn;
 565     dc->fw_name = "pci";
 566     dc->no_user = 1;
 567 }
 568
 569 static const TypeInfo i440fx_pcihost_info = {
 570     .name          = "i440FX-pcihost",
 571     .parent        = TYPE_PCI_HOST_BRIDGE,
 572     .instance_size = sizeof(I440FXState),
 573     .class_init    = i440fx_pcihost_class_init,
 574 };
 575
 576 static void i440fx_register_types(void)
 577 {
 578     type_register_static(&i440fx_info);
 579     type_register_static(&piix3_info);
 580     type_register_static(&piix3_xen_info);
 581     type_register_static(&i440fx_pcihost_info);
 582 }
 583
 584 type_init(i440fx_register_types)