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git.proxmox.com Git - qemu.git/blob - hw/piix_pci.c
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 typedef uint32_t pci_addr_t
;
29 typedef PCIHostState I440FXState
;
31 static void i440fx_addr_writel(void* opaque
, uint32_t addr
, uint32_t val
)
33 I440FXState
*s
= opaque
;
37 static uint32_t i440fx_addr_readl(void* opaque
, uint32_t addr
)
39 I440FXState
*s
= opaque
;
43 static void piix3_set_irq(void *pic
, int irq_num
, int level
);
45 /* return the global irq number corresponding to a given device irq
46 pin. We could also use the bus number to have a more precise
48 static int pci_slot_get_pirq(PCIDevice
*pci_dev
, int irq_num
)
51 slot_addend
= (pci_dev
->devfn
>> 3) - 1;
52 return (irq_num
+ slot_addend
) & 3;
55 static uint32_t isa_page_descs
[384 / 4];
56 static uint8_t smm_enabled
;
58 static void update_pam(PCIDevice
*d
, uint32_t start
, uint32_t end
, int r
)
62 // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
66 cpu_register_physical_memory(start
, end
- start
,
70 /* ROM (XXX: not quite correct) */
71 cpu_register_physical_memory(start
, end
- start
,
76 /* XXX: should distinguish read/write cases */
77 for(addr
= start
; addr
< end
; addr
+= 4096) {
78 cpu_register_physical_memory(addr
, 4096,
79 isa_page_descs
[(addr
- 0xa0000) >> 12]);
85 static void i440fx_update_memory_mappings(PCIDevice
*d
)
90 update_pam(d
, 0xf0000, 0x100000, (d
->config
[0x59] >> 4) & 3);
91 for(i
= 0; i
< 12; i
++) {
92 r
= (d
->config
[(i
>> 1) + 0x5a] >> ((i
& 1) * 4)) & 3;
93 update_pam(d
, 0xc0000 + 0x4000 * i
, 0xc0000 + 0x4000 * (i
+ 1), r
);
95 smram
= d
->config
[0x72];
96 if ((smm_enabled
&& (smram
& 0x08)) || (smram
& 0x40)) {
97 cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
99 for(addr
= 0xa0000; addr
< 0xc0000; addr
+= 4096) {
100 cpu_register_physical_memory(addr
, 4096,
101 isa_page_descs
[(addr
- 0xa0000) >> 12]);
106 void i440fx_set_smm(PCIDevice
*d
, int val
)
109 if (smm_enabled
!= val
) {
111 i440fx_update_memory_mappings(d
);
116 /* XXX: suppress when better memory API. We make the assumption that
117 no device (in particular the VGA) changes the memory mappings in
118 the 0xa0000-0x100000 range */
119 void i440fx_init_memory_mappings(PCIDevice
*d
)
122 for(i
= 0; i
< 96; i
++) {
123 isa_page_descs
[i
] = cpu_get_physical_page_desc(0xa0000 + i
* 0x1000);
127 static void i440fx_write_config(PCIDevice
*d
,
128 uint32_t address
, uint32_t val
, int len
)
130 /* XXX: implement SMRAM.D_LOCK */
131 pci_default_write_config(d
, address
, val
, len
);
132 if ((address
>= 0x59 && address
<= 0x5f) || address
== 0x72)
133 i440fx_update_memory_mappings(d
);
136 static void i440fx_save(QEMUFile
* f
, void *opaque
)
138 PCIDevice
*d
= opaque
;
139 pci_device_save(d
, f
);
140 qemu_put_8s(f
, &smm_enabled
);
143 static int i440fx_load(QEMUFile
* f
, void *opaque
, int version_id
)
145 PCIDevice
*d
= opaque
;
150 ret
= pci_device_load(d
, f
);
153 i440fx_update_memory_mappings(d
);
154 qemu_get_8s(f
, &smm_enabled
);
158 PCIBus
*i440fx_init(PCIDevice
**pi440fx_state
)
164 s
= qemu_mallocz(sizeof(I440FXState
));
165 b
= pci_register_bus(piix3_set_irq
, pci_slot_get_pirq
, NULL
, 0, 4);
168 register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel
, s
);
169 register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl
, s
);
171 register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb
, s
);
172 register_ioport_write(0xcfc, 4, 2, pci_host_data_writew
, s
);
173 register_ioport_write(0xcfc, 4, 4, pci_host_data_writel
, s
);
174 register_ioport_read(0xcfc, 4, 1, pci_host_data_readb
, s
);
175 register_ioport_read(0xcfc, 4, 2, pci_host_data_readw
, s
);
176 register_ioport_read(0xcfc, 4, 4, pci_host_data_readl
, s
);
178 d
= pci_register_device(b
, "i440FX", sizeof(PCIDevice
), 0,
179 NULL
, i440fx_write_config
);
181 d
->config
[0x00] = 0x86; // vendor_id
182 d
->config
[0x01] = 0x80;
183 d
->config
[0x02] = 0x37; // device_id
184 d
->config
[0x03] = 0x12;
185 d
->config
[0x08] = 0x02; // revision
186 d
->config
[0x0a] = 0x00; // class_sub = host2pci
187 d
->config
[0x0b] = 0x06; // class_base = PCI_bridge
188 d
->config
[0x0e] = 0x00; // header_type
190 d
->config
[0x72] = 0x02; /* SMRAM */
192 register_savevm("I440FX", 0, 1, i440fx_save
, i440fx_load
, d
);
197 /* PIIX3 PCI to ISA bridge */
199 static PCIDevice
*piix3_dev
;
201 /* just used for simpler irq handling. */
202 #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
204 static int pci_irq_levels
[4];
206 static void piix3_set_irq(void *pic
, int irq_num
, int level
)
208 int i
, pic_irq
, pic_level
;
210 pci_irq_levels
[irq_num
] = level
;
212 /* now we change the pic irq level according to the piix irq mappings */
214 pic_irq
= piix3_dev
->config
[0x60 + irq_num
];
216 /* The pic level is the logical OR of all the PCI irqs mapped
219 for (i
= 0; i
< 4; i
++) {
220 if (pic_irq
== piix3_dev
->config
[0x60 + i
])
221 pic_level
|= pci_irq_levels
[i
];
223 pic_set_irq(pic_irq
, pic_level
);
227 static void piix3_reset(PCIDevice
*d
)
229 uint8_t *pci_conf
= d
->config
;
231 pci_conf
[0x04] = 0x07; // master, memory and I/O
232 pci_conf
[0x05] = 0x00;
233 pci_conf
[0x06] = 0x00;
234 pci_conf
[0x07] = 0x02; // PCI_status_devsel_medium
235 pci_conf
[0x4c] = 0x4d;
236 pci_conf
[0x4e] = 0x03;
237 pci_conf
[0x4f] = 0x00;
238 pci_conf
[0x60] = 0x80;
239 pci_conf
[0x69] = 0x02;
240 pci_conf
[0x70] = 0x80;
241 pci_conf
[0x76] = 0x0c;
242 pci_conf
[0x77] = 0x0c;
243 pci_conf
[0x78] = 0x02;
244 pci_conf
[0x79] = 0x00;
245 pci_conf
[0x80] = 0x00;
246 pci_conf
[0x82] = 0x00;
247 pci_conf
[0xa0] = 0x08;
248 pci_conf
[0xa0] = 0x08;
249 pci_conf
[0xa2] = 0x00;
250 pci_conf
[0xa3] = 0x00;
251 pci_conf
[0xa4] = 0x00;
252 pci_conf
[0xa5] = 0x00;
253 pci_conf
[0xa6] = 0x00;
254 pci_conf
[0xa7] = 0x00;
255 pci_conf
[0xa8] = 0x0f;
256 pci_conf
[0xaa] = 0x00;
257 pci_conf
[0xab] = 0x00;
258 pci_conf
[0xac] = 0x00;
259 pci_conf
[0xae] = 0x00;
262 static void piix_save(QEMUFile
* f
, void *opaque
)
264 PCIDevice
*d
= opaque
;
265 pci_device_save(d
, f
);
268 static int piix_load(QEMUFile
* f
, void *opaque
, int version_id
)
270 PCIDevice
*d
= opaque
;
273 return pci_device_load(d
, f
);
276 int piix3_init(PCIBus
*bus
)
281 d
= pci_register_device(bus
, "PIIX3", sizeof(PCIDevice
),
283 register_savevm("PIIX3", 0, 2, piix_save
, piix_load
, d
);
286 pci_conf
= d
->config
;
288 pci_conf
[0x00] = 0x86; // Intel
289 pci_conf
[0x01] = 0x80;
290 pci_conf
[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
291 pci_conf
[0x03] = 0x70;
292 pci_conf
[0x0a] = 0x01; // class_sub = PCI_ISA
293 pci_conf
[0x0b] = 0x06; // class_base = PCI_bridge
294 pci_conf
[0x0e] = 0x80; // header_type = PCI_multifunction, generic