hw/ppc/e500.c

   1 /*
   2  * QEMU PowerPC e500-based platforms
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "e500.h"
  20 #include "e500-ccsr.h"
  21 #include "net/net.h"
  22 #include "qemu/config-file.h"
  23 #include "hw/hw.h"
  24 #include "hw/char/serial.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29 #include "kvm_ppc.h"
  30 #include "sysemu/device_tree.h"
  31 #include "hw/ppc/openpic.h"
  32 #include "hw/ppc/ppc.h"
  33 #include "hw/loader.h"
  34 #include "elf.h"
  35 #include "hw/sysbus.h"
  36 #include "exec/address-spaces.h"
  37 #include "qemu/host-utils.h"
  38 #include "hw/pci-host/ppce500.h"
  39
  40 #define EPAPR_MAGIC                (0x45504150)
  41 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  42 #define UIMAGE_LOAD_BASE           0
  43 #define DTC_LOAD_PAD               0x1800000
  44 #define DTC_PAD_MASK               0xFFFFF
  45 #define DTB_MAX_SIZE               (8 * 1024 * 1024)
  46 #define INITRD_LOAD_PAD            0x2000000
  47 #define INITRD_PAD_MASK            0xFFFFFF
  48
  49 #define RAM_SIZES_ALIGN            (64UL << 20)
  50
  51 /* TODO: parameterize */
  52 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  53 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  54 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
  55 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
  56 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
  57 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
  58 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
  59 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
  60                                     MPC8544_PCI_REGS_OFFSET)
  61 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  62 #define MPC8544_PCI_IO             0xE1000000ULL
  63 #define MPC8544_UTIL_OFFSET        0xe0000ULL
  64 #define MPC8544_SPIN_BASE          0xEF000000ULL
  65
  66 struct boot_info
  67 {
  68     uint32_t dt_base;
  69     uint32_t dt_size;
  70     uint32_t entry;
  71 };
  72
  73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
  74                                 int nr_slots, int *len)
  75 {
  76     int i = 0;
  77     int slot;
  78     int pci_irq;
  79     int host_irq;
  80     int last_slot = first_slot + nr_slots;
  81     uint32_t *pci_map;
  82
  83     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
  84     pci_map = g_malloc(*len);
  85
  86     for (slot = first_slot; slot < last_slot; slot++) {
  87         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
  88             pci_map[i++] = cpu_to_be32(slot << 11);
  89             pci_map[i++] = cpu_to_be32(0x0);
  90             pci_map[i++] = cpu_to_be32(0x0);
  91             pci_map[i++] = cpu_to_be32(pci_irq + 1);
  92             pci_map[i++] = cpu_to_be32(mpic);
  93             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
  94             pci_map[i++] = cpu_to_be32(host_irq + 1);
  95             pci_map[i++] = cpu_to_be32(0x1);
  96         }
  97     }
  98
  99     assert((i * sizeof(uint32_t)) == *len);
 100
 101     return pci_map;
 102 }
 103
 104 static void dt_serial_create(void *fdt, unsigned long long offset,
 105                              const char *soc, const char *mpic,
 106                              const char *alias, int idx, bool defcon)
 107 {
 108     char ser[128];
 109
 110     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
 111     qemu_devtree_add_subnode(fdt, ser);
 112     qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
 113     qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
 114     qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
 115     qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
 116     qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
 117     qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2);
 118     qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 119     qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
 120
 121     if (defcon) {
 122         qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 123     }
 124 }
 125
 126 static int ppce500_load_device_tree(CPUPPCState *env,
 127                                     PPCE500Params *params,
 128                                     hwaddr addr,
 129                                     hwaddr initrd_base,
 130                                     hwaddr initrd_size)
 131 {
 132     int ret = -1;
 133     uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
 134     int fdt_size;
 135     void *fdt;
 136     uint8_t hypercall[16];
 137     uint32_t clock_freq = 400000000;
 138     uint32_t tb_freq = 400000000;
 139     int i;
 140     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 141     char soc[128];
 142     char mpic[128];
 143     uint32_t mpic_ph;
 144     uint32_t msi_ph;
 145     char gutil[128];
 146     char pci[128];
 147     char msi[128];
 148     uint32_t *pci_map = NULL;
 149     int len;
 150     uint32_t pci_ranges[14] =
 151         {
 152             0x2000000, 0x0, 0xc0000000,
 153             0x0, 0xc0000000,
 154             0x0, 0x20000000,
 155
 156             0x1000000, 0x0, 0x0,
 157             0x0, 0xe1000000,
 158             0x0, 0x10000,
 159         };
 160     QemuOpts *machine_opts = qemu_get_machine_opts();
 161     const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
 162     const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
 163
 164     if (dtb_file) {
 165         char *filename;
 166         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 167         if (!filename) {
 168             goto out;
 169         }
 170
 171         fdt = load_device_tree(filename, &fdt_size);
 172         if (!fdt) {
 173             goto out;
 174         }
 175         goto done;
 176     }
 177
 178     fdt = create_device_tree(&fdt_size);
 179     if (fdt == NULL) {
 180         goto out;
 181     }
 182
 183     /* Manipulate device tree in memory. */
 184     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 185     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 186
 187     qemu_devtree_add_subnode(fdt, "/memory");
 188     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 189     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 190                          sizeof(mem_reg_property));
 191
 192     qemu_devtree_add_subnode(fdt, "/chosen");
 193     if (initrd_size) {
 194         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 195                                         initrd_base);
 196         if (ret < 0) {
 197             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 198         }
 199
 200         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 201                                         (initrd_base + initrd_size));
 202         if (ret < 0) {
 203             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 204         }
 205     }
 206
 207     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 208                                       params->kernel_cmdline);
 209     if (ret < 0)
 210         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 211
 212     if (kvm_enabled()) {
 213         /* Read out host's frequencies */
 214         clock_freq = kvmppc_get_clockfreq();
 215         tb_freq = kvmppc_get_tbfreq();
 216
 217         /* indicate KVM hypercall interface */
 218         qemu_devtree_add_subnode(fdt, "/hypervisor");
 219         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 220                                     "linux,kvm");
 221         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 222         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 223                              hypercall, sizeof(hypercall));
 224         /* if KVM supports the idle hcall, set property indicating this */
 225         if (kvmppc_get_hasidle(env)) {
 226             qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
 227         }
 228     }
 229
 230     /* Create CPU nodes */
 231     qemu_devtree_add_subnode(fdt, "/cpus");
 232     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 233     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 234
 235     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 236        the first node as boot node and be happy */
 237     for (i = smp_cpus - 1; i >= 0; i--) {
 238         CPUState *cpu;
 239         char cpu_name[128];
 240         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 241
 242         cpu = qemu_get_cpu(i);
 243         if (cpu == NULL) {
 244             continue;
 245         }
 246         env = cpu->env_ptr;
 247
 248         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
 249                  cpu->cpu_index);
 250         qemu_devtree_add_subnode(fdt, cpu_name);
 251         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 252         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 253         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 254         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index);
 255         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 256                                   env->dcache_line_size);
 257         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 258                                   env->icache_line_size);
 259         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 260         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 261         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 262         if (cpu->cpu_index) {
 263             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 264             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 265             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 266                                      cpu_release_addr);
 267         } else {
 268             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 269         }
 270     }
 271
 272     qemu_devtree_add_subnode(fdt, "/aliases");
 273     /* XXX These should go into their respective devices' code */
 274     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 275     qemu_devtree_add_subnode(fdt, soc);
 276     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 277     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 278                          sizeof(compatible_sb));
 279     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 280     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 281     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 282                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 283                                MPC8544_CCSRBAR_SIZE);
 284     /* XXX should contain a reasonable value */
 285     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 286
 287     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
 288     qemu_devtree_add_subnode(fdt, mpic);
 289     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 290     qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
 291     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
 292                                0x40000);
 293     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 294     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
 295     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 296     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 297     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 298     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 299
 300     /*
 301      * We have to generate ser1 first, because Linux takes the first
 302      * device it finds in the dt as serial output device. And we generate
 303      * devices in reverse order to the dt.
 304      */
 305     dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
 306                      soc, mpic, "serial1", 1, false);
 307     dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
 308                      soc, mpic, "serial0", 0, true);
 309
 310     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 311              MPC8544_UTIL_OFFSET);
 312     qemu_devtree_add_subnode(fdt, gutil);
 313     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 314     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
 315     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 316
 317     snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
 318     qemu_devtree_add_subnode(fdt, msi);
 319     qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
 320     qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
 321     msi_ph = qemu_devtree_alloc_phandle(fdt);
 322     qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
 323     qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
 324     qemu_devtree_setprop_cells(fdt, msi, "interrupts",
 325         0xe0, 0x0,
 326         0xe1, 0x0,
 327         0xe2, 0x0,
 328         0xe3, 0x0,
 329         0xe4, 0x0,
 330         0xe5, 0x0,
 331         0xe6, 0x0,
 332         0xe7, 0x0);
 333     qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
 334     qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
 335
 336     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 337     qemu_devtree_add_subnode(fdt, pci);
 338     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 339     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 340     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 341     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 342                                0x0, 0x7);
 343     pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
 344                              params->pci_first_slot, params->pci_nr_slots,
 345                              &len);
 346     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
 347     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 348     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
 349     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 350     for (i = 0; i < 14; i++) {
 351         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 352     }
 353     qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
 354     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 355     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 356                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 357     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 358     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 359     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 360     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 361     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 362
 363     params->fixup_devtree(params, fdt);
 364
 365     if (toplevel_compat) {
 366         qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat,
 367                              strlen(toplevel_compat) + 1);
 368     }
 369
 370 done:
 371     qemu_devtree_dumpdtb(fdt, fdt_size);
 372     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 373     if (ret < 0) {
 374         goto out;
 375     }
 376     g_free(fdt);
 377     ret = fdt_size;
 378
 379 out:
 380     g_free(pci_map);
 381
 382     return ret;
 383 }
 384
 385 /* Create -kernel TLB entries for BookE.  */
 386 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
 387 {
 388     return 63 - clz64(size >> 10);
 389 }
 390
 391 static int booke206_initial_map_tsize(CPUPPCState *env)
 392 {
 393     struct boot_info *bi = env->load_info;
 394     hwaddr dt_end;
 395     int ps;
 396
 397     /* Our initial TLB entry needs to cover everything from 0 to
 398        the device tree top */
 399     dt_end = bi->dt_base + bi->dt_size;
 400     ps = booke206_page_size_to_tlb(dt_end) + 1;
 401     if (ps & 1) {
 402         /* e500v2 can only do even TLB size bits */
 403         ps++;
 404     }
 405     return ps;
 406 }
 407
 408 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
 409 {
 410     int tsize;
 411
 412     tsize = booke206_initial_map_tsize(env);
 413     return (1ULL << 10 << tsize);
 414 }
 415
 416 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 417 {
 418     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 419     hwaddr size;
 420     int ps;
 421
 422     ps = booke206_initial_map_tsize(env);
 423     size = (ps << MAS1_TSIZE_SHIFT);
 424     tlb->mas1 = MAS1_VALID | size;
 425     tlb->mas2 = 0;
 426     tlb->mas7_3 = 0;
 427     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 428
 429     env->tlb_dirty = true;
 430 }
 431
 432 static void ppce500_cpu_reset_sec(void *opaque)
 433 {
 434     PowerPCCPU *cpu = opaque;
 435     CPUState *cs = CPU(cpu);
 436     CPUPPCState *env = &cpu->env;
 437
 438     cpu_reset(cs);
 439
 440     /* Secondary CPU starts in halted state for now. Needs to change when
 441        implementing non-kernel boot. */
 442     cs->halted = 1;
 443     env->exception_index = EXCP_HLT;
 444 }
 445
 446 static void ppce500_cpu_reset(void *opaque)
 447 {
 448     PowerPCCPU *cpu = opaque;
 449     CPUState *cs = CPU(cpu);
 450     CPUPPCState *env = &cpu->env;
 451     struct boot_info *bi = env->load_info;
 452
 453     cpu_reset(cs);
 454
 455     /* Set initial guest state. */
 456     cs->halted = 0;
 457     env->gpr[1] = (16<<20) - 8;
 458     env->gpr[3] = bi->dt_base;
 459     env->gpr[4] = 0;
 460     env->gpr[5] = 0;
 461     env->gpr[6] = EPAPR_MAGIC;
 462     env->gpr[7] = mmubooke_initial_mapsize(env);
 463     env->gpr[8] = 0;
 464     env->gpr[9] = 0;
 465     env->nip = bi->entry;
 466     mmubooke_create_initial_mapping(env);
 467 }
 468
 469 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
 470                                            qemu_irq **irqs)
 471 {
 472     DeviceState *dev;
 473     SysBusDevice *s;
 474     int i, j, k;
 475
 476     dev = qdev_create(NULL, TYPE_OPENPIC);
 477     qdev_prop_set_uint32(dev, "model", params->mpic_version);
 478     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
 479
 480     qdev_init_nofail(dev);
 481     s = SYS_BUS_DEVICE(dev);
 482
 483     k = 0;
 484     for (i = 0; i < smp_cpus; i++) {
 485         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
 486             sysbus_connect_irq(s, k++, irqs[i][j]);
 487         }
 488     }
 489
 490     return dev;
 491 }
 492
 493 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
 494                                           qemu_irq **irqs)
 495 {
 496     DeviceState *dev;
 497     CPUState *cs;
 498     int r;
 499
 500     dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
 501     qdev_prop_set_uint32(dev, "model", params->mpic_version);
 502
 503     r = qdev_init(dev);
 504     if (r) {
 505         return NULL;
 506     }
 507
 508     for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) {
 509         if (kvm_openpic_connect_vcpu(dev, cs)) {
 510             fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
 511                     __func__);
 512             abort();
 513         }
 514     }
 515
 516     return dev;
 517 }
 518
 519 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr,
 520                                    qemu_irq **irqs)
 521 {
 522     qemu_irq *mpic;
 523     DeviceState *dev = NULL;
 524     SysBusDevice *s;
 525     int i;
 526
 527     mpic = g_new(qemu_irq, 256);
 528
 529     if (kvm_enabled()) {
 530         QemuOpts *machine_opts = qemu_get_machine_opts();
 531         bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
 532                                                 "kernel_irqchip", true);
 533         bool irqchip_required = qemu_opt_get_bool(machine_opts,
 534                                                   "kernel_irqchip", false);
 535
 536         if (irqchip_allowed) {
 537             dev = ppce500_init_mpic_kvm(params, irqs);
 538         }
 539
 540         if (irqchip_required && !dev) {
 541             fprintf(stderr, "%s: irqchip requested but unavailable\n",
 542                     __func__);
 543             abort();
 544         }
 545     }
 546
 547     if (!dev) {
 548         dev = ppce500_init_mpic_qemu(params, irqs);
 549     }
 550
 551     for (i = 0; i < 256; i++) {
 552         mpic[i] = qdev_get_gpio_in(dev, i);
 553     }
 554
 555     s = SYS_BUS_DEVICE(dev);
 556     memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
 557                                 s->mmio[0].memory);
 558
 559     return mpic;
 560 }
 561
 562 void ppce500_init(PPCE500Params *params)
 563 {
 564     MemoryRegion *address_space_mem = get_system_memory();
 565     MemoryRegion *ram = g_new(MemoryRegion, 1);
 566     PCIBus *pci_bus;
 567     CPUPPCState *env = NULL;
 568     uint64_t elf_entry;
 569     uint64_t elf_lowaddr;
 570     hwaddr entry=0;
 571     hwaddr loadaddr=UIMAGE_LOAD_BASE;
 572     target_long kernel_size=0;
 573     target_ulong dt_base = 0;
 574     target_ulong initrd_base = 0;
 575     target_long initrd_size = 0;
 576     target_ulong cur_base = 0;
 577     int i;
 578     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 579     qemu_irq **irqs, *mpic;
 580     DeviceState *dev;
 581     CPUPPCState *firstenv = NULL;
 582     MemoryRegion *ccsr_addr_space;
 583     SysBusDevice *s;
 584     PPCE500CCSRState *ccsr;
 585
 586     /* Setup CPUs */
 587     if (params->cpu_model == NULL) {
 588         params->cpu_model = "e500v2_v30";
 589     }
 590
 591     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 592     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 593     for (i = 0; i < smp_cpus; i++) {
 594         PowerPCCPU *cpu;
 595         CPUState *cs;
 596         qemu_irq *input;
 597
 598         cpu = cpu_ppc_init(params->cpu_model);
 599         if (cpu == NULL) {
 600             fprintf(stderr, "Unable to initialize CPU!\n");
 601             exit(1);
 602         }
 603         env = &cpu->env;
 604         cs = CPU(cpu);
 605
 606         if (!firstenv) {
 607             firstenv = env;
 608         }
 609
 610         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 611         input = (qemu_irq *)env->irq_inputs;
 612         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 613         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 614         env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i;
 615         env->mpic_iack = MPC8544_CCSRBAR_BASE +
 616                          MPC8544_MPIC_REGS_OFFSET + 0xa0;
 617
 618         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
 619
 620         /* Register reset handler */
 621         if (!i) {
 622             /* Primary CPU */
 623             struct boot_info *boot_info;
 624             boot_info = g_malloc0(sizeof(struct boot_info));
 625             qemu_register_reset(ppce500_cpu_reset, cpu);
 626             env->load_info = boot_info;
 627         } else {
 628             /* Secondary CPUs */
 629             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
 630         }
 631     }
 632
 633     env = firstenv;
 634
 635     /* Fixup Memory size on a alignment boundary */
 636     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 637     params->ram_size = ram_size;
 638
 639     /* Register Memory */
 640     memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size);
 641     vmstate_register_ram_global(ram);
 642     memory_region_add_subregion(address_space_mem, 0, ram);
 643
 644     dev = qdev_create(NULL, "e500-ccsr");
 645     object_property_add_child(qdev_get_machine(), "e500-ccsr",
 646                               OBJECT(dev), NULL);
 647     qdev_init_nofail(dev);
 648     ccsr = CCSR(dev);
 649     ccsr_addr_space = &ccsr->ccsr_space;
 650     memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
 651                                 ccsr_addr_space);
 652
 653     mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
 654
 655     /* Serial */
 656     if (serial_hds[0]) {
 657         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
 658                        0, mpic[42], 399193,
 659                        serial_hds[0], DEVICE_BIG_ENDIAN);
 660     }
 661
 662     if (serial_hds[1]) {
 663         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
 664                        0, mpic[42], 399193,
 665                        serial_hds[1], DEVICE_BIG_ENDIAN);
 666     }
 667
 668     /* General Utility device */
 669     dev = qdev_create(NULL, "mpc8544-guts");
 670     qdev_init_nofail(dev);
 671     s = SYS_BUS_DEVICE(dev);
 672     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
 673                                 sysbus_mmio_get_region(s, 0));
 674
 675     /* PCI */
 676     dev = qdev_create(NULL, "e500-pcihost");
 677     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
 678     qdev_init_nofail(dev);
 679     s = SYS_BUS_DEVICE(dev);
 680     sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
 681     sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
 682     sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
 683     sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
 684     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
 685                                 sysbus_mmio_get_region(s, 0));
 686
 687     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 688     if (!pci_bus)
 689         printf("couldn't create PCI controller!\n");
 690
 691     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
 692
 693     if (pci_bus) {
 694         /* Register network interfaces. */
 695         for (i = 0; i < nb_nics; i++) {
 696             pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);
 697         }
 698     }
 699
 700     /* Register spinning region */
 701     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 702
 703     /* Load kernel. */
 704     if (params->kernel_filename) {
 705         kernel_size = load_uimage(params->kernel_filename, &entry,
 706                                   &loadaddr, NULL);
 707         if (kernel_size < 0) {
 708             kernel_size = load_elf(params->kernel_filename, NULL, NULL,
 709                                    &elf_entry, &elf_lowaddr, NULL, 1,
 710                                    ELF_MACHINE, 0);
 711             entry = elf_entry;
 712             loadaddr = elf_lowaddr;
 713         }
 714         /* XXX try again as binary */
 715         if (kernel_size < 0) {
 716             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 717                     params->kernel_filename);
 718             exit(1);
 719         }
 720
 721         cur_base = loadaddr + kernel_size;
 722
 723         /* Reserve space for dtb */
 724         dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 725         cur_base += DTB_MAX_SIZE;
 726     }
 727
 728     /* Load initrd. */
 729     if (params->initrd_filename) {
 730         initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 731         initrd_size = load_image_targphys(params->initrd_filename, initrd_base,
 732                                           ram_size - initrd_base);
 733
 734         if (initrd_size < 0) {
 735             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 736                     params->initrd_filename);
 737             exit(1);
 738         }
 739
 740         cur_base = initrd_base + initrd_size;
 741     }
 742
 743     /* If we're loading a kernel directly, we must load the device tree too. */
 744     if (params->kernel_filename) {
 745         struct boot_info *boot_info;
 746         int dt_size;
 747
 748         dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base,
 749                                            initrd_size);
 750         if (dt_size < 0) {
 751             fprintf(stderr, "couldn't load device tree\n");
 752             exit(1);
 753         }
 754         assert(dt_size < DTB_MAX_SIZE);
 755
 756         boot_info = env->load_info;
 757         boot_info->entry = entry;
 758         boot_info->dt_base = dt_base;
 759         boot_info->dt_size = dt_size;
 760     }
 761
 762     if (kvm_enabled()) {
 763         kvmppc_init();
 764     }
 765 }
 766
 767 static int e500_ccsr_initfn(SysBusDevice *dev)
 768 {
 769     PPCE500CCSRState *ccsr;
 770
 771     ccsr = CCSR(dev);
 772     memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr",
 773                        MPC8544_CCSRBAR_SIZE);
 774     return 0;
 775 }
 776
 777 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
 778 {
 779     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 780     k->init = e500_ccsr_initfn;
 781 }
 782
 783 static const TypeInfo e500_ccsr_info = {
 784     .name          = TYPE_CCSR,
 785     .parent        = TYPE_SYS_BUS_DEVICE,
 786     .instance_size = sizeof(PPCE500CCSRState),
 787     .class_init    = e500_ccsr_class_init,
 788 };
 789
 790 static void e500_register_types(void)
 791 {
 792     type_register_static(&e500_ccsr_info);
 793 }
 794
 795 type_init(e500_register_types)