hw/ppc/e500.c

   1 /*
   2  * QEMU PowerPC e500-based platforms
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "e500.h"
  20 #include "e500-ccsr.h"
  21 #include "net/net.h"
  22 #include "qemu/config-file.h"
  23 #include "hw/hw.h"
  24 #include "hw/serial.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29 #include "kvm_ppc.h"
  30 #include "sysemu/device_tree.h"
  31 #include "hw/openpic.h"
  32 #include "hw/ppc.h"
  33 #include "hw/loader.h"
  34 #include "elf.h"
  35 #include "hw/sysbus.h"
  36 #include "exec/address-spaces.h"
  37 #include "qemu/host-utils.h"
  38 #include "hw/ppce500_pci.h"
  39
  40 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  41 #define UIMAGE_LOAD_BASE           0
  42 #define DTC_LOAD_PAD               0x1800000
  43 #define DTC_PAD_MASK               0xFFFFF
  44 #define INITRD_LOAD_PAD            0x2000000
  45 #define INITRD_PAD_MASK            0xFFFFFF
  46
  47 #define RAM_SIZES_ALIGN            (64UL << 20)
  48
  49 /* TODO: parameterize */
  50 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  51 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  52 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
  53 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
  54 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
  55 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
  56 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
  57 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
  58                                     MPC8544_PCI_REGS_OFFSET)
  59 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  60 #define MPC8544_PCI_IO             0xE1000000ULL
  61 #define MPC8544_UTIL_OFFSET        0xe0000ULL
  62 #define MPC8544_SPIN_BASE          0xEF000000ULL
  63
  64 struct boot_info
  65 {
  66     uint32_t dt_base;
  67     uint32_t dt_size;
  68     uint32_t entry;
  69 };
  70
  71 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
  72                                 int nr_slots, int *len)
  73 {
  74     int i = 0;
  75     int slot;
  76     int pci_irq;
  77     int host_irq;
  78     int last_slot = first_slot + nr_slots;
  79     uint32_t *pci_map;
  80
  81     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
  82     pci_map = g_malloc(*len);
  83
  84     for (slot = first_slot; slot < last_slot; slot++) {
  85         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
  86             pci_map[i++] = cpu_to_be32(slot << 11);
  87             pci_map[i++] = cpu_to_be32(0x0);
  88             pci_map[i++] = cpu_to_be32(0x0);
  89             pci_map[i++] = cpu_to_be32(pci_irq + 1);
  90             pci_map[i++] = cpu_to_be32(mpic);
  91             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
  92             pci_map[i++] = cpu_to_be32(host_irq + 1);
  93             pci_map[i++] = cpu_to_be32(0x1);
  94         }
  95     }
  96
  97     assert((i * sizeof(uint32_t)) == *len);
  98
  99     return pci_map;
 100 }
 101
 102 static void dt_serial_create(void *fdt, unsigned long long offset,
 103                              const char *soc, const char *mpic,
 104                              const char *alias, int idx, bool defcon)
 105 {
 106     char ser[128];
 107
 108     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
 109     qemu_devtree_add_subnode(fdt, ser);
 110     qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
 111     qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
 112     qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
 113     qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
 114     qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
 115     qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2);
 116     qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 117     qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
 118
 119     if (defcon) {
 120         qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 121     }
 122 }
 123
 124 static int ppce500_load_device_tree(CPUPPCState *env,
 125                                     PPCE500Params *params,
 126                                     hwaddr addr,
 127                                     hwaddr initrd_base,
 128                                     hwaddr initrd_size)
 129 {
 130     int ret = -1;
 131     uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
 132     int fdt_size;
 133     void *fdt;
 134     uint8_t hypercall[16];
 135     uint32_t clock_freq = 400000000;
 136     uint32_t tb_freq = 400000000;
 137     int i;
 138     const char *toplevel_compat = NULL; /* user override */
 139     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 140     char soc[128];
 141     char mpic[128];
 142     uint32_t mpic_ph;
 143     uint32_t msi_ph;
 144     char gutil[128];
 145     char pci[128];
 146     char msi[128];
 147     uint32_t *pci_map = NULL;
 148     int len;
 149     uint32_t pci_ranges[14] =
 150         {
 151             0x2000000, 0x0, 0xc0000000,
 152             0x0, 0xc0000000,
 153             0x0, 0x20000000,
 154
 155             0x1000000, 0x0, 0x0,
 156             0x0, 0xe1000000,
 157             0x0, 0x10000,
 158         };
 159     QemuOpts *machine_opts;
 160     const char *dtb_file = NULL;
 161
 162     machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
 163     if (machine_opts) {
 164         dtb_file = qemu_opt_get(machine_opts, "dtb");
 165         toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
 166     }
 167
 168     if (dtb_file) {
 169         char *filename;
 170         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 171         if (!filename) {
 172             goto out;
 173         }
 174
 175         fdt = load_device_tree(filename, &fdt_size);
 176         if (!fdt) {
 177             goto out;
 178         }
 179         goto done;
 180     }
 181
 182     fdt = create_device_tree(&fdt_size);
 183     if (fdt == NULL) {
 184         goto out;
 185     }
 186
 187     /* Manipulate device tree in memory. */
 188     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 189     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 190
 191     qemu_devtree_add_subnode(fdt, "/memory");
 192     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 193     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 194                          sizeof(mem_reg_property));
 195
 196     qemu_devtree_add_subnode(fdt, "/chosen");
 197     if (initrd_size) {
 198         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 199                                         initrd_base);
 200         if (ret < 0) {
 201             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 202         }
 203
 204         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 205                                         (initrd_base + initrd_size));
 206         if (ret < 0) {
 207             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 208         }
 209     }
 210
 211     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 212                                       params->kernel_cmdline);
 213     if (ret < 0)
 214         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 215
 216     if (kvm_enabled()) {
 217         /* Read out host's frequencies */
 218         clock_freq = kvmppc_get_clockfreq();
 219         tb_freq = kvmppc_get_tbfreq();
 220
 221         /* indicate KVM hypercall interface */
 222         qemu_devtree_add_subnode(fdt, "/hypervisor");
 223         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 224                                     "linux,kvm");
 225         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 226         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 227                              hypercall, sizeof(hypercall));
 228     }
 229
 230     /* Create CPU nodes */
 231     qemu_devtree_add_subnode(fdt, "/cpus");
 232     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 233     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 234
 235     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 236        the first node as boot node and be happy */
 237     for (i = smp_cpus - 1; i >= 0; i--) {
 238         char cpu_name[128];
 239         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 240
 241         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 242             if (env->cpu_index == i) {
 243                 break;
 244             }
 245         }
 246
 247         if (!env) {
 248             continue;
 249         }
 250
 251         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
 252         qemu_devtree_add_subnode(fdt, cpu_name);
 253         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 254         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 255         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 256         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
 257         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 258                                   env->dcache_line_size);
 259         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 260                                   env->icache_line_size);
 261         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 262         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 263         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 264         if (env->cpu_index) {
 265             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 266             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 267             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 268                                      cpu_release_addr);
 269         } else {
 270             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 271         }
 272     }
 273
 274     qemu_devtree_add_subnode(fdt, "/aliases");
 275     /* XXX These should go into their respective devices' code */
 276     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 277     qemu_devtree_add_subnode(fdt, soc);
 278     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 279     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 280                          sizeof(compatible_sb));
 281     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 282     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 283     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 284                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 285                                MPC8544_CCSRBAR_SIZE);
 286     /* XXX should contain a reasonable value */
 287     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 288
 289     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
 290     qemu_devtree_add_subnode(fdt, mpic);
 291     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 292     qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
 293     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
 294                                0x40000);
 295     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 296     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
 297     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 298     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 299     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 300     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 301
 302     /*
 303      * We have to generate ser1 first, because Linux takes the first
 304      * device it finds in the dt as serial output device. And we generate
 305      * devices in reverse order to the dt.
 306      */
 307     dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
 308                      soc, mpic, "serial1", 1, false);
 309     dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
 310                      soc, mpic, "serial0", 0, true);
 311
 312     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 313              MPC8544_UTIL_OFFSET);
 314     qemu_devtree_add_subnode(fdt, gutil);
 315     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 316     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
 317     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 318
 319     snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
 320     qemu_devtree_add_subnode(fdt, msi);
 321     qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
 322     qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
 323     msi_ph = qemu_devtree_alloc_phandle(fdt);
 324     qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
 325     qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
 326     qemu_devtree_setprop_cells(fdt, msi, "interrupts",
 327         0xe0, 0x0,
 328         0xe1, 0x0,
 329         0xe2, 0x0,
 330         0xe3, 0x0,
 331         0xe4, 0x0,
 332         0xe5, 0x0,
 333         0xe6, 0x0,
 334         0xe7, 0x0);
 335     qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
 336     qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
 337
 338     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 339     qemu_devtree_add_subnode(fdt, pci);
 340     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 341     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 342     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 343     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 344                                0x0, 0x7);
 345     pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
 346                              params->pci_first_slot, params->pci_nr_slots,
 347                              &len);
 348     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
 349     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 350     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
 351     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 352     for (i = 0; i < 14; i++) {
 353         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 354     }
 355     qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
 356     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 357     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 358                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 359     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 360     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 361     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 362     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 363     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 364
 365     params->fixup_devtree(params, fdt);
 366
 367     if (toplevel_compat) {
 368         qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat,
 369                              strlen(toplevel_compat) + 1);
 370     }
 371
 372 done:
 373     qemu_devtree_dumpdtb(fdt, fdt_size);
 374     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 375     if (ret < 0) {
 376         goto out;
 377     }
 378     g_free(fdt);
 379     ret = fdt_size;
 380
 381 out:
 382     g_free(pci_map);
 383
 384     return ret;
 385 }
 386
 387 /* Create -kernel TLB entries for BookE.  */
 388 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
 389 {
 390     return 63 - clz64(size >> 10);
 391 }
 392
 393 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 394 {
 395     struct boot_info *bi = env->load_info;
 396     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 397     hwaddr size, dt_end;
 398     int ps;
 399
 400     /* Our initial TLB entry needs to cover everything from 0 to
 401        the device tree top */
 402     dt_end = bi->dt_base + bi->dt_size;
 403     ps = booke206_page_size_to_tlb(dt_end) + 1;
 404     if (ps & 1) {
 405         /* e500v2 can only do even TLB size bits */
 406         ps++;
 407     }
 408     size = (ps << MAS1_TSIZE_SHIFT);
 409     tlb->mas1 = MAS1_VALID | size;
 410     tlb->mas2 = 0;
 411     tlb->mas7_3 = 0;
 412     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 413
 414     env->tlb_dirty = true;
 415 }
 416
 417 static void ppce500_cpu_reset_sec(void *opaque)
 418 {
 419     PowerPCCPU *cpu = opaque;
 420     CPUPPCState *env = &cpu->env;
 421
 422     cpu_reset(CPU(cpu));
 423
 424     /* Secondary CPU starts in halted state for now. Needs to change when
 425        implementing non-kernel boot. */
 426     env->halted = 1;
 427     env->exception_index = EXCP_HLT;
 428 }
 429
 430 static void ppce500_cpu_reset(void *opaque)
 431 {
 432     PowerPCCPU *cpu = opaque;
 433     CPUPPCState *env = &cpu->env;
 434     struct boot_info *bi = env->load_info;
 435
 436     cpu_reset(CPU(cpu));
 437
 438     /* Set initial guest state. */
 439     env->halted = 0;
 440     env->gpr[1] = (16<<20) - 8;
 441     env->gpr[3] = bi->dt_base;
 442     env->nip = bi->entry;
 443     mmubooke_create_initial_mapping(env);
 444 }
 445
 446 void ppce500_init(PPCE500Params *params)
 447 {
 448     MemoryRegion *address_space_mem = get_system_memory();
 449     MemoryRegion *ram = g_new(MemoryRegion, 1);
 450     PCIBus *pci_bus;
 451     CPUPPCState *env = NULL;
 452     uint64_t elf_entry;
 453     uint64_t elf_lowaddr;
 454     hwaddr entry=0;
 455     hwaddr loadaddr=UIMAGE_LOAD_BASE;
 456     target_long kernel_size=0;
 457     target_ulong dt_base = 0;
 458     target_ulong initrd_base = 0;
 459     target_long initrd_size=0;
 460     int i = 0, j, k;
 461     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 462     qemu_irq **irqs, *mpic;
 463     DeviceState *dev;
 464     CPUPPCState *firstenv = NULL;
 465     MemoryRegion *ccsr_addr_space;
 466     SysBusDevice *s;
 467     PPCE500CCSRState *ccsr;
 468
 469     /* Setup CPUs */
 470     if (params->cpu_model == NULL) {
 471         params->cpu_model = "e500v2_v30";
 472     }
 473
 474     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 475     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 476     for (i = 0; i < smp_cpus; i++) {
 477         PowerPCCPU *cpu;
 478         qemu_irq *input;
 479
 480         cpu = cpu_ppc_init(params->cpu_model);
 481         if (cpu == NULL) {
 482             fprintf(stderr, "Unable to initialize CPU!\n");
 483             exit(1);
 484         }
 485         env = &cpu->env;
 486
 487         if (!firstenv) {
 488             firstenv = env;
 489         }
 490
 491         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 492         input = (qemu_irq *)env->irq_inputs;
 493         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 494         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 495         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 496         env->mpic_cpu_base = MPC8544_CCSRBAR_BASE +
 497                               MPC8544_MPIC_REGS_OFFSET + 0x20000;
 498
 499         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
 500
 501         /* Register reset handler */
 502         if (!i) {
 503             /* Primary CPU */
 504             struct boot_info *boot_info;
 505             boot_info = g_malloc0(sizeof(struct boot_info));
 506             qemu_register_reset(ppce500_cpu_reset, cpu);
 507             env->load_info = boot_info;
 508         } else {
 509             /* Secondary CPUs */
 510             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
 511         }
 512     }
 513
 514     env = firstenv;
 515
 516     /* Fixup Memory size on a alignment boundary */
 517     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 518
 519     /* Register Memory */
 520     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 521     vmstate_register_ram_global(ram);
 522     memory_region_add_subregion(address_space_mem, 0, ram);
 523
 524     dev = qdev_create(NULL, "e500-ccsr");
 525     object_property_add_child(qdev_get_machine(), "e500-ccsr",
 526                               OBJECT(dev), NULL);
 527     qdev_init_nofail(dev);
 528     ccsr = CCSR(dev);
 529     ccsr_addr_space = &ccsr->ccsr_space;
 530     memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
 531                                 ccsr_addr_space);
 532
 533     /* MPIC */
 534     mpic = g_new(qemu_irq, 256);
 535     dev = qdev_create(NULL, "openpic");
 536     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
 537     qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
 538     qdev_init_nofail(dev);
 539     s = sysbus_from_qdev(dev);
 540
 541     k = 0;
 542     for (i = 0; i < smp_cpus; i++) {
 543         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
 544             sysbus_connect_irq(s, k++, irqs[i][j]);
 545         }
 546     }
 547
 548     for (i = 0; i < 256; i++) {
 549         mpic[i] = qdev_get_gpio_in(dev, i);
 550     }
 551
 552     memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
 553                                 s->mmio[0].memory);
 554
 555     /* Serial */
 556     if (serial_hds[0]) {
 557         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
 558                        0, mpic[42], 399193,
 559                        serial_hds[0], DEVICE_BIG_ENDIAN);
 560     }
 561
 562     if (serial_hds[1]) {
 563         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
 564                        0, mpic[42], 399193,
 565                        serial_hds[1], DEVICE_BIG_ENDIAN);
 566     }
 567
 568     /* General Utility device */
 569     dev = qdev_create(NULL, "mpc8544-guts");
 570     qdev_init_nofail(dev);
 571     s = SYS_BUS_DEVICE(dev);
 572     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
 573                                 sysbus_mmio_get_region(s, 0));
 574
 575     /* PCI */
 576     dev = qdev_create(NULL, "e500-pcihost");
 577     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
 578     qdev_init_nofail(dev);
 579     s = SYS_BUS_DEVICE(dev);
 580     sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
 581     sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
 582     sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
 583     sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
 584     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
 585                                 sysbus_mmio_get_region(s, 0));
 586
 587     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 588     if (!pci_bus)
 589         printf("couldn't create PCI controller!\n");
 590
 591     sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO);
 592
 593     if (pci_bus) {
 594         /* Register network interfaces. */
 595         for (i = 0; i < nb_nics; i++) {
 596             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 597         }
 598     }
 599
 600     /* Register spinning region */
 601     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 602
 603     /* Load kernel. */
 604     if (params->kernel_filename) {
 605         kernel_size = load_uimage(params->kernel_filename, &entry,
 606                                   &loadaddr, NULL);
 607         if (kernel_size < 0) {
 608             kernel_size = load_elf(params->kernel_filename, NULL, NULL,
 609                                    &elf_entry, &elf_lowaddr, NULL, 1,
 610                                    ELF_MACHINE, 0);
 611             entry = elf_entry;
 612             loadaddr = elf_lowaddr;
 613         }
 614         /* XXX try again as binary */
 615         if (kernel_size < 0) {
 616             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 617                     params->kernel_filename);
 618             exit(1);
 619         }
 620     }
 621
 622     /* Load initrd. */
 623     if (params->initrd_filename) {
 624         initrd_base = (loadaddr + kernel_size + INITRD_LOAD_PAD) &
 625             ~INITRD_PAD_MASK;
 626         initrd_size = load_image_targphys(params->initrd_filename, initrd_base,
 627                                           ram_size - initrd_base);
 628
 629         if (initrd_size < 0) {
 630             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 631                     params->initrd_filename);
 632             exit(1);
 633         }
 634     }
 635
 636     /* If we're loading a kernel directly, we must load the device tree too. */
 637     if (params->kernel_filename) {
 638         struct boot_info *boot_info;
 639         int dt_size;
 640
 641         dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 642         dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base,
 643                                            initrd_size);
 644         if (dt_size < 0) {
 645             fprintf(stderr, "couldn't load device tree\n");
 646             exit(1);
 647         }
 648
 649         boot_info = env->load_info;
 650         boot_info->entry = entry;
 651         boot_info->dt_base = dt_base;
 652         boot_info->dt_size = dt_size;
 653     }
 654
 655     if (kvm_enabled()) {
 656         kvmppc_init();
 657     }
 658 }
 659
 660 static int e500_ccsr_initfn(SysBusDevice *dev)
 661 {
 662     PPCE500CCSRState *ccsr;
 663
 664     ccsr = CCSR(dev);
 665     memory_region_init(&ccsr->ccsr_space, "e500-ccsr",
 666                        MPC8544_CCSRBAR_SIZE);
 667     return 0;
 668 }
 669
 670 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
 671 {
 672     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 673     k->init = e500_ccsr_initfn;
 674 }
 675
 676 static const TypeInfo e500_ccsr_info = {
 677     .name          = TYPE_CCSR,
 678     .parent        = TYPE_SYS_BUS_DEVICE,
 679     .instance_size = sizeof(PPCE500CCSRState),
 680     .class_init    = e500_ccsr_class_init,
 681 };
 682
 683 static void e500_register_types(void)
 684 {
 685     type_register_static(&e500_ccsr_info);
 686 }
 687
 688 type_init(e500_register_types)