hw/ppc/e500.c

   1 /*
   2  * QEMU PowerPC e500-based platforms
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "e500.h"
  20 #include "e500-ccsr.h"
  21 #include "net/net.h"
  22 #include "qemu/config-file.h"
  23 #include "hw/hw.h"
  24 #include "hw/serial.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/sysemu.h"
  28 #include "sysemu/kvm.h"
  29 #include "kvm_ppc.h"
  30 #include "sysemu/device_tree.h"
  31 #include "hw/openpic.h"
  32 #include "hw/ppc.h"
  33 #include "hw/loader.h"
  34 #include "elf.h"
  35 #include "hw/sysbus.h"
  36 #include "exec/address-spaces.h"
  37 #include "qemu/host-utils.h"
  38 #include "hw/ppce500_pci.h"
  39
  40 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  41 #define UIMAGE_LOAD_BASE           0
  42 #define DTC_LOAD_PAD               0x1800000
  43 #define DTC_PAD_MASK               0xFFFFF
  44 #define INITRD_LOAD_PAD            0x2000000
  45 #define INITRD_PAD_MASK            0xFFFFFF
  46
  47 #define RAM_SIZES_ALIGN            (64UL << 20)
  48
  49 /* TODO: parameterize */
  50 #define MPC8544_CCSRBAR_BASE       0xE0000000ULL
  51 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
  52 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
  53 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
  54 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
  55 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
  56 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
  57 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + \
  58                                     MPC8544_PCI_REGS_OFFSET)
  59 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
  60 #define MPC8544_PCI_IO             0xE1000000ULL
  61 #define MPC8544_UTIL_OFFSET        0xe0000ULL
  62 #define MPC8544_SPIN_BASE          0xEF000000ULL
  63
  64 struct boot_info
  65 {
  66     uint32_t dt_base;
  67     uint32_t dt_size;
  68     uint32_t entry;
  69 };
  70
  71 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
  72                                 int nr_slots, int *len)
  73 {
  74     int i = 0;
  75     int slot;
  76     int pci_irq;
  77     int host_irq;
  78     int last_slot = first_slot + nr_slots;
  79     uint32_t *pci_map;
  80
  81     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
  82     pci_map = g_malloc(*len);
  83
  84     for (slot = first_slot; slot < last_slot; slot++) {
  85         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
  86             pci_map[i++] = cpu_to_be32(slot << 11);
  87             pci_map[i++] = cpu_to_be32(0x0);
  88             pci_map[i++] = cpu_to_be32(0x0);
  89             pci_map[i++] = cpu_to_be32(pci_irq + 1);
  90             pci_map[i++] = cpu_to_be32(mpic);
  91             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
  92             pci_map[i++] = cpu_to_be32(host_irq + 1);
  93             pci_map[i++] = cpu_to_be32(0x1);
  94         }
  95     }
  96
  97     assert((i * sizeof(uint32_t)) == *len);
  98
  99     return pci_map;
 100 }
 101
 102 static void dt_serial_create(void *fdt, unsigned long long offset,
 103                              const char *soc, const char *mpic,
 104                              const char *alias, int idx, bool defcon)
 105 {
 106     char ser[128];
 107
 108     snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
 109     qemu_devtree_add_subnode(fdt, ser);
 110     qemu_devtree_setprop_string(fdt, ser, "device_type", "serial");
 111     qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550");
 112     qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100);
 113     qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx);
 114     qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0);
 115     qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2);
 116     qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
 117     qemu_devtree_setprop_string(fdt, "/aliases", alias, ser);
 118
 119     if (defcon) {
 120         qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
 121     }
 122 }
 123
 124 static int ppce500_load_device_tree(CPUPPCState *env,
 125                                     PPCE500Params *params,
 126                                     hwaddr addr,
 127                                     hwaddr initrd_base,
 128                                     hwaddr initrd_size)
 129 {
 130     int ret = -1;
 131     uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) };
 132     int fdt_size;
 133     void *fdt;
 134     uint8_t hypercall[16];
 135     uint32_t clock_freq = 400000000;
 136     uint32_t tb_freq = 400000000;
 137     int i;
 138     const char *toplevel_compat = NULL; /* user override */
 139     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
 140     char soc[128];
 141     char mpic[128];
 142     uint32_t mpic_ph;
 143     uint32_t msi_ph;
 144     char gutil[128];
 145     char pci[128];
 146     char msi[128];
 147     uint32_t *pci_map = NULL;
 148     int len;
 149     uint32_t pci_ranges[14] =
 150         {
 151             0x2000000, 0x0, 0xc0000000,
 152             0x0, 0xc0000000,
 153             0x0, 0x20000000,
 154
 155             0x1000000, 0x0, 0x0,
 156             0x0, 0xe1000000,
 157             0x0, 0x10000,
 158         };
 159     QemuOpts *machine_opts;
 160     const char *dtb_file = NULL;
 161
 162     machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
 163     if (machine_opts) {
 164         dtb_file = qemu_opt_get(machine_opts, "dtb");
 165         toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
 166     }
 167
 168     if (dtb_file) {
 169         char *filename;
 170         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
 171         if (!filename) {
 172             goto out;
 173         }
 174
 175         fdt = load_device_tree(filename, &fdt_size);
 176         if (!fdt) {
 177             goto out;
 178         }
 179         goto done;
 180     }
 181
 182     fdt = create_device_tree(&fdt_size);
 183     if (fdt == NULL) {
 184         goto out;
 185     }
 186
 187     /* Manipulate device tree in memory. */
 188     qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
 189     qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
 190
 191     qemu_devtree_add_subnode(fdt, "/memory");
 192     qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
 193     qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
 194                          sizeof(mem_reg_property));
 195
 196     qemu_devtree_add_subnode(fdt, "/chosen");
 197     if (initrd_size) {
 198         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
 199                                         initrd_base);
 200         if (ret < 0) {
 201             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 202         }
 203
 204         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 205                                         (initrd_base + initrd_size));
 206         if (ret < 0) {
 207             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 208         }
 209     }
 210
 211     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 212                                       params->kernel_cmdline);
 213     if (ret < 0)
 214         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 215
 216     if (kvm_enabled()) {
 217         /* Read out host's frequencies */
 218         clock_freq = kvmppc_get_clockfreq();
 219         tb_freq = kvmppc_get_tbfreq();
 220
 221         /* indicate KVM hypercall interface */
 222         qemu_devtree_add_subnode(fdt, "/hypervisor");
 223         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 224                                     "linux,kvm");
 225         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 226         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 227                              hypercall, sizeof(hypercall));
 228         /* if KVM supports the idle hcall, set property indicating this */
 229         if (kvmppc_get_hasidle(env)) {
 230             qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
 231         }
 232     }
 233
 234     /* Create CPU nodes */
 235     qemu_devtree_add_subnode(fdt, "/cpus");
 236     qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
 237     qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
 238
 239     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 240        the first node as boot node and be happy */
 241     for (i = smp_cpus - 1; i >= 0; i--) {
 242         CPUState *cpu = NULL;
 243         char cpu_name[128];
 244         uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
 245
 246         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 247             cpu = ENV_GET_CPU(env);
 248             if (cpu->cpu_index == i) {
 249                 break;
 250             }
 251         }
 252
 253         if (cpu == NULL) {
 254             continue;
 255         }
 256
 257         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
 258                  cpu->cpu_index);
 259         qemu_devtree_add_subnode(fdt, cpu_name);
 260         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 261         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 262         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 263         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index);
 264         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 265                                   env->dcache_line_size);
 266         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 267                                   env->icache_line_size);
 268         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 269         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 270         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 271         if (cpu->cpu_index) {
 272             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 273             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 274             qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr",
 275                                      cpu_release_addr);
 276         } else {
 277             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 278         }
 279     }
 280
 281     qemu_devtree_add_subnode(fdt, "/aliases");
 282     /* XXX These should go into their respective devices' code */
 283     snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
 284     qemu_devtree_add_subnode(fdt, soc);
 285     qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
 286     qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb,
 287                          sizeof(compatible_sb));
 288     qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
 289     qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
 290     qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
 291                                MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
 292                                MPC8544_CCSRBAR_SIZE);
 293     /* XXX should contain a reasonable value */
 294     qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
 295
 296     snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
 297     qemu_devtree_add_subnode(fdt, mpic);
 298     qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic");
 299     qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic");
 300     qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
 301                                0x40000);
 302     qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0);
 303     qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
 304     mpic_ph = qemu_devtree_alloc_phandle(fdt);
 305     qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph);
 306     qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
 307     qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
 308
 309     /*
 310      * We have to generate ser1 first, because Linux takes the first
 311      * device it finds in the dt as serial output device. And we generate
 312      * devices in reverse order to the dt.
 313      */
 314     dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
 315                      soc, mpic, "serial1", 1, false);
 316     dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
 317                      soc, mpic, "serial0", 0, true);
 318
 319     snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
 320              MPC8544_UTIL_OFFSET);
 321     qemu_devtree_add_subnode(fdt, gutil);
 322     qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
 323     qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
 324     qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
 325
 326     snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
 327     qemu_devtree_add_subnode(fdt, msi);
 328     qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
 329     qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
 330     msi_ph = qemu_devtree_alloc_phandle(fdt);
 331     qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
 332     qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
 333     qemu_devtree_setprop_cells(fdt, msi, "interrupts",
 334         0xe0, 0x0,
 335         0xe1, 0x0,
 336         0xe2, 0x0,
 337         0xe3, 0x0,
 338         0xe4, 0x0,
 339         0xe5, 0x0,
 340         0xe6, 0x0,
 341         0xe7, 0x0);
 342     qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph);
 343     qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
 344
 345     snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
 346     qemu_devtree_add_subnode(fdt, pci);
 347     qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
 348     qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
 349     qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
 350     qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
 351                                0x0, 0x7);
 352     pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic),
 353                              params->pci_first_slot, params->pci_nr_slots,
 354                              &len);
 355     qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len);
 356     qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
 357     qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
 358     qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
 359     for (i = 0; i < 14; i++) {
 360         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
 361     }
 362     qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
 363     qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
 364     qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
 365                                MPC8544_PCI_REGS_BASE, 0, 0x1000);
 366     qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
 367     qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
 368     qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
 369     qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
 370     qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
 371
 372     params->fixup_devtree(params, fdt);
 373
 374     if (toplevel_compat) {
 375         qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat,
 376                              strlen(toplevel_compat) + 1);
 377     }
 378
 379 done:
 380     qemu_devtree_dumpdtb(fdt, fdt_size);
 381     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 382     if (ret < 0) {
 383         goto out;
 384     }
 385     g_free(fdt);
 386     ret = fdt_size;
 387
 388 out:
 389     g_free(pci_map);
 390
 391     return ret;
 392 }
 393
 394 /* Create -kernel TLB entries for BookE.  */
 395 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
 396 {
 397     return 63 - clz64(size >> 10);
 398 }
 399
 400 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 401 {
 402     struct boot_info *bi = env->load_info;
 403     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 404     hwaddr size, dt_end;
 405     int ps;
 406
 407     /* Our initial TLB entry needs to cover everything from 0 to
 408        the device tree top */
 409     dt_end = bi->dt_base + bi->dt_size;
 410     ps = booke206_page_size_to_tlb(dt_end) + 1;
 411     if (ps & 1) {
 412         /* e500v2 can only do even TLB size bits */
 413         ps++;
 414     }
 415     size = (ps << MAS1_TSIZE_SHIFT);
 416     tlb->mas1 = MAS1_VALID | size;
 417     tlb->mas2 = 0;
 418     tlb->mas7_3 = 0;
 419     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 420
 421     env->tlb_dirty = true;
 422 }
 423
 424 static void ppce500_cpu_reset_sec(void *opaque)
 425 {
 426     PowerPCCPU *cpu = opaque;
 427     CPUPPCState *env = &cpu->env;
 428
 429     cpu_reset(CPU(cpu));
 430
 431     /* Secondary CPU starts in halted state for now. Needs to change when
 432        implementing non-kernel boot. */
 433     env->halted = 1;
 434     env->exception_index = EXCP_HLT;
 435 }
 436
 437 static void ppce500_cpu_reset(void *opaque)
 438 {
 439     PowerPCCPU *cpu = opaque;
 440     CPUPPCState *env = &cpu->env;
 441     struct boot_info *bi = env->load_info;
 442
 443     cpu_reset(CPU(cpu));
 444
 445     /* Set initial guest state. */
 446     env->halted = 0;
 447     env->gpr[1] = (16<<20) - 8;
 448     env->gpr[3] = bi->dt_base;
 449     env->nip = bi->entry;
 450     mmubooke_create_initial_mapping(env);
 451 }
 452
 453 void ppce500_init(PPCE500Params *params)
 454 {
 455     MemoryRegion *address_space_mem = get_system_memory();
 456     MemoryRegion *ram = g_new(MemoryRegion, 1);
 457     PCIBus *pci_bus;
 458     CPUPPCState *env = NULL;
 459     uint64_t elf_entry;
 460     uint64_t elf_lowaddr;
 461     hwaddr entry=0;
 462     hwaddr loadaddr=UIMAGE_LOAD_BASE;
 463     target_long kernel_size=0;
 464     target_ulong dt_base = 0;
 465     target_ulong initrd_base = 0;
 466     target_long initrd_size=0;
 467     int i = 0, j, k;
 468     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 469     qemu_irq **irqs, *mpic;
 470     DeviceState *dev;
 471     CPUPPCState *firstenv = NULL;
 472     MemoryRegion *ccsr_addr_space;
 473     SysBusDevice *s;
 474     PPCE500CCSRState *ccsr;
 475
 476     /* Setup CPUs */
 477     if (params->cpu_model == NULL) {
 478         params->cpu_model = "e500v2_v30";
 479     }
 480
 481     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 482     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 483     for (i = 0; i < smp_cpus; i++) {
 484         PowerPCCPU *cpu;
 485         CPUState *cs;
 486         qemu_irq *input;
 487
 488         cpu = cpu_ppc_init(params->cpu_model);
 489         if (cpu == NULL) {
 490             fprintf(stderr, "Unable to initialize CPU!\n");
 491             exit(1);
 492         }
 493         env = &cpu->env;
 494         cs = CPU(cpu);
 495
 496         if (!firstenv) {
 497             firstenv = env;
 498         }
 499
 500         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 501         input = (qemu_irq *)env->irq_inputs;
 502         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 503         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 504         env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i;
 505         env->mpic_iack = MPC8544_CCSRBAR_BASE +
 506                          MPC8544_MPIC_REGS_OFFSET + 0x200A0;
 507
 508         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
 509
 510         /* Register reset handler */
 511         if (!i) {
 512             /* Primary CPU */
 513             struct boot_info *boot_info;
 514             boot_info = g_malloc0(sizeof(struct boot_info));
 515             qemu_register_reset(ppce500_cpu_reset, cpu);
 516             env->load_info = boot_info;
 517         } else {
 518             /* Secondary CPUs */
 519             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
 520         }
 521     }
 522
 523     env = firstenv;
 524
 525     /* Fixup Memory size on a alignment boundary */
 526     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 527
 528     /* Register Memory */
 529     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 530     vmstate_register_ram_global(ram);
 531     memory_region_add_subregion(address_space_mem, 0, ram);
 532
 533     dev = qdev_create(NULL, "e500-ccsr");
 534     object_property_add_child(qdev_get_machine(), "e500-ccsr",
 535                               OBJECT(dev), NULL);
 536     qdev_init_nofail(dev);
 537     ccsr = CCSR(dev);
 538     ccsr_addr_space = &ccsr->ccsr_space;
 539     memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
 540                                 ccsr_addr_space);
 541
 542     /* MPIC */
 543     mpic = g_new(qemu_irq, 256);
 544     dev = qdev_create(NULL, "openpic");
 545     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
 546     qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_FSL_MPIC_20);
 547     qdev_init_nofail(dev);
 548     s = sysbus_from_qdev(dev);
 549
 550     k = 0;
 551     for (i = 0; i < smp_cpus; i++) {
 552         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
 553             sysbus_connect_irq(s, k++, irqs[i][j]);
 554         }
 555     }
 556
 557     for (i = 0; i < 256; i++) {
 558         mpic[i] = qdev_get_gpio_in(dev, i);
 559     }
 560
 561     memory_region_add_subregion(ccsr_addr_space, MPC8544_MPIC_REGS_OFFSET,
 562                                 s->mmio[0].memory);
 563
 564     /* Serial */
 565     if (serial_hds[0]) {
 566         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
 567                        0, mpic[42], 399193,
 568                        serial_hds[0], DEVICE_BIG_ENDIAN);
 569     }
 570
 571     if (serial_hds[1]) {
 572         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
 573                        0, mpic[42], 399193,
 574                        serial_hds[1], DEVICE_BIG_ENDIAN);
 575     }
 576
 577     /* General Utility device */
 578     dev = qdev_create(NULL, "mpc8544-guts");
 579     qdev_init_nofail(dev);
 580     s = SYS_BUS_DEVICE(dev);
 581     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
 582                                 sysbus_mmio_get_region(s, 0));
 583
 584     /* PCI */
 585     dev = qdev_create(NULL, "e500-pcihost");
 586     qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
 587     qdev_init_nofail(dev);
 588     s = SYS_BUS_DEVICE(dev);
 589     sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
 590     sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]);
 591     sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]);
 592     sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]);
 593     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
 594                                 sysbus_mmio_get_region(s, 0));
 595
 596     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 597     if (!pci_bus)
 598         printf("couldn't create PCI controller!\n");
 599
 600     sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO);
 601
 602     if (pci_bus) {
 603         /* Register network interfaces. */
 604         for (i = 0; i < nb_nics; i++) {
 605             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 606         }
 607     }
 608
 609     /* Register spinning region */
 610     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 611
 612     /* Load kernel. */
 613     if (params->kernel_filename) {
 614         kernel_size = load_uimage(params->kernel_filename, &entry,
 615                                   &loadaddr, NULL);
 616         if (kernel_size < 0) {
 617             kernel_size = load_elf(params->kernel_filename, NULL, NULL,
 618                                    &elf_entry, &elf_lowaddr, NULL, 1,
 619                                    ELF_MACHINE, 0);
 620             entry = elf_entry;
 621             loadaddr = elf_lowaddr;
 622         }
 623         /* XXX try again as binary */
 624         if (kernel_size < 0) {
 625             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 626                     params->kernel_filename);
 627             exit(1);
 628         }
 629     }
 630
 631     /* Load initrd. */
 632     if (params->initrd_filename) {
 633         initrd_base = (loadaddr + kernel_size + INITRD_LOAD_PAD) &
 634             ~INITRD_PAD_MASK;
 635         initrd_size = load_image_targphys(params->initrd_filename, initrd_base,
 636                                           ram_size - initrd_base);
 637
 638         if (initrd_size < 0) {
 639             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 640                     params->initrd_filename);
 641             exit(1);
 642         }
 643     }
 644
 645     /* If we're loading a kernel directly, we must load the device tree too. */
 646     if (params->kernel_filename) {
 647         struct boot_info *boot_info;
 648         int dt_size;
 649
 650         dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 651         dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base,
 652                                            initrd_size);
 653         if (dt_size < 0) {
 654             fprintf(stderr, "couldn't load device tree\n");
 655             exit(1);
 656         }
 657
 658         boot_info = env->load_info;
 659         boot_info->entry = entry;
 660         boot_info->dt_base = dt_base;
 661         boot_info->dt_size = dt_size;
 662     }
 663
 664     if (kvm_enabled()) {
 665         kvmppc_init();
 666     }
 667 }
 668
 669 static int e500_ccsr_initfn(SysBusDevice *dev)
 670 {
 671     PPCE500CCSRState *ccsr;
 672
 673     ccsr = CCSR(dev);
 674     memory_region_init(&ccsr->ccsr_space, "e500-ccsr",
 675                        MPC8544_CCSRBAR_SIZE);
 676     return 0;
 677 }
 678
 679 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
 680 {
 681     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 682     k->init = e500_ccsr_initfn;
 683 }
 684
 685 static const TypeInfo e500_ccsr_info = {
 686     .name          = TYPE_CCSR,
 687     .parent        = TYPE_SYS_BUS_DEVICE,
 688     .instance_size = sizeof(PPCE500CCSRState),
 689     .class_init    = e500_ccsr_class_init,
 690 };
 691
 692 static void e500_register_types(void)
 693 {
 694     type_register_static(&e500_ccsr_info);
 695 }
 696
 697 type_init(e500_register_types)