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[qemu.git] / hw / ppc / mac_newworld.c
1 /*
2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 *
25 * PCI bus layout on a real G5 (U3 based):
26 *
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47 *
48 */
49 #include "hw/hw.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/ppc/mac.h"
52 #include "hw/input/adb.h"
53 #include "hw/ppc/mac_dbdma.h"
54 #include "hw/timer/m48t59.h"
55 #include "hw/pci/pci.h"
56 #include "net/net.h"
57 #include "sysemu/sysemu.h"
58 #include "hw/boards.h"
59 #include "hw/nvram/fw_cfg.h"
60 #include "hw/char/escc.h"
61 #include "hw/ppc/openpic.h"
62 #include "hw/ide.h"
63 #include "hw/loader.h"
64 #include "elf.h"
65 #include "sysemu/kvm.h"
66 #include "kvm_ppc.h"
67 #include "hw/usb.h"
68 #include "sysemu/blockdev.h"
69 #include "exec/address-spaces.h"
70 #include "hw/sysbus.h"
71
72 #define MAX_IDE_BUS 2
73 #define CFG_ADDR 0xf0000510
74
75 /* debug UniNorth */
76 //#define DEBUG_UNIN
77
78 #ifdef DEBUG_UNIN
79 #define UNIN_DPRINTF(fmt, ...) \
80 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
81 #else
82 #define UNIN_DPRINTF(fmt, ...)
83 #endif
84
85 /* UniN device */
86 static void unin_write(void *opaque, hwaddr addr, uint64_t value,
87 unsigned size)
88 {
89 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
90 if (addr == 0x0) {
91 *(int*)opaque = value;
92 }
93 }
94
95 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
96 {
97 uint32_t value;
98
99 value = 0;
100 switch (addr) {
101 case 0:
102 value = *(int*)opaque;
103 }
104
105 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
106
107 return value;
108 }
109
110 static const MemoryRegionOps unin_ops = {
111 .read = unin_read,
112 .write = unin_write,
113 .endianness = DEVICE_NATIVE_ENDIAN,
114 };
115
116 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
117 {
118 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
119 return 0;
120 }
121
122 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
123 {
124 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
125 }
126
127 static hwaddr round_page(hwaddr addr)
128 {
129 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
130 }
131
132 static void ppc_core99_reset(void *opaque)
133 {
134 PowerPCCPU *cpu = opaque;
135
136 cpu_reset(CPU(cpu));
137 /* 970 CPUs want to get their initial IP as part of their boot protocol */
138 cpu->env.nip = PROM_ADDR + 0x100;
139 }
140
141 /* PowerPC Mac99 hardware initialisation */
142 static void ppc_core99_init(QEMUMachineInitArgs *args)
143 {
144 ram_addr_t ram_size = args->ram_size;
145 const char *cpu_model = args->cpu_model;
146 const char *kernel_filename = args->kernel_filename;
147 const char *kernel_cmdline = args->kernel_cmdline;
148 const char *initrd_filename = args->initrd_filename;
149 const char *boot_device = args->boot_device;
150 PowerPCCPU *cpu = NULL;
151 CPUPPCState *env = NULL;
152 char *filename;
153 qemu_irq *pic, **openpic_irqs;
154 MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
155 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
156 int linux_boot, i, j, k;
157 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
158 hwaddr kernel_base, initrd_base, cmdline_base = 0;
159 long kernel_size, initrd_size;
160 PCIBus *pci_bus;
161 PCIDevice *macio;
162 MACIOIDEState *macio_ide;
163 BusState *adb_bus;
164 MacIONVRAMState *nvr;
165 int bios_size;
166 MemoryRegion *pic_mem, *escc_mem;
167 MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
168 int ppc_boot_device;
169 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
170 void *fw_cfg;
171 int machine_arch;
172 SysBusDevice *s;
173 DeviceState *dev;
174 int *token = g_new(int, 1);
175
176 linux_boot = (kernel_filename != NULL);
177
178 /* init CPUs */
179 if (cpu_model == NULL)
180 #ifdef TARGET_PPC64
181 cpu_model = "970fx";
182 #else
183 cpu_model = "G4";
184 #endif
185 for (i = 0; i < smp_cpus; i++) {
186 cpu = cpu_ppc_init(cpu_model);
187 if (cpu == NULL) {
188 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
189 exit(1);
190 }
191 env = &cpu->env;
192
193 /* Set time-base frequency to 100 Mhz */
194 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
195 qemu_register_reset(ppc_core99_reset, cpu);
196 }
197
198 /* allocate RAM */
199 memory_region_init_ram(ram, "ppc_core99.ram", ram_size);
200 vmstate_register_ram_global(ram);
201 memory_region_add_subregion(get_system_memory(), 0, ram);
202
203 /* allocate and load BIOS */
204 memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE);
205 vmstate_register_ram_global(bios);
206 if (bios_name == NULL)
207 bios_name = PROM_FILENAME;
208 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
209 memory_region_set_readonly(bios, true);
210 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
211
212 /* Load OpenBIOS (ELF) */
213 if (filename) {
214 bios_size = load_elf(filename, NULL, NULL, NULL,
215 NULL, NULL, 1, ELF_MACHINE, 0);
216
217 g_free(filename);
218 } else {
219 bios_size = -1;
220 }
221 if (bios_size < 0 || bios_size > BIOS_SIZE) {
222 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
223 exit(1);
224 }
225
226 if (linux_boot) {
227 uint64_t lowaddr = 0;
228 int bswap_needed;
229
230 #ifdef BSWAP_NEEDED
231 bswap_needed = 1;
232 #else
233 bswap_needed = 0;
234 #endif
235 kernel_base = KERNEL_LOAD_ADDR;
236
237 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
238 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
239 if (kernel_size < 0)
240 kernel_size = load_aout(kernel_filename, kernel_base,
241 ram_size - kernel_base, bswap_needed,
242 TARGET_PAGE_SIZE);
243 if (kernel_size < 0)
244 kernel_size = load_image_targphys(kernel_filename,
245 kernel_base,
246 ram_size - kernel_base);
247 if (kernel_size < 0) {
248 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
249 exit(1);
250 }
251 /* load initrd */
252 if (initrd_filename) {
253 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
254 initrd_size = load_image_targphys(initrd_filename, initrd_base,
255 ram_size - initrd_base);
256 if (initrd_size < 0) {
257 hw_error("qemu: could not load initial ram disk '%s'\n",
258 initrd_filename);
259 exit(1);
260 }
261 cmdline_base = round_page(initrd_base + initrd_size);
262 } else {
263 initrd_base = 0;
264 initrd_size = 0;
265 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
266 }
267 ppc_boot_device = 'm';
268 } else {
269 kernel_base = 0;
270 kernel_size = 0;
271 initrd_base = 0;
272 initrd_size = 0;
273 ppc_boot_device = '\0';
274 /* We consider that NewWorld PowerMac never have any floppy drive
275 * For now, OHW cannot boot from the network.
276 */
277 for (i = 0; boot_device[i] != '\0'; i++) {
278 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
279 ppc_boot_device = boot_device[i];
280 break;
281 }
282 }
283 if (ppc_boot_device == '\0') {
284 fprintf(stderr, "No valid boot device for Mac99 machine\n");
285 exit(1);
286 }
287 }
288
289 /* Register 8 MB of ISA IO space */
290 isa_mmio_init(0xf2000000, 0x00800000);
291
292 /* UniN init: XXX should be a real device */
293 memory_region_init_io(unin_memory, &unin_ops, token, "unin", 0x1000);
294 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
295
296 memory_region_init_io(unin2_memory, &unin_ops, token, "unin", 0x1000);
297 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
298
299 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
300 openpic_irqs[0] =
301 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
302 for (i = 0; i < smp_cpus; i++) {
303 /* Mac99 IRQ connection between OpenPIC outputs pins
304 * and PowerPC input pins
305 */
306 switch (PPC_INPUT(env)) {
307 case PPC_FLAGS_INPUT_6xx:
308 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
309 openpic_irqs[i][OPENPIC_OUTPUT_INT] =
310 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
311 openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
312 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
313 openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
314 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
315 /* Not connected ? */
316 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
317 /* Check this */
318 openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
319 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
320 break;
321 #if defined(TARGET_PPC64)
322 case PPC_FLAGS_INPUT_970:
323 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
324 openpic_irqs[i][OPENPIC_OUTPUT_INT] =
325 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
326 openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
327 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
328 openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
329 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
330 /* Not connected ? */
331 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
332 /* Check this */
333 openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
334 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
335 break;
336 #endif /* defined(TARGET_PPC64) */
337 default:
338 hw_error("Bus model not supported on mac99 machine\n");
339 exit(1);
340 }
341 }
342
343 pic = g_new(qemu_irq, 64);
344
345 dev = qdev_create(NULL, TYPE_OPENPIC);
346 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN);
347 qdev_init_nofail(dev);
348 s = SYS_BUS_DEVICE(dev);
349 pic_mem = s->mmio[0].memory;
350 k = 0;
351 for (i = 0; i < smp_cpus; i++) {
352 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
353 sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
354 }
355 }
356
357 for (i = 0; i < 64; i++) {
358 pic[i] = qdev_get_gpio_in(dev, i);
359 }
360
361 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
362 /* 970 gets a U3 bus */
363 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
364 machine_arch = ARCH_MAC99_U3;
365 } else {
366 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
367 machine_arch = ARCH_MAC99;
368 }
369 /* init basic PC hardware */
370 pci_vga_init(pci_bus);
371
372 escc_mem = escc_init(0, pic[0x25], pic[0x24],
373 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
374 memory_region_init_alias(escc_bar, "escc-bar",
375 escc_mem, 0, memory_region_size(escc_mem));
376
377 for(i = 0; i < nb_nics; i++)
378 pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
379
380 ide_drive_get(hd, MAX_IDE_BUS);
381
382 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO);
383 dev = DEVICE(macio);
384 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
385 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */
386 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */
387 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */
388 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */
389 macio_init(macio, pic_mem, escc_bar);
390
391 /* We only emulate 2 out of 3 IDE controllers for now */
392 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
393 "ide[0]"));
394 macio_ide_init_drives(macio_ide, hd);
395
396 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
397 "ide[1]"));
398 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
399
400 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
401 adb_bus = qdev_get_child_bus(dev, "adb.0");
402 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
403 qdev_init_nofail(dev);
404 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
405 qdev_init_nofail(dev);
406
407 if (usb_enabled(machine_arch == ARCH_MAC99_U3)) {
408 pci_create_simple(pci_bus, -1, "pci-ohci");
409 /* U3 needs to use USB for input because Linux doesn't support via-cuda
410 on PPC64 */
411 if (machine_arch == ARCH_MAC99_U3) {
412 usbdevice_create("keyboard");
413 usbdevice_create("mouse");
414 }
415 }
416
417 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
418 graphic_depth = 15;
419
420 /* The NewWorld NVRAM is not located in the MacIO device */
421 dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
422 qdev_prop_set_uint32(dev, "size", 0x2000);
423 qdev_prop_set_uint32(dev, "it_shift", 1);
424 qdev_init_nofail(dev);
425 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xFFF04000);
426 nvr = MACIO_NVRAM(dev);
427 pmac_format_nvram_partition(nvr, 0x2000);
428 /* No PCI init: the BIOS will do it */
429
430 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
431 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
432 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
433 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
434 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
435 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
436 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
437 if (kernel_cmdline) {
438 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
439 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
440 } else {
441 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
442 }
443 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
444 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
445 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
446
447 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
448 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
449 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
450
451 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
452 if (kvm_enabled()) {
453 #ifdef CONFIG_KVM
454 uint8_t *hypercall;
455
456 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
457 hypercall = g_malloc(16);
458 kvmppc_get_hypercall(env, hypercall, 16);
459 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
460 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
461 #endif
462 } else {
463 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
464 }
465 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
466 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 266000000);
467
468 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
469 }
470
471 static QEMUMachine core99_machine = {
472 .name = "mac99",
473 .desc = "Mac99 based PowerMAC",
474 .init = ppc_core99_init,
475 .max_cpus = MAX_CPUS,
476 DEFAULT_MACHINE_OPTIONS,
477 };
478
479 static void core99_machine_init(void)
480 {
481 qemu_register_machine(&core99_machine);
482 }
483
484 machine_init(core99_machine_init);
Qemu copy for testing