]> git.proxmox.com Git - qemu.git/blob - hw/ppc/ppc.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
tcg/aarch64: Implement tlb lookup fast path
[qemu.git] / hw / ppc / ppc.c
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/ppc/ppc.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/timer/m48t59.h"
29 #include "qemu/log.h"
30 #include "hw/loader.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33
34 //#define PPC_DEBUG_IRQ
35 //#define PPC_DEBUG_TB
36
37 #ifdef PPC_DEBUG_IRQ
38 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
39 #else
40 # define LOG_IRQ(...) do { } while (0)
41 #endif
42
43
44 #ifdef PPC_DEBUG_TB
45 # define LOG_TB(...) qemu_log(__VA_ARGS__)
46 #else
47 # define LOG_TB(...) do { } while (0)
48 #endif
49
50 static void cpu_ppc_tb_stop (CPUPPCState *env);
51 static void cpu_ppc_tb_start (CPUPPCState *env);
52
53 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
54 {
55 CPUState *cs = CPU(cpu);
56 CPUPPCState *env = &cpu->env;
57 unsigned int old_pending = env->pending_interrupts;
58
59 if (level) {
60 env->pending_interrupts |= 1 << n_IRQ;
61 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
62 } else {
63 env->pending_interrupts &= ~(1 << n_IRQ);
64 if (env->pending_interrupts == 0) {
65 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
66 }
67 }
68
69 if (old_pending != env->pending_interrupts) {
70 #ifdef CONFIG_KVM
71 kvmppc_set_interrupt(cpu, n_IRQ, level);
72 #endif
73 }
74
75 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
76 "req %08x\n", __func__, env, n_IRQ, level,
77 env->pending_interrupts, CPU(cpu)->interrupt_request);
78 }
79
80 /* PowerPC 6xx / 7xx internal IRQ controller */
81 static void ppc6xx_set_irq(void *opaque, int pin, int level)
82 {
83 PowerPCCPU *cpu = opaque;
84 CPUPPCState *env = &cpu->env;
85 int cur_level;
86
87 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
88 env, pin, level);
89 cur_level = (env->irq_input_state >> pin) & 1;
90 /* Don't generate spurious events */
91 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
92 CPUState *cs = CPU(cpu);
93
94 switch (pin) {
95 case PPC6xx_INPUT_TBEN:
96 /* Level sensitive - active high */
97 LOG_IRQ("%s: %s the time base\n",
98 __func__, level ? "start" : "stop");
99 if (level) {
100 cpu_ppc_tb_start(env);
101 } else {
102 cpu_ppc_tb_stop(env);
103 }
104 case PPC6xx_INPUT_INT:
105 /* Level sensitive - active high */
106 LOG_IRQ("%s: set the external IRQ state to %d\n",
107 __func__, level);
108 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
109 break;
110 case PPC6xx_INPUT_SMI:
111 /* Level sensitive - active high */
112 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
113 __func__, level);
114 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
115 break;
116 case PPC6xx_INPUT_MCP:
117 /* Negative edge sensitive */
118 /* XXX: TODO: actual reaction may depends on HID0 status
119 * 603/604/740/750: check HID0[EMCP]
120 */
121 if (cur_level == 1 && level == 0) {
122 LOG_IRQ("%s: raise machine check state\n",
123 __func__);
124 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
125 }
126 break;
127 case PPC6xx_INPUT_CKSTP_IN:
128 /* Level sensitive - active low */
129 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
130 /* XXX: Note that the only way to restart the CPU is to reset it */
131 if (level) {
132 LOG_IRQ("%s: stop the CPU\n", __func__);
133 cs->halted = 1;
134 }
135 break;
136 case PPC6xx_INPUT_HRESET:
137 /* Level sensitive - active low */
138 if (level) {
139 LOG_IRQ("%s: reset the CPU\n", __func__);
140 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
141 }
142 break;
143 case PPC6xx_INPUT_SRESET:
144 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
145 __func__, level);
146 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
147 break;
148 default:
149 /* Unknown pin - do nothing */
150 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
151 return;
152 }
153 if (level)
154 env->irq_input_state |= 1 << pin;
155 else
156 env->irq_input_state &= ~(1 << pin);
157 }
158 }
159
160 void ppc6xx_irq_init(CPUPPCState *env)
161 {
162 PowerPCCPU *cpu = ppc_env_get_cpu(env);
163
164 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
165 PPC6xx_INPUT_NB);
166 }
167
168 #if defined(TARGET_PPC64)
169 /* PowerPC 970 internal IRQ controller */
170 static void ppc970_set_irq(void *opaque, int pin, int level)
171 {
172 PowerPCCPU *cpu = opaque;
173 CPUPPCState *env = &cpu->env;
174 int cur_level;
175
176 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
177 env, pin, level);
178 cur_level = (env->irq_input_state >> pin) & 1;
179 /* Don't generate spurious events */
180 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
181 CPUState *cs = CPU(cpu);
182
183 switch (pin) {
184 case PPC970_INPUT_INT:
185 /* Level sensitive - active high */
186 LOG_IRQ("%s: set the external IRQ state to %d\n",
187 __func__, level);
188 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
189 break;
190 case PPC970_INPUT_THINT:
191 /* Level sensitive - active high */
192 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
193 level);
194 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
195 break;
196 case PPC970_INPUT_MCP:
197 /* Negative edge sensitive */
198 /* XXX: TODO: actual reaction may depends on HID0 status
199 * 603/604/740/750: check HID0[EMCP]
200 */
201 if (cur_level == 1 && level == 0) {
202 LOG_IRQ("%s: raise machine check state\n",
203 __func__);
204 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
205 }
206 break;
207 case PPC970_INPUT_CKSTP:
208 /* Level sensitive - active low */
209 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
210 if (level) {
211 LOG_IRQ("%s: stop the CPU\n", __func__);
212 cs->halted = 1;
213 } else {
214 LOG_IRQ("%s: restart the CPU\n", __func__);
215 cs->halted = 0;
216 qemu_cpu_kick(cs);
217 }
218 break;
219 case PPC970_INPUT_HRESET:
220 /* Level sensitive - active low */
221 if (level) {
222 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
223 }
224 break;
225 case PPC970_INPUT_SRESET:
226 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
227 __func__, level);
228 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
229 break;
230 case PPC970_INPUT_TBEN:
231 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
232 level);
233 /* XXX: TODO */
234 break;
235 default:
236 /* Unknown pin - do nothing */
237 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
238 return;
239 }
240 if (level)
241 env->irq_input_state |= 1 << pin;
242 else
243 env->irq_input_state &= ~(1 << pin);
244 }
245 }
246
247 void ppc970_irq_init(CPUPPCState *env)
248 {
249 PowerPCCPU *cpu = ppc_env_get_cpu(env);
250
251 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
252 PPC970_INPUT_NB);
253 }
254
255 /* POWER7 internal IRQ controller */
256 static void power7_set_irq(void *opaque, int pin, int level)
257 {
258 PowerPCCPU *cpu = opaque;
259 CPUPPCState *env = &cpu->env;
260
261 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
262 env, pin, level);
263
264 switch (pin) {
265 case POWER7_INPUT_INT:
266 /* Level sensitive - active high */
267 LOG_IRQ("%s: set the external IRQ state to %d\n",
268 __func__, level);
269 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
270 break;
271 default:
272 /* Unknown pin - do nothing */
273 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
274 return;
275 }
276 if (level) {
277 env->irq_input_state |= 1 << pin;
278 } else {
279 env->irq_input_state &= ~(1 << pin);
280 }
281 }
282
283 void ppcPOWER7_irq_init(CPUPPCState *env)
284 {
285 PowerPCCPU *cpu = ppc_env_get_cpu(env);
286
287 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
288 POWER7_INPUT_NB);
289 }
290 #endif /* defined(TARGET_PPC64) */
291
292 /* PowerPC 40x internal IRQ controller */
293 static void ppc40x_set_irq(void *opaque, int pin, int level)
294 {
295 PowerPCCPU *cpu = opaque;
296 CPUPPCState *env = &cpu->env;
297 int cur_level;
298
299 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
300 env, pin, level);
301 cur_level = (env->irq_input_state >> pin) & 1;
302 /* Don't generate spurious events */
303 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
304 CPUState *cs = CPU(cpu);
305
306 switch (pin) {
307 case PPC40x_INPUT_RESET_SYS:
308 if (level) {
309 LOG_IRQ("%s: reset the PowerPC system\n",
310 __func__);
311 ppc40x_system_reset(cpu);
312 }
313 break;
314 case PPC40x_INPUT_RESET_CHIP:
315 if (level) {
316 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
317 ppc40x_chip_reset(cpu);
318 }
319 break;
320 case PPC40x_INPUT_RESET_CORE:
321 /* XXX: TODO: update DBSR[MRR] */
322 if (level) {
323 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
324 ppc40x_core_reset(cpu);
325 }
326 break;
327 case PPC40x_INPUT_CINT:
328 /* Level sensitive - active high */
329 LOG_IRQ("%s: set the critical IRQ state to %d\n",
330 __func__, level);
331 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
332 break;
333 case PPC40x_INPUT_INT:
334 /* Level sensitive - active high */
335 LOG_IRQ("%s: set the external IRQ state to %d\n",
336 __func__, level);
337 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
338 break;
339 case PPC40x_INPUT_HALT:
340 /* Level sensitive - active low */
341 if (level) {
342 LOG_IRQ("%s: stop the CPU\n", __func__);
343 cs->halted = 1;
344 } else {
345 LOG_IRQ("%s: restart the CPU\n", __func__);
346 cs->halted = 0;
347 qemu_cpu_kick(cs);
348 }
349 break;
350 case PPC40x_INPUT_DEBUG:
351 /* Level sensitive - active high */
352 LOG_IRQ("%s: set the debug pin state to %d\n",
353 __func__, level);
354 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
355 break;
356 default:
357 /* Unknown pin - do nothing */
358 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
359 return;
360 }
361 if (level)
362 env->irq_input_state |= 1 << pin;
363 else
364 env->irq_input_state &= ~(1 << pin);
365 }
366 }
367
368 void ppc40x_irq_init(CPUPPCState *env)
369 {
370 PowerPCCPU *cpu = ppc_env_get_cpu(env);
371
372 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
373 cpu, PPC40x_INPUT_NB);
374 }
375
376 /* PowerPC E500 internal IRQ controller */
377 static void ppce500_set_irq(void *opaque, int pin, int level)
378 {
379 PowerPCCPU *cpu = opaque;
380 CPUPPCState *env = &cpu->env;
381 int cur_level;
382
383 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
384 env, pin, level);
385 cur_level = (env->irq_input_state >> pin) & 1;
386 /* Don't generate spurious events */
387 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
388 switch (pin) {
389 case PPCE500_INPUT_MCK:
390 if (level) {
391 LOG_IRQ("%s: reset the PowerPC system\n",
392 __func__);
393 qemu_system_reset_request();
394 }
395 break;
396 case PPCE500_INPUT_RESET_CORE:
397 if (level) {
398 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
399 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
400 }
401 break;
402 case PPCE500_INPUT_CINT:
403 /* Level sensitive - active high */
404 LOG_IRQ("%s: set the critical IRQ state to %d\n",
405 __func__, level);
406 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
407 break;
408 case PPCE500_INPUT_INT:
409 /* Level sensitive - active high */
410 LOG_IRQ("%s: set the core IRQ state to %d\n",
411 __func__, level);
412 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
413 break;
414 case PPCE500_INPUT_DEBUG:
415 /* Level sensitive - active high */
416 LOG_IRQ("%s: set the debug pin state to %d\n",
417 __func__, level);
418 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
419 break;
420 default:
421 /* Unknown pin - do nothing */
422 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
423 return;
424 }
425 if (level)
426 env->irq_input_state |= 1 << pin;
427 else
428 env->irq_input_state &= ~(1 << pin);
429 }
430 }
431
432 void ppce500_irq_init(CPUPPCState *env)
433 {
434 PowerPCCPU *cpu = ppc_env_get_cpu(env);
435
436 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
437 cpu, PPCE500_INPUT_NB);
438 }
439
440 /* Enable or Disable the E500 EPR capability */
441 void ppce500_set_mpic_proxy(bool enabled)
442 {
443 CPUPPCState *env;
444
445 for (env = first_cpu; env != NULL; env = env->next_cpu) {
446 PowerPCCPU *cpu = ppc_env_get_cpu(env);
447 CPUState *cs = CPU(cpu);
448
449 env->mpic_proxy = enabled;
450 if (kvm_enabled()) {
451 kvmppc_set_mpic_proxy(POWERPC_CPU(cs), enabled);
452 }
453 }
454 }
455
456 /*****************************************************************************/
457 /* PowerPC time base and decrementer emulation */
458
459 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
460 {
461 /* TB time in tb periods */
462 return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
463 }
464
465 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
466 {
467 ppc_tb_t *tb_env = env->tb_env;
468 uint64_t tb;
469
470 if (kvm_enabled()) {
471 return env->spr[SPR_TBL];
472 }
473
474 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
475 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
476
477 return tb;
478 }
479
480 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
481 {
482 ppc_tb_t *tb_env = env->tb_env;
483 uint64_t tb;
484
485 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
486 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
487
488 return tb >> 32;
489 }
490
491 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
492 {
493 if (kvm_enabled()) {
494 return env->spr[SPR_TBU];
495 }
496
497 return _cpu_ppc_load_tbu(env);
498 }
499
500 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
501 int64_t *tb_offsetp, uint64_t value)
502 {
503 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec());
504 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
505 __func__, value, *tb_offsetp);
506 }
507
508 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
509 {
510 ppc_tb_t *tb_env = env->tb_env;
511 uint64_t tb;
512
513 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
514 tb &= 0xFFFFFFFF00000000ULL;
515 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
516 &tb_env->tb_offset, tb | (uint64_t)value);
517 }
518
519 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
520 {
521 ppc_tb_t *tb_env = env->tb_env;
522 uint64_t tb;
523
524 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
525 tb &= 0x00000000FFFFFFFFULL;
526 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
527 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
528 }
529
530 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
531 {
532 _cpu_ppc_store_tbu(env, value);
533 }
534
535 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
536 {
537 ppc_tb_t *tb_env = env->tb_env;
538 uint64_t tb;
539
540 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
541 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
542
543 return tb;
544 }
545
546 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
547 {
548 ppc_tb_t *tb_env = env->tb_env;
549 uint64_t tb;
550
551 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
552 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
553
554 return tb >> 32;
555 }
556
557 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
558 {
559 ppc_tb_t *tb_env = env->tb_env;
560 uint64_t tb;
561
562 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
563 tb &= 0xFFFFFFFF00000000ULL;
564 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
565 &tb_env->atb_offset, tb | (uint64_t)value);
566 }
567
568 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
569 {
570 ppc_tb_t *tb_env = env->tb_env;
571 uint64_t tb;
572
573 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
574 tb &= 0x00000000FFFFFFFFULL;
575 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
576 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
577 }
578
579 static void cpu_ppc_tb_stop (CPUPPCState *env)
580 {
581 ppc_tb_t *tb_env = env->tb_env;
582 uint64_t tb, atb, vmclk;
583
584 /* If the time base is already frozen, do nothing */
585 if (tb_env->tb_freq != 0) {
586 vmclk = qemu_get_clock_ns(vm_clock);
587 /* Get the time base */
588 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
589 /* Get the alternate time base */
590 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
591 /* Store the time base value (ie compute the current offset) */
592 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
593 /* Store the alternate time base value (compute the current offset) */
594 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
595 /* Set the time base frequency to zero */
596 tb_env->tb_freq = 0;
597 /* Now, the time bases are frozen to tb_offset / atb_offset value */
598 }
599 }
600
601 static void cpu_ppc_tb_start (CPUPPCState *env)
602 {
603 ppc_tb_t *tb_env = env->tb_env;
604 uint64_t tb, atb, vmclk;
605
606 /* If the time base is not frozen, do nothing */
607 if (tb_env->tb_freq == 0) {
608 vmclk = qemu_get_clock_ns(vm_clock);
609 /* Get the time base from tb_offset */
610 tb = tb_env->tb_offset;
611 /* Get the alternate time base from atb_offset */
612 atb = tb_env->atb_offset;
613 /* Restore the tb frequency from the decrementer frequency */
614 tb_env->tb_freq = tb_env->decr_freq;
615 /* Store the time base value */
616 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
617 /* Store the alternate time base value */
618 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
619 }
620 }
621
622 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
623 {
624 ppc_tb_t *tb_env = env->tb_env;
625 uint32_t decr;
626 int64_t diff;
627
628 diff = next - qemu_get_clock_ns(vm_clock);
629 if (diff >= 0) {
630 decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
631 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
632 decr = 0;
633 } else {
634 decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec());
635 }
636 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
637
638 return decr;
639 }
640
641 uint32_t cpu_ppc_load_decr (CPUPPCState *env)
642 {
643 ppc_tb_t *tb_env = env->tb_env;
644
645 if (kvm_enabled()) {
646 return env->spr[SPR_DECR];
647 }
648
649 return _cpu_ppc_load_decr(env, tb_env->decr_next);
650 }
651
652 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
653 {
654 ppc_tb_t *tb_env = env->tb_env;
655
656 return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
657 }
658
659 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
660 {
661 ppc_tb_t *tb_env = env->tb_env;
662 uint64_t diff;
663
664 diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start;
665
666 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
667 }
668
669 /* When decrementer expires,
670 * all we need to do is generate or queue a CPU exception
671 */
672 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
673 {
674 /* Raise it */
675 LOG_TB("raise decrementer exception\n");
676 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
677 }
678
679 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
680 {
681 /* Raise it */
682 LOG_TB("raise decrementer exception\n");
683 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
684 }
685
686 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
687 struct QEMUTimer *timer,
688 void (*raise_excp)(PowerPCCPU *),
689 uint32_t decr, uint32_t value,
690 int is_excp)
691 {
692 CPUPPCState *env = &cpu->env;
693 ppc_tb_t *tb_env = env->tb_env;
694 uint64_t now, next;
695
696 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
697 decr, value);
698
699 if (kvm_enabled()) {
700 /* KVM handles decrementer exceptions, we don't need our own timer */
701 return;
702 }
703
704 now = qemu_get_clock_ns(vm_clock);
705 next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
706 if (is_excp) {
707 next += *nextp - now;
708 }
709 if (next == now) {
710 next++;
711 }
712 *nextp = next;
713 /* Adjust timer */
714 qemu_mod_timer(timer, next);
715
716 /* If we set a negative value and the decrementer was positive, raise an
717 * exception.
718 */
719 if ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED)
720 && (value & 0x80000000)
721 && !(decr & 0x80000000)) {
722 (*raise_excp)(cpu);
723 }
724 }
725
726 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
727 uint32_t value, int is_excp)
728 {
729 ppc_tb_t *tb_env = cpu->env.tb_env;
730
731 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
732 &cpu_ppc_decr_excp, decr, value, is_excp);
733 }
734
735 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
736 {
737 PowerPCCPU *cpu = ppc_env_get_cpu(env);
738
739 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0);
740 }
741
742 static void cpu_ppc_decr_cb(void *opaque)
743 {
744 PowerPCCPU *cpu = opaque;
745
746 _cpu_ppc_store_decr(cpu, 0x00000000, 0xFFFFFFFF, 1);
747 }
748
749 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
750 uint32_t value, int is_excp)
751 {
752 ppc_tb_t *tb_env = cpu->env.tb_env;
753
754 if (tb_env->hdecr_timer != NULL) {
755 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
756 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
757 }
758 }
759
760 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
761 {
762 PowerPCCPU *cpu = ppc_env_get_cpu(env);
763
764 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 0);
765 }
766
767 static void cpu_ppc_hdecr_cb(void *opaque)
768 {
769 PowerPCCPU *cpu = opaque;
770
771 _cpu_ppc_store_hdecr(cpu, 0x00000000, 0xFFFFFFFF, 1);
772 }
773
774 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
775 {
776 ppc_tb_t *tb_env = cpu->env.tb_env;
777
778 tb_env->purr_load = value;
779 tb_env->purr_start = qemu_get_clock_ns(vm_clock);
780 }
781
782 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
783 {
784 CPUPPCState *env = opaque;
785 PowerPCCPU *cpu = ppc_env_get_cpu(env);
786 ppc_tb_t *tb_env = env->tb_env;
787
788 tb_env->tb_freq = freq;
789 tb_env->decr_freq = freq;
790 /* There is a bug in Linux 2.4 kernels:
791 * if a decrementer exception is pending when it enables msr_ee at startup,
792 * it's not ready to handle it...
793 */
794 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
795 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
796 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
797 }
798
799 /* Set up (once) timebase frequency (in Hz) */
800 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
801 {
802 PowerPCCPU *cpu = ppc_env_get_cpu(env);
803 ppc_tb_t *tb_env;
804
805 tb_env = g_malloc0(sizeof(ppc_tb_t));
806 env->tb_env = tb_env;
807 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
808 /* Create new timer */
809 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, cpu);
810 if (0) {
811 /* XXX: find a suitable condition to enable the hypervisor decrementer
812 */
813 tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb,
814 cpu);
815 } else {
816 tb_env->hdecr_timer = NULL;
817 }
818 cpu_ppc_set_tb_clk(env, freq);
819
820 return &cpu_ppc_set_tb_clk;
821 }
822
823 /* Specific helpers for POWER & PowerPC 601 RTC */
824 #if 0
825 static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
826 {
827 return cpu_ppc_tb_init(env, 7812500);
828 }
829 #endif
830
831 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
832 {
833 _cpu_ppc_store_tbu(env, value);
834 }
835
836 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
837 {
838 return _cpu_ppc_load_tbu(env);
839 }
840
841 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
842 {
843 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
844 }
845
846 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
847 {
848 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
849 }
850
851 /*****************************************************************************/
852 /* PowerPC 40x timers */
853
854 /* PIT, FIT & WDT */
855 typedef struct ppc40x_timer_t ppc40x_timer_t;
856 struct ppc40x_timer_t {
857 uint64_t pit_reload; /* PIT auto-reload value */
858 uint64_t fit_next; /* Tick for next FIT interrupt */
859 struct QEMUTimer *fit_timer;
860 uint64_t wdt_next; /* Tick for next WDT interrupt */
861 struct QEMUTimer *wdt_timer;
862
863 /* 405 have the PIT, 440 have a DECR. */
864 unsigned int decr_excp;
865 };
866
867 /* Fixed interval timer */
868 static void cpu_4xx_fit_cb (void *opaque)
869 {
870 PowerPCCPU *cpu;
871 CPUPPCState *env;
872 ppc_tb_t *tb_env;
873 ppc40x_timer_t *ppc40x_timer;
874 uint64_t now, next;
875
876 env = opaque;
877 cpu = ppc_env_get_cpu(env);
878 tb_env = env->tb_env;
879 ppc40x_timer = tb_env->opaque;
880 now = qemu_get_clock_ns(vm_clock);
881 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
882 case 0:
883 next = 1 << 9;
884 break;
885 case 1:
886 next = 1 << 13;
887 break;
888 case 2:
889 next = 1 << 17;
890 break;
891 case 3:
892 next = 1 << 21;
893 break;
894 default:
895 /* Cannot occur, but makes gcc happy */
896 return;
897 }
898 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq);
899 if (next == now)
900 next++;
901 qemu_mod_timer(ppc40x_timer->fit_timer, next);
902 env->spr[SPR_40x_TSR] |= 1 << 26;
903 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
904 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
905 }
906 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
907 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
908 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
909 }
910
911 /* Programmable interval timer */
912 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
913 {
914 ppc40x_timer_t *ppc40x_timer;
915 uint64_t now, next;
916
917 ppc40x_timer = tb_env->opaque;
918 if (ppc40x_timer->pit_reload <= 1 ||
919 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
920 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
921 /* Stop PIT */
922 LOG_TB("%s: stop PIT\n", __func__);
923 qemu_del_timer(tb_env->decr_timer);
924 } else {
925 LOG_TB("%s: start PIT %016" PRIx64 "\n",
926 __func__, ppc40x_timer->pit_reload);
927 now = qemu_get_clock_ns(vm_clock);
928 next = now + muldiv64(ppc40x_timer->pit_reload,
929 get_ticks_per_sec(), tb_env->decr_freq);
930 if (is_excp)
931 next += tb_env->decr_next - now;
932 if (next == now)
933 next++;
934 qemu_mod_timer(tb_env->decr_timer, next);
935 tb_env->decr_next = next;
936 }
937 }
938
939 static void cpu_4xx_pit_cb (void *opaque)
940 {
941 PowerPCCPU *cpu;
942 CPUPPCState *env;
943 ppc_tb_t *tb_env;
944 ppc40x_timer_t *ppc40x_timer;
945
946 env = opaque;
947 cpu = ppc_env_get_cpu(env);
948 tb_env = env->tb_env;
949 ppc40x_timer = tb_env->opaque;
950 env->spr[SPR_40x_TSR] |= 1 << 27;
951 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
952 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
953 }
954 start_stop_pit(env, tb_env, 1);
955 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
956 "%016" PRIx64 "\n", __func__,
957 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
958 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
959 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
960 ppc40x_timer->pit_reload);
961 }
962
963 /* Watchdog timer */
964 static void cpu_4xx_wdt_cb (void *opaque)
965 {
966 PowerPCCPU *cpu;
967 CPUPPCState *env;
968 ppc_tb_t *tb_env;
969 ppc40x_timer_t *ppc40x_timer;
970 uint64_t now, next;
971
972 env = opaque;
973 cpu = ppc_env_get_cpu(env);
974 tb_env = env->tb_env;
975 ppc40x_timer = tb_env->opaque;
976 now = qemu_get_clock_ns(vm_clock);
977 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
978 case 0:
979 next = 1 << 17;
980 break;
981 case 1:
982 next = 1 << 21;
983 break;
984 case 2:
985 next = 1 << 25;
986 break;
987 case 3:
988 next = 1 << 29;
989 break;
990 default:
991 /* Cannot occur, but makes gcc happy */
992 return;
993 }
994 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq);
995 if (next == now)
996 next++;
997 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
998 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
999 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1000 case 0x0:
1001 case 0x1:
1002 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
1003 ppc40x_timer->wdt_next = next;
1004 env->spr[SPR_40x_TSR] |= 1 << 31;
1005 break;
1006 case 0x2:
1007 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
1008 ppc40x_timer->wdt_next = next;
1009 env->spr[SPR_40x_TSR] |= 1 << 30;
1010 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1011 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1012 }
1013 break;
1014 case 0x3:
1015 env->spr[SPR_40x_TSR] &= ~0x30000000;
1016 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1017 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1018 case 0x0:
1019 /* No reset */
1020 break;
1021 case 0x1: /* Core reset */
1022 ppc40x_core_reset(cpu);
1023 break;
1024 case 0x2: /* Chip reset */
1025 ppc40x_chip_reset(cpu);
1026 break;
1027 case 0x3: /* System reset */
1028 ppc40x_system_reset(cpu);
1029 break;
1030 }
1031 }
1032 }
1033
1034 void store_40x_pit (CPUPPCState *env, target_ulong val)
1035 {
1036 ppc_tb_t *tb_env;
1037 ppc40x_timer_t *ppc40x_timer;
1038
1039 tb_env = env->tb_env;
1040 ppc40x_timer = tb_env->opaque;
1041 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1042 ppc40x_timer->pit_reload = val;
1043 start_stop_pit(env, tb_env, 0);
1044 }
1045
1046 target_ulong load_40x_pit (CPUPPCState *env)
1047 {
1048 return cpu_ppc_load_decr(env);
1049 }
1050
1051 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1052 {
1053 CPUPPCState *env = opaque;
1054 ppc_tb_t *tb_env = env->tb_env;
1055
1056 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1057 freq);
1058 tb_env->tb_freq = freq;
1059 tb_env->decr_freq = freq;
1060 /* XXX: we should also update all timers */
1061 }
1062
1063 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1064 unsigned int decr_excp)
1065 {
1066 ppc_tb_t *tb_env;
1067 ppc40x_timer_t *ppc40x_timer;
1068
1069 tb_env = g_malloc0(sizeof(ppc_tb_t));
1070 env->tb_env = tb_env;
1071 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1072 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1073 tb_env->tb_freq = freq;
1074 tb_env->decr_freq = freq;
1075 tb_env->opaque = ppc40x_timer;
1076 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1077 if (ppc40x_timer != NULL) {
1078 /* We use decr timer for PIT */
1079 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
1080 ppc40x_timer->fit_timer =
1081 qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
1082 ppc40x_timer->wdt_timer =
1083 qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
1084 ppc40x_timer->decr_excp = decr_excp;
1085 }
1086
1087 return &ppc_40x_set_tb_clk;
1088 }
1089
1090 /*****************************************************************************/
1091 /* Embedded PowerPC Device Control Registers */
1092 typedef struct ppc_dcrn_t ppc_dcrn_t;
1093 struct ppc_dcrn_t {
1094 dcr_read_cb dcr_read;
1095 dcr_write_cb dcr_write;
1096 void *opaque;
1097 };
1098
1099 /* XXX: on 460, DCR addresses are 32 bits wide,
1100 * using DCRIPR to get the 22 upper bits of the DCR address
1101 */
1102 #define DCRN_NB 1024
1103 struct ppc_dcr_t {
1104 ppc_dcrn_t dcrn[DCRN_NB];
1105 int (*read_error)(int dcrn);
1106 int (*write_error)(int dcrn);
1107 };
1108
1109 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1110 {
1111 ppc_dcrn_t *dcr;
1112
1113 if (dcrn < 0 || dcrn >= DCRN_NB)
1114 goto error;
1115 dcr = &dcr_env->dcrn[dcrn];
1116 if (dcr->dcr_read == NULL)
1117 goto error;
1118 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1119
1120 return 0;
1121
1122 error:
1123 if (dcr_env->read_error != NULL)
1124 return (*dcr_env->read_error)(dcrn);
1125
1126 return -1;
1127 }
1128
1129 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1130 {
1131 ppc_dcrn_t *dcr;
1132
1133 if (dcrn < 0 || dcrn >= DCRN_NB)
1134 goto error;
1135 dcr = &dcr_env->dcrn[dcrn];
1136 if (dcr->dcr_write == NULL)
1137 goto error;
1138 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1139
1140 return 0;
1141
1142 error:
1143 if (dcr_env->write_error != NULL)
1144 return (*dcr_env->write_error)(dcrn);
1145
1146 return -1;
1147 }
1148
1149 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1150 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1151 {
1152 ppc_dcr_t *dcr_env;
1153 ppc_dcrn_t *dcr;
1154
1155 dcr_env = env->dcr_env;
1156 if (dcr_env == NULL)
1157 return -1;
1158 if (dcrn < 0 || dcrn >= DCRN_NB)
1159 return -1;
1160 dcr = &dcr_env->dcrn[dcrn];
1161 if (dcr->opaque != NULL ||
1162 dcr->dcr_read != NULL ||
1163 dcr->dcr_write != NULL)
1164 return -1;
1165 dcr->opaque = opaque;
1166 dcr->dcr_read = dcr_read;
1167 dcr->dcr_write = dcr_write;
1168
1169 return 0;
1170 }
1171
1172 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1173 int (*write_error)(int dcrn))
1174 {
1175 ppc_dcr_t *dcr_env;
1176
1177 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1178 dcr_env->read_error = read_error;
1179 dcr_env->write_error = write_error;
1180 env->dcr_env = dcr_env;
1181
1182 return 0;
1183 }
1184
1185 /*****************************************************************************/
1186 /* Debug port */
1187 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1188 {
1189 addr &= 0xF;
1190 switch (addr) {
1191 case 0:
1192 printf("%c", val);
1193 break;
1194 case 1:
1195 printf("\n");
1196 fflush(stdout);
1197 break;
1198 case 2:
1199 printf("Set loglevel to %04" PRIx32 "\n", val);
1200 qemu_set_log(val | 0x100);
1201 break;
1202 }
1203 }
1204
1205 /*****************************************************************************/
1206 /* NVRAM helpers */
1207 static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
1208 {
1209 return (*nvram->read_fn)(nvram->opaque, addr);
1210 }
1211
1212 static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
1213 {
1214 (*nvram->write_fn)(nvram->opaque, addr, val);
1215 }
1216
1217 static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value)
1218 {
1219 nvram_write(nvram, addr, value);
1220 }
1221
1222 static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr)
1223 {
1224 return nvram_read(nvram, addr);
1225 }
1226
1227 static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value)
1228 {
1229 nvram_write(nvram, addr, value >> 8);
1230 nvram_write(nvram, addr + 1, value & 0xFF);
1231 }
1232
1233 static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr)
1234 {
1235 uint16_t tmp;
1236
1237 tmp = nvram_read(nvram, addr) << 8;
1238 tmp |= nvram_read(nvram, addr + 1);
1239
1240 return tmp;
1241 }
1242
1243 static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value)
1244 {
1245 nvram_write(nvram, addr, value >> 24);
1246 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
1247 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
1248 nvram_write(nvram, addr + 3, value & 0xFF);
1249 }
1250
1251 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
1252 {
1253 uint32_t tmp;
1254
1255 tmp = nvram_read(nvram, addr) << 24;
1256 tmp |= nvram_read(nvram, addr + 1) << 16;
1257 tmp |= nvram_read(nvram, addr + 2) << 8;
1258 tmp |= nvram_read(nvram, addr + 3);
1259
1260 return tmp;
1261 }
1262
1263 static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str,
1264 uint32_t max)
1265 {
1266 int i;
1267
1268 for (i = 0; i < max && str[i] != '\0'; i++) {
1269 nvram_write(nvram, addr + i, str[i]);
1270 }
1271 nvram_write(nvram, addr + i, str[i]);
1272 nvram_write(nvram, addr + max - 1, '\0');
1273 }
1274
1275 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
1276 {
1277 int i;
1278
1279 memset(dst, 0, max);
1280 for (i = 0; i < max; i++) {
1281 dst[i] = NVRAM_get_byte(nvram, addr + i);
1282 if (dst[i] == '\0')
1283 break;
1284 }
1285
1286 return i;
1287 }
1288
1289 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1290 {
1291 uint16_t tmp;
1292 uint16_t pd, pd1, pd2;
1293
1294 tmp = prev >> 8;
1295 pd = prev ^ value;
1296 pd1 = pd & 0x000F;
1297 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1298 tmp ^= (pd1 << 3) | (pd1 << 8);
1299 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1300
1301 return tmp;
1302 }
1303
1304 static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
1305 {
1306 uint32_t i;
1307 uint16_t crc = 0xFFFF;
1308 int odd;
1309
1310 odd = count & 1;
1311 count &= ~1;
1312 for (i = 0; i != count; i++) {
1313 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1314 }
1315 if (odd) {
1316 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1317 }
1318
1319 return crc;
1320 }
1321
1322 #define CMDLINE_ADDR 0x017ff000
1323
1324 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1325 const char *arch,
1326 uint32_t RAM_size, int boot_device,
1327 uint32_t kernel_image, uint32_t kernel_size,
1328 const char *cmdline,
1329 uint32_t initrd_image, uint32_t initrd_size,
1330 uint32_t NVRAM_image,
1331 int width, int height, int depth)
1332 {
1333 uint16_t crc;
1334
1335 /* Set parameters for Open Hack'Ware BIOS */
1336 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1337 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1338 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1339 NVRAM_set_string(nvram, 0x20, arch, 16);
1340 NVRAM_set_lword(nvram, 0x30, RAM_size);
1341 NVRAM_set_byte(nvram, 0x34, boot_device);
1342 NVRAM_set_lword(nvram, 0x38, kernel_image);
1343 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1344 if (cmdline) {
1345 /* XXX: put the cmdline in NVRAM too ? */
1346 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
1347 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1348 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1349 } else {
1350 NVRAM_set_lword(nvram, 0x40, 0);
1351 NVRAM_set_lword(nvram, 0x44, 0);
1352 }
1353 NVRAM_set_lword(nvram, 0x48, initrd_image);
1354 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1355 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1356
1357 NVRAM_set_word(nvram, 0x54, width);
1358 NVRAM_set_word(nvram, 0x56, height);
1359 NVRAM_set_word(nvram, 0x58, depth);
1360 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1361 NVRAM_set_word(nvram, 0xFC, crc);
1362
1363 return 0;
1364 }
Qemu copy for testing