2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
30 #include "hw/loader.h"
31 #include "sysemu/kvm.h"
34 //#define PPC_DEBUG_IRQ
35 //#define PPC_DEBUG_TB
38 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
40 # define LOG_IRQ(...) do { } while (0)
45 # define LOG_TB(...) qemu_log(__VA_ARGS__)
47 # define LOG_TB(...) do { } while (0)
50 static void cpu_ppc_tb_stop (CPUPPCState
*env
);
51 static void cpu_ppc_tb_start (CPUPPCState
*env
);
53 void ppc_set_irq(PowerPCCPU
*cpu
, int n_IRQ
, int level
)
55 CPUPPCState
*env
= &cpu
->env
;
56 unsigned int old_pending
= env
->pending_interrupts
;
59 env
->pending_interrupts
|= 1 << n_IRQ
;
60 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
62 env
->pending_interrupts
&= ~(1 << n_IRQ
);
63 if (env
->pending_interrupts
== 0)
64 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
67 if (old_pending
!= env
->pending_interrupts
) {
69 kvmppc_set_interrupt(cpu
, n_IRQ
, level
);
73 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
74 "req %08x\n", __func__
, env
, n_IRQ
, level
,
75 env
->pending_interrupts
, CPU(cpu
)->interrupt_request
);
78 /* PowerPC 6xx / 7xx internal IRQ controller */
79 static void ppc6xx_set_irq(void *opaque
, int pin
, int level
)
81 PowerPCCPU
*cpu
= opaque
;
82 CPUPPCState
*env
= &cpu
->env
;
85 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
87 cur_level
= (env
->irq_input_state
>> pin
) & 1;
88 /* Don't generate spurious events */
89 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
90 CPUState
*cs
= CPU(cpu
);
93 case PPC6xx_INPUT_TBEN
:
94 /* Level sensitive - active high */
95 LOG_IRQ("%s: %s the time base\n",
96 __func__
, level
? "start" : "stop");
98 cpu_ppc_tb_start(env
);
100 cpu_ppc_tb_stop(env
);
102 case PPC6xx_INPUT_INT
:
103 /* Level sensitive - active high */
104 LOG_IRQ("%s: set the external IRQ state to %d\n",
106 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
108 case PPC6xx_INPUT_SMI
:
109 /* Level sensitive - active high */
110 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
112 ppc_set_irq(cpu
, PPC_INTERRUPT_SMI
, level
);
114 case PPC6xx_INPUT_MCP
:
115 /* Negative edge sensitive */
116 /* XXX: TODO: actual reaction may depends on HID0 status
117 * 603/604/740/750: check HID0[EMCP]
119 if (cur_level
== 1 && level
== 0) {
120 LOG_IRQ("%s: raise machine check state\n",
122 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, 1);
125 case PPC6xx_INPUT_CKSTP_IN
:
126 /* Level sensitive - active low */
127 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
128 /* XXX: Note that the only way to restart the CPU is to reset it */
130 LOG_IRQ("%s: stop the CPU\n", __func__
);
134 case PPC6xx_INPUT_HRESET
:
135 /* Level sensitive - active low */
137 LOG_IRQ("%s: reset the CPU\n", __func__
);
138 cpu_interrupt(env
, CPU_INTERRUPT_RESET
);
141 case PPC6xx_INPUT_SRESET
:
142 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
144 ppc_set_irq(cpu
, PPC_INTERRUPT_RESET
, level
);
147 /* Unknown pin - do nothing */
148 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
152 env
->irq_input_state
|= 1 << pin
;
154 env
->irq_input_state
&= ~(1 << pin
);
158 void ppc6xx_irq_init(CPUPPCState
*env
)
160 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
162 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc6xx_set_irq
, cpu
,
166 #if defined(TARGET_PPC64)
167 /* PowerPC 970 internal IRQ controller */
168 static void ppc970_set_irq(void *opaque
, int pin
, int level
)
170 PowerPCCPU
*cpu
= opaque
;
171 CPUPPCState
*env
= &cpu
->env
;
174 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
176 cur_level
= (env
->irq_input_state
>> pin
) & 1;
177 /* Don't generate spurious events */
178 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
179 CPUState
*cs
= CPU(cpu
);
182 case PPC970_INPUT_INT
:
183 /* Level sensitive - active high */
184 LOG_IRQ("%s: set the external IRQ state to %d\n",
186 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
188 case PPC970_INPUT_THINT
:
189 /* Level sensitive - active high */
190 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__
,
192 ppc_set_irq(cpu
, PPC_INTERRUPT_THERM
, level
);
194 case PPC970_INPUT_MCP
:
195 /* Negative edge sensitive */
196 /* XXX: TODO: actual reaction may depends on HID0 status
197 * 603/604/740/750: check HID0[EMCP]
199 if (cur_level
== 1 && level
== 0) {
200 LOG_IRQ("%s: raise machine check state\n",
202 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, 1);
205 case PPC970_INPUT_CKSTP
:
206 /* Level sensitive - active low */
207 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
209 LOG_IRQ("%s: stop the CPU\n", __func__
);
212 LOG_IRQ("%s: restart the CPU\n", __func__
);
217 case PPC970_INPUT_HRESET
:
218 /* Level sensitive - active low */
220 cpu_interrupt(env
, CPU_INTERRUPT_RESET
);
223 case PPC970_INPUT_SRESET
:
224 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
226 ppc_set_irq(cpu
, PPC_INTERRUPT_RESET
, level
);
228 case PPC970_INPUT_TBEN
:
229 LOG_IRQ("%s: set the TBEN state to %d\n", __func__
,
234 /* Unknown pin - do nothing */
235 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
239 env
->irq_input_state
|= 1 << pin
;
241 env
->irq_input_state
&= ~(1 << pin
);
245 void ppc970_irq_init(CPUPPCState
*env
)
247 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
249 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc970_set_irq
, cpu
,
253 /* POWER7 internal IRQ controller */
254 static void power7_set_irq(void *opaque
, int pin
, int level
)
256 PowerPCCPU
*cpu
= opaque
;
257 CPUPPCState
*env
= &cpu
->env
;
259 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
263 case POWER7_INPUT_INT
:
264 /* Level sensitive - active high */
265 LOG_IRQ("%s: set the external IRQ state to %d\n",
267 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
270 /* Unknown pin - do nothing */
271 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
275 env
->irq_input_state
|= 1 << pin
;
277 env
->irq_input_state
&= ~(1 << pin
);
281 void ppcPOWER7_irq_init(CPUPPCState
*env
)
283 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
285 env
->irq_inputs
= (void **)qemu_allocate_irqs(&power7_set_irq
, cpu
,
288 #endif /* defined(TARGET_PPC64) */
290 /* PowerPC 40x internal IRQ controller */
291 static void ppc40x_set_irq(void *opaque
, int pin
, int level
)
293 PowerPCCPU
*cpu
= opaque
;
294 CPUPPCState
*env
= &cpu
->env
;
297 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
299 cur_level
= (env
->irq_input_state
>> pin
) & 1;
300 /* Don't generate spurious events */
301 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
302 CPUState
*cs
= CPU(cpu
);
305 case PPC40x_INPUT_RESET_SYS
:
307 LOG_IRQ("%s: reset the PowerPC system\n",
309 ppc40x_system_reset(cpu
);
312 case PPC40x_INPUT_RESET_CHIP
:
314 LOG_IRQ("%s: reset the PowerPC chip\n", __func__
);
315 ppc40x_chip_reset(cpu
);
318 case PPC40x_INPUT_RESET_CORE
:
319 /* XXX: TODO: update DBSR[MRR] */
321 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
322 ppc40x_core_reset(cpu
);
325 case PPC40x_INPUT_CINT
:
326 /* Level sensitive - active high */
327 LOG_IRQ("%s: set the critical IRQ state to %d\n",
329 ppc_set_irq(cpu
, PPC_INTERRUPT_CEXT
, level
);
331 case PPC40x_INPUT_INT
:
332 /* Level sensitive - active high */
333 LOG_IRQ("%s: set the external IRQ state to %d\n",
335 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
337 case PPC40x_INPUT_HALT
:
338 /* Level sensitive - active low */
340 LOG_IRQ("%s: stop the CPU\n", __func__
);
343 LOG_IRQ("%s: restart the CPU\n", __func__
);
348 case PPC40x_INPUT_DEBUG
:
349 /* Level sensitive - active high */
350 LOG_IRQ("%s: set the debug pin state to %d\n",
352 ppc_set_irq(cpu
, PPC_INTERRUPT_DEBUG
, level
);
355 /* Unknown pin - do nothing */
356 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
360 env
->irq_input_state
|= 1 << pin
;
362 env
->irq_input_state
&= ~(1 << pin
);
366 void ppc40x_irq_init(CPUPPCState
*env
)
368 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
370 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc40x_set_irq
,
371 cpu
, PPC40x_INPUT_NB
);
374 /* PowerPC E500 internal IRQ controller */
375 static void ppce500_set_irq(void *opaque
, int pin
, int level
)
377 PowerPCCPU
*cpu
= opaque
;
378 CPUPPCState
*env
= &cpu
->env
;
381 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
383 cur_level
= (env
->irq_input_state
>> pin
) & 1;
384 /* Don't generate spurious events */
385 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
387 case PPCE500_INPUT_MCK
:
389 LOG_IRQ("%s: reset the PowerPC system\n",
391 qemu_system_reset_request();
394 case PPCE500_INPUT_RESET_CORE
:
396 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
397 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, level
);
400 case PPCE500_INPUT_CINT
:
401 /* Level sensitive - active high */
402 LOG_IRQ("%s: set the critical IRQ state to %d\n",
404 ppc_set_irq(cpu
, PPC_INTERRUPT_CEXT
, level
);
406 case PPCE500_INPUT_INT
:
407 /* Level sensitive - active high */
408 LOG_IRQ("%s: set the core IRQ state to %d\n",
410 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
412 case PPCE500_INPUT_DEBUG
:
413 /* Level sensitive - active high */
414 LOG_IRQ("%s: set the debug pin state to %d\n",
416 ppc_set_irq(cpu
, PPC_INTERRUPT_DEBUG
, level
);
419 /* Unknown pin - do nothing */
420 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
424 env
->irq_input_state
|= 1 << pin
;
426 env
->irq_input_state
&= ~(1 << pin
);
430 void ppce500_irq_init(CPUPPCState
*env
)
432 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
434 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppce500_set_irq
,
435 cpu
, PPCE500_INPUT_NB
);
438 /* Enable or Disable the E500 EPR capability */
439 void ppce500_set_mpic_proxy(bool enabled
)
443 for (env
= first_cpu
; env
!= NULL
; env
= env
->next_cpu
) {
444 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
445 CPUState
*cs
= CPU(cpu
);
447 env
->mpic_proxy
= enabled
;
449 kvmppc_set_mpic_proxy(POWERPC_CPU(cs
), enabled
);
454 /*****************************************************************************/
455 /* PowerPC time base and decrementer emulation */
457 uint64_t cpu_ppc_get_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
, int64_t tb_offset
)
459 /* TB time in tb periods */
460 return muldiv64(vmclk
, tb_env
->tb_freq
, get_ticks_per_sec()) + tb_offset
;
463 uint64_t cpu_ppc_load_tbl (CPUPPCState
*env
)
465 ppc_tb_t
*tb_env
= env
->tb_env
;
469 return env
->spr
[SPR_TBL
];
472 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
473 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
478 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState
*env
)
480 ppc_tb_t
*tb_env
= env
->tb_env
;
483 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
484 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
489 uint32_t cpu_ppc_load_tbu (CPUPPCState
*env
)
492 return env
->spr
[SPR_TBU
];
495 return _cpu_ppc_load_tbu(env
);
498 static inline void cpu_ppc_store_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
,
499 int64_t *tb_offsetp
, uint64_t value
)
501 *tb_offsetp
= value
- muldiv64(vmclk
, tb_env
->tb_freq
, get_ticks_per_sec());
502 LOG_TB("%s: tb %016" PRIx64
" offset %08" PRIx64
"\n",
503 __func__
, value
, *tb_offsetp
);
506 void cpu_ppc_store_tbl (CPUPPCState
*env
, uint32_t value
)
508 ppc_tb_t
*tb_env
= env
->tb_env
;
511 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
512 tb
&= 0xFFFFFFFF00000000ULL
;
513 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
514 &tb_env
->tb_offset
, tb
| (uint64_t)value
);
517 static inline void _cpu_ppc_store_tbu(CPUPPCState
*env
, uint32_t value
)
519 ppc_tb_t
*tb_env
= env
->tb_env
;
522 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->tb_offset
);
523 tb
&= 0x00000000FFFFFFFFULL
;
524 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
525 &tb_env
->tb_offset
, ((uint64_t)value
<< 32) | tb
);
528 void cpu_ppc_store_tbu (CPUPPCState
*env
, uint32_t value
)
530 _cpu_ppc_store_tbu(env
, value
);
533 uint64_t cpu_ppc_load_atbl (CPUPPCState
*env
)
535 ppc_tb_t
*tb_env
= env
->tb_env
;
538 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
539 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
544 uint32_t cpu_ppc_load_atbu (CPUPPCState
*env
)
546 ppc_tb_t
*tb_env
= env
->tb_env
;
549 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
550 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
555 void cpu_ppc_store_atbl (CPUPPCState
*env
, uint32_t value
)
557 ppc_tb_t
*tb_env
= env
->tb_env
;
560 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
561 tb
&= 0xFFFFFFFF00000000ULL
;
562 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
563 &tb_env
->atb_offset
, tb
| (uint64_t)value
);
566 void cpu_ppc_store_atbu (CPUPPCState
*env
, uint32_t value
)
568 ppc_tb_t
*tb_env
= env
->tb_env
;
571 tb
= cpu_ppc_get_tb(tb_env
, qemu_get_clock_ns(vm_clock
), tb_env
->atb_offset
);
572 tb
&= 0x00000000FFFFFFFFULL
;
573 cpu_ppc_store_tb(tb_env
, qemu_get_clock_ns(vm_clock
),
574 &tb_env
->atb_offset
, ((uint64_t)value
<< 32) | tb
);
577 static void cpu_ppc_tb_stop (CPUPPCState
*env
)
579 ppc_tb_t
*tb_env
= env
->tb_env
;
580 uint64_t tb
, atb
, vmclk
;
582 /* If the time base is already frozen, do nothing */
583 if (tb_env
->tb_freq
!= 0) {
584 vmclk
= qemu_get_clock_ns(vm_clock
);
585 /* Get the time base */
586 tb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->tb_offset
);
587 /* Get the alternate time base */
588 atb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->atb_offset
);
589 /* Store the time base value (ie compute the current offset) */
590 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
591 /* Store the alternate time base value (compute the current offset) */
592 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
593 /* Set the time base frequency to zero */
595 /* Now, the time bases are frozen to tb_offset / atb_offset value */
599 static void cpu_ppc_tb_start (CPUPPCState
*env
)
601 ppc_tb_t
*tb_env
= env
->tb_env
;
602 uint64_t tb
, atb
, vmclk
;
604 /* If the time base is not frozen, do nothing */
605 if (tb_env
->tb_freq
== 0) {
606 vmclk
= qemu_get_clock_ns(vm_clock
);
607 /* Get the time base from tb_offset */
608 tb
= tb_env
->tb_offset
;
609 /* Get the alternate time base from atb_offset */
610 atb
= tb_env
->atb_offset
;
611 /* Restore the tb frequency from the decrementer frequency */
612 tb_env
->tb_freq
= tb_env
->decr_freq
;
613 /* Store the time base value */
614 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
615 /* Store the alternate time base value */
616 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
620 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState
*env
, uint64_t next
)
622 ppc_tb_t
*tb_env
= env
->tb_env
;
626 diff
= next
- qemu_get_clock_ns(vm_clock
);
628 decr
= muldiv64(diff
, tb_env
->decr_freq
, get_ticks_per_sec());
629 } else if (tb_env
->flags
& PPC_TIMER_BOOKE
) {
632 decr
= -muldiv64(-diff
, tb_env
->decr_freq
, get_ticks_per_sec());
634 LOG_TB("%s: %08" PRIx32
"\n", __func__
, decr
);
639 uint32_t cpu_ppc_load_decr (CPUPPCState
*env
)
641 ppc_tb_t
*tb_env
= env
->tb_env
;
644 return env
->spr
[SPR_DECR
];
647 return _cpu_ppc_load_decr(env
, tb_env
->decr_next
);
650 uint32_t cpu_ppc_load_hdecr (CPUPPCState
*env
)
652 ppc_tb_t
*tb_env
= env
->tb_env
;
654 return _cpu_ppc_load_decr(env
, tb_env
->hdecr_next
);
657 uint64_t cpu_ppc_load_purr (CPUPPCState
*env
)
659 ppc_tb_t
*tb_env
= env
->tb_env
;
662 diff
= qemu_get_clock_ns(vm_clock
) - tb_env
->purr_start
;
664 return tb_env
->purr_load
+ muldiv64(diff
, tb_env
->tb_freq
, get_ticks_per_sec());
667 /* When decrementer expires,
668 * all we need to do is generate or queue a CPU exception
670 static inline void cpu_ppc_decr_excp(PowerPCCPU
*cpu
)
673 LOG_TB("raise decrementer exception\n");
674 ppc_set_irq(cpu
, PPC_INTERRUPT_DECR
, 1);
677 static inline void cpu_ppc_hdecr_excp(PowerPCCPU
*cpu
)
680 LOG_TB("raise decrementer exception\n");
681 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 1);
684 static void __cpu_ppc_store_decr(PowerPCCPU
*cpu
, uint64_t *nextp
,
685 struct QEMUTimer
*timer
,
686 void (*raise_excp
)(PowerPCCPU
*),
687 uint32_t decr
, uint32_t value
,
690 CPUPPCState
*env
= &cpu
->env
;
691 ppc_tb_t
*tb_env
= env
->tb_env
;
694 LOG_TB("%s: %08" PRIx32
" => %08" PRIx32
"\n", __func__
,
698 /* KVM handles decrementer exceptions, we don't need our own timer */
702 now
= qemu_get_clock_ns(vm_clock
);
703 next
= now
+ muldiv64(value
, get_ticks_per_sec(), tb_env
->decr_freq
);
705 next
+= *nextp
- now
;
712 qemu_mod_timer(timer
, next
);
714 /* If we set a negative value and the decrementer was positive, raise an
717 if ((tb_env
->flags
& PPC_DECR_UNDERFLOW_TRIGGERED
)
718 && (value
& 0x80000000)
719 && !(decr
& 0x80000000)) {
724 static inline void _cpu_ppc_store_decr(PowerPCCPU
*cpu
, uint32_t decr
,
725 uint32_t value
, int is_excp
)
727 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
729 __cpu_ppc_store_decr(cpu
, &tb_env
->decr_next
, tb_env
->decr_timer
,
730 &cpu_ppc_decr_excp
, decr
, value
, is_excp
);
733 void cpu_ppc_store_decr (CPUPPCState
*env
, uint32_t value
)
735 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
737 _cpu_ppc_store_decr(cpu
, cpu_ppc_load_decr(env
), value
, 0);
740 static void cpu_ppc_decr_cb(void *opaque
)
742 PowerPCCPU
*cpu
= opaque
;
744 _cpu_ppc_store_decr(cpu
, 0x00000000, 0xFFFFFFFF, 1);
747 static inline void _cpu_ppc_store_hdecr(PowerPCCPU
*cpu
, uint32_t hdecr
,
748 uint32_t value
, int is_excp
)
750 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
752 if (tb_env
->hdecr_timer
!= NULL
) {
753 __cpu_ppc_store_decr(cpu
, &tb_env
->hdecr_next
, tb_env
->hdecr_timer
,
754 &cpu_ppc_hdecr_excp
, hdecr
, value
, is_excp
);
758 void cpu_ppc_store_hdecr (CPUPPCState
*env
, uint32_t value
)
760 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
762 _cpu_ppc_store_hdecr(cpu
, cpu_ppc_load_hdecr(env
), value
, 0);
765 static void cpu_ppc_hdecr_cb(void *opaque
)
767 PowerPCCPU
*cpu
= opaque
;
769 _cpu_ppc_store_hdecr(cpu
, 0x00000000, 0xFFFFFFFF, 1);
772 static void cpu_ppc_store_purr(PowerPCCPU
*cpu
, uint64_t value
)
774 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
776 tb_env
->purr_load
= value
;
777 tb_env
->purr_start
= qemu_get_clock_ns(vm_clock
);
780 static void cpu_ppc_set_tb_clk (void *opaque
, uint32_t freq
)
782 CPUPPCState
*env
= opaque
;
783 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
784 ppc_tb_t
*tb_env
= env
->tb_env
;
786 tb_env
->tb_freq
= freq
;
787 tb_env
->decr_freq
= freq
;
788 /* There is a bug in Linux 2.4 kernels:
789 * if a decrementer exception is pending when it enables msr_ee at startup,
790 * it's not ready to handle it...
792 _cpu_ppc_store_decr(cpu
, 0xFFFFFFFF, 0xFFFFFFFF, 0);
793 _cpu_ppc_store_hdecr(cpu
, 0xFFFFFFFF, 0xFFFFFFFF, 0);
794 cpu_ppc_store_purr(cpu
, 0x0000000000000000ULL
);
797 /* Set up (once) timebase frequency (in Hz) */
798 clk_setup_cb
cpu_ppc_tb_init (CPUPPCState
*env
, uint32_t freq
)
800 PowerPCCPU
*cpu
= ppc_env_get_cpu(env
);
803 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
804 env
->tb_env
= tb_env
;
805 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
806 /* Create new timer */
807 tb_env
->decr_timer
= qemu_new_timer_ns(vm_clock
, &cpu_ppc_decr_cb
, cpu
);
809 /* XXX: find a suitable condition to enable the hypervisor decrementer
811 tb_env
->hdecr_timer
= qemu_new_timer_ns(vm_clock
, &cpu_ppc_hdecr_cb
,
814 tb_env
->hdecr_timer
= NULL
;
816 cpu_ppc_set_tb_clk(env
, freq
);
818 return &cpu_ppc_set_tb_clk
;
821 /* Specific helpers for POWER & PowerPC 601 RTC */
823 static clk_setup_cb
cpu_ppc601_rtc_init (CPUPPCState
*env
)
825 return cpu_ppc_tb_init(env
, 7812500);
829 void cpu_ppc601_store_rtcu (CPUPPCState
*env
, uint32_t value
)
831 _cpu_ppc_store_tbu(env
, value
);
834 uint32_t cpu_ppc601_load_rtcu (CPUPPCState
*env
)
836 return _cpu_ppc_load_tbu(env
);
839 void cpu_ppc601_store_rtcl (CPUPPCState
*env
, uint32_t value
)
841 cpu_ppc_store_tbl(env
, value
& 0x3FFFFF80);
844 uint32_t cpu_ppc601_load_rtcl (CPUPPCState
*env
)
846 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
849 /*****************************************************************************/
850 /* PowerPC 40x timers */
853 typedef struct ppc40x_timer_t ppc40x_timer_t
;
854 struct ppc40x_timer_t
{
855 uint64_t pit_reload
; /* PIT auto-reload value */
856 uint64_t fit_next
; /* Tick for next FIT interrupt */
857 struct QEMUTimer
*fit_timer
;
858 uint64_t wdt_next
; /* Tick for next WDT interrupt */
859 struct QEMUTimer
*wdt_timer
;
861 /* 405 have the PIT, 440 have a DECR. */
862 unsigned int decr_excp
;
865 /* Fixed interval timer */
866 static void cpu_4xx_fit_cb (void *opaque
)
871 ppc40x_timer_t
*ppc40x_timer
;
875 cpu
= ppc_env_get_cpu(env
);
876 tb_env
= env
->tb_env
;
877 ppc40x_timer
= tb_env
->opaque
;
878 now
= qemu_get_clock_ns(vm_clock
);
879 switch ((env
->spr
[SPR_40x_TCR
] >> 24) & 0x3) {
893 /* Cannot occur, but makes gcc happy */
896 next
= now
+ muldiv64(next
, get_ticks_per_sec(), tb_env
->tb_freq
);
899 qemu_mod_timer(ppc40x_timer
->fit_timer
, next
);
900 env
->spr
[SPR_40x_TSR
] |= 1 << 26;
901 if ((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1) {
902 ppc_set_irq(cpu
, PPC_INTERRUPT_FIT
, 1);
904 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
905 (int)((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1),
906 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
909 /* Programmable interval timer */
910 static void start_stop_pit (CPUPPCState
*env
, ppc_tb_t
*tb_env
, int is_excp
)
912 ppc40x_timer_t
*ppc40x_timer
;
915 ppc40x_timer
= tb_env
->opaque
;
916 if (ppc40x_timer
->pit_reload
<= 1 ||
917 !((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) ||
918 (is_excp
&& !((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1))) {
920 LOG_TB("%s: stop PIT\n", __func__
);
921 qemu_del_timer(tb_env
->decr_timer
);
923 LOG_TB("%s: start PIT %016" PRIx64
"\n",
924 __func__
, ppc40x_timer
->pit_reload
);
925 now
= qemu_get_clock_ns(vm_clock
);
926 next
= now
+ muldiv64(ppc40x_timer
->pit_reload
,
927 get_ticks_per_sec(), tb_env
->decr_freq
);
929 next
+= tb_env
->decr_next
- now
;
932 qemu_mod_timer(tb_env
->decr_timer
, next
);
933 tb_env
->decr_next
= next
;
937 static void cpu_4xx_pit_cb (void *opaque
)
942 ppc40x_timer_t
*ppc40x_timer
;
945 cpu
= ppc_env_get_cpu(env
);
946 tb_env
= env
->tb_env
;
947 ppc40x_timer
= tb_env
->opaque
;
948 env
->spr
[SPR_40x_TSR
] |= 1 << 27;
949 if ((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) {
950 ppc_set_irq(cpu
, ppc40x_timer
->decr_excp
, 1);
952 start_stop_pit(env
, tb_env
, 1);
953 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
" "
954 "%016" PRIx64
"\n", __func__
,
955 (int)((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1),
956 (int)((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1),
957 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
],
958 ppc40x_timer
->pit_reload
);
962 static void cpu_4xx_wdt_cb (void *opaque
)
967 ppc40x_timer_t
*ppc40x_timer
;
971 cpu
= ppc_env_get_cpu(env
);
972 tb_env
= env
->tb_env
;
973 ppc40x_timer
= tb_env
->opaque
;
974 now
= qemu_get_clock_ns(vm_clock
);
975 switch ((env
->spr
[SPR_40x_TCR
] >> 30) & 0x3) {
989 /* Cannot occur, but makes gcc happy */
992 next
= now
+ muldiv64(next
, get_ticks_per_sec(), tb_env
->decr_freq
);
995 LOG_TB("%s: TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
996 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
997 switch ((env
->spr
[SPR_40x_TSR
] >> 30) & 0x3) {
1000 qemu_mod_timer(ppc40x_timer
->wdt_timer
, next
);
1001 ppc40x_timer
->wdt_next
= next
;
1002 env
->spr
[SPR_40x_TSR
] |= 1 << 31;
1005 qemu_mod_timer(ppc40x_timer
->wdt_timer
, next
);
1006 ppc40x_timer
->wdt_next
= next
;
1007 env
->spr
[SPR_40x_TSR
] |= 1 << 30;
1008 if ((env
->spr
[SPR_40x_TCR
] >> 27) & 0x1) {
1009 ppc_set_irq(cpu
, PPC_INTERRUPT_WDT
, 1);
1013 env
->spr
[SPR_40x_TSR
] &= ~0x30000000;
1014 env
->spr
[SPR_40x_TSR
] |= env
->spr
[SPR_40x_TCR
] & 0x30000000;
1015 switch ((env
->spr
[SPR_40x_TCR
] >> 28) & 0x3) {
1019 case 0x1: /* Core reset */
1020 ppc40x_core_reset(cpu
);
1022 case 0x2: /* Chip reset */
1023 ppc40x_chip_reset(cpu
);
1025 case 0x3: /* System reset */
1026 ppc40x_system_reset(cpu
);
1032 void store_40x_pit (CPUPPCState
*env
, target_ulong val
)
1035 ppc40x_timer_t
*ppc40x_timer
;
1037 tb_env
= env
->tb_env
;
1038 ppc40x_timer
= tb_env
->opaque
;
1039 LOG_TB("%s val" TARGET_FMT_lx
"\n", __func__
, val
);
1040 ppc40x_timer
->pit_reload
= val
;
1041 start_stop_pit(env
, tb_env
, 0);
1044 target_ulong
load_40x_pit (CPUPPCState
*env
)
1046 return cpu_ppc_load_decr(env
);
1049 static void ppc_40x_set_tb_clk (void *opaque
, uint32_t freq
)
1051 CPUPPCState
*env
= opaque
;
1052 ppc_tb_t
*tb_env
= env
->tb_env
;
1054 LOG_TB("%s set new frequency to %" PRIu32
"\n", __func__
,
1056 tb_env
->tb_freq
= freq
;
1057 tb_env
->decr_freq
= freq
;
1058 /* XXX: we should also update all timers */
1061 clk_setup_cb
ppc_40x_timers_init (CPUPPCState
*env
, uint32_t freq
,
1062 unsigned int decr_excp
)
1065 ppc40x_timer_t
*ppc40x_timer
;
1067 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
1068 env
->tb_env
= tb_env
;
1069 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
1070 ppc40x_timer
= g_malloc0(sizeof(ppc40x_timer_t
));
1071 tb_env
->tb_freq
= freq
;
1072 tb_env
->decr_freq
= freq
;
1073 tb_env
->opaque
= ppc40x_timer
;
1074 LOG_TB("%s freq %" PRIu32
"\n", __func__
, freq
);
1075 if (ppc40x_timer
!= NULL
) {
1076 /* We use decr timer for PIT */
1077 tb_env
->decr_timer
= qemu_new_timer_ns(vm_clock
, &cpu_4xx_pit_cb
, env
);
1078 ppc40x_timer
->fit_timer
=
1079 qemu_new_timer_ns(vm_clock
, &cpu_4xx_fit_cb
, env
);
1080 ppc40x_timer
->wdt_timer
=
1081 qemu_new_timer_ns(vm_clock
, &cpu_4xx_wdt_cb
, env
);
1082 ppc40x_timer
->decr_excp
= decr_excp
;
1085 return &ppc_40x_set_tb_clk
;
1088 /*****************************************************************************/
1089 /* Embedded PowerPC Device Control Registers */
1090 typedef struct ppc_dcrn_t ppc_dcrn_t
;
1092 dcr_read_cb dcr_read
;
1093 dcr_write_cb dcr_write
;
1097 /* XXX: on 460, DCR addresses are 32 bits wide,
1098 * using DCRIPR to get the 22 upper bits of the DCR address
1100 #define DCRN_NB 1024
1102 ppc_dcrn_t dcrn
[DCRN_NB
];
1103 int (*read_error
)(int dcrn
);
1104 int (*write_error
)(int dcrn
);
1107 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1111 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1113 dcr
= &dcr_env
->dcrn
[dcrn
];
1114 if (dcr
->dcr_read
== NULL
)
1116 *valp
= (*dcr
->dcr_read
)(dcr
->opaque
, dcrn
);
1121 if (dcr_env
->read_error
!= NULL
)
1122 return (*dcr_env
->read_error
)(dcrn
);
1127 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1131 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1133 dcr
= &dcr_env
->dcrn
[dcrn
];
1134 if (dcr
->dcr_write
== NULL
)
1136 (*dcr
->dcr_write
)(dcr
->opaque
, dcrn
, val
);
1141 if (dcr_env
->write_error
!= NULL
)
1142 return (*dcr_env
->write_error
)(dcrn
);
1147 int ppc_dcr_register (CPUPPCState
*env
, int dcrn
, void *opaque
,
1148 dcr_read_cb dcr_read
, dcr_write_cb dcr_write
)
1153 dcr_env
= env
->dcr_env
;
1154 if (dcr_env
== NULL
)
1156 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1158 dcr
= &dcr_env
->dcrn
[dcrn
];
1159 if (dcr
->opaque
!= NULL
||
1160 dcr
->dcr_read
!= NULL
||
1161 dcr
->dcr_write
!= NULL
)
1163 dcr
->opaque
= opaque
;
1164 dcr
->dcr_read
= dcr_read
;
1165 dcr
->dcr_write
= dcr_write
;
1170 int ppc_dcr_init (CPUPPCState
*env
, int (*read_error
)(int dcrn
),
1171 int (*write_error
)(int dcrn
))
1175 dcr_env
= g_malloc0(sizeof(ppc_dcr_t
));
1176 dcr_env
->read_error
= read_error
;
1177 dcr_env
->write_error
= write_error
;
1178 env
->dcr_env
= dcr_env
;
1183 /*****************************************************************************/
1185 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
)
1197 printf("Set loglevel to %04" PRIx32
"\n", val
);
1198 qemu_set_log(val
| 0x100);
1203 /*****************************************************************************/
1205 static inline uint32_t nvram_read (nvram_t
*nvram
, uint32_t addr
)
1207 return (*nvram
->read_fn
)(nvram
->opaque
, addr
);
1210 static inline void nvram_write (nvram_t
*nvram
, uint32_t addr
, uint32_t val
)
1212 (*nvram
->write_fn
)(nvram
->opaque
, addr
, val
);
1215 static void NVRAM_set_byte(nvram_t
*nvram
, uint32_t addr
, uint8_t value
)
1217 nvram_write(nvram
, addr
, value
);
1220 static uint8_t NVRAM_get_byte(nvram_t
*nvram
, uint32_t addr
)
1222 return nvram_read(nvram
, addr
);
1225 static void NVRAM_set_word(nvram_t
*nvram
, uint32_t addr
, uint16_t value
)
1227 nvram_write(nvram
, addr
, value
>> 8);
1228 nvram_write(nvram
, addr
+ 1, value
& 0xFF);
1231 static uint16_t NVRAM_get_word(nvram_t
*nvram
, uint32_t addr
)
1235 tmp
= nvram_read(nvram
, addr
) << 8;
1236 tmp
|= nvram_read(nvram
, addr
+ 1);
1241 static void NVRAM_set_lword(nvram_t
*nvram
, uint32_t addr
, uint32_t value
)
1243 nvram_write(nvram
, addr
, value
>> 24);
1244 nvram_write(nvram
, addr
+ 1, (value
>> 16) & 0xFF);
1245 nvram_write(nvram
, addr
+ 2, (value
>> 8) & 0xFF);
1246 nvram_write(nvram
, addr
+ 3, value
& 0xFF);
1249 uint32_t NVRAM_get_lword (nvram_t
*nvram
, uint32_t addr
)
1253 tmp
= nvram_read(nvram
, addr
) << 24;
1254 tmp
|= nvram_read(nvram
, addr
+ 1) << 16;
1255 tmp
|= nvram_read(nvram
, addr
+ 2) << 8;
1256 tmp
|= nvram_read(nvram
, addr
+ 3);
1261 static void NVRAM_set_string(nvram_t
*nvram
, uint32_t addr
, const char *str
,
1266 for (i
= 0; i
< max
&& str
[i
] != '\0'; i
++) {
1267 nvram_write(nvram
, addr
+ i
, str
[i
]);
1269 nvram_write(nvram
, addr
+ i
, str
[i
]);
1270 nvram_write(nvram
, addr
+ max
- 1, '\0');
1273 int NVRAM_get_string (nvram_t
*nvram
, uint8_t *dst
, uint16_t addr
, int max
)
1277 memset(dst
, 0, max
);
1278 for (i
= 0; i
< max
; i
++) {
1279 dst
[i
] = NVRAM_get_byte(nvram
, addr
+ i
);
1287 static uint16_t NVRAM_crc_update (uint16_t prev
, uint16_t value
)
1290 uint16_t pd
, pd1
, pd2
;
1295 pd2
= ((pd
>> 4) & 0x000F) ^ pd1
;
1296 tmp
^= (pd1
<< 3) | (pd1
<< 8);
1297 tmp
^= pd2
| (pd2
<< 7) | (pd2
<< 12);
1302 static uint16_t NVRAM_compute_crc (nvram_t
*nvram
, uint32_t start
, uint32_t count
)
1305 uint16_t crc
= 0xFFFF;
1310 for (i
= 0; i
!= count
; i
++) {
1311 crc
= NVRAM_crc_update(crc
, NVRAM_get_word(nvram
, start
+ i
));
1314 crc
= NVRAM_crc_update(crc
, NVRAM_get_byte(nvram
, start
+ i
) << 8);
1320 #define CMDLINE_ADDR 0x017ff000
1322 int PPC_NVRAM_set_params (nvram_t
*nvram
, uint16_t NVRAM_size
,
1324 uint32_t RAM_size
, int boot_device
,
1325 uint32_t kernel_image
, uint32_t kernel_size
,
1326 const char *cmdline
,
1327 uint32_t initrd_image
, uint32_t initrd_size
,
1328 uint32_t NVRAM_image
,
1329 int width
, int height
, int depth
)
1333 /* Set parameters for Open Hack'Ware BIOS */
1334 NVRAM_set_string(nvram
, 0x00, "QEMU_BIOS", 16);
1335 NVRAM_set_lword(nvram
, 0x10, 0x00000002); /* structure v2 */
1336 NVRAM_set_word(nvram
, 0x14, NVRAM_size
);
1337 NVRAM_set_string(nvram
, 0x20, arch
, 16);
1338 NVRAM_set_lword(nvram
, 0x30, RAM_size
);
1339 NVRAM_set_byte(nvram
, 0x34, boot_device
);
1340 NVRAM_set_lword(nvram
, 0x38, kernel_image
);
1341 NVRAM_set_lword(nvram
, 0x3C, kernel_size
);
1343 /* XXX: put the cmdline in NVRAM too ? */
1344 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, RAM_size
- CMDLINE_ADDR
, cmdline
);
1345 NVRAM_set_lword(nvram
, 0x40, CMDLINE_ADDR
);
1346 NVRAM_set_lword(nvram
, 0x44, strlen(cmdline
));
1348 NVRAM_set_lword(nvram
, 0x40, 0);
1349 NVRAM_set_lword(nvram
, 0x44, 0);
1351 NVRAM_set_lword(nvram
, 0x48, initrd_image
);
1352 NVRAM_set_lword(nvram
, 0x4C, initrd_size
);
1353 NVRAM_set_lword(nvram
, 0x50, NVRAM_image
);
1355 NVRAM_set_word(nvram
, 0x54, width
);
1356 NVRAM_set_word(nvram
, 0x56, height
);
1357 NVRAM_set_word(nvram
, 0x58, depth
);
1358 crc
= NVRAM_compute_crc(nvram
, 0x00, 0xF8);
1359 NVRAM_set_word(nvram
, 0xFC, crc
);