hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32
  33 extern int loglevel;
  34 extern FILE *logfile;
  35
  36 #define BIOS_FILENAME "ppc405_rom.bin"
  37 #undef BIOS_SIZE
  38 #define BIOS_SIZE (2048 * 1024)
  39
  40 #define KERNEL_LOAD_ADDR 0x00000000
  41 #define INITRD_LOAD_ADDR 0x01800000
  42
  43 #define USE_FLASH_BIOS
  44
  45 #define DEBUG_BOARD_INIT
  46
  47 /*****************************************************************************/
  48 /* PPC405EP reference board (IBM) */
  49 /* Standalone board with:
  50  * - PowerPC 405EP CPU
  51  * - SDRAM (0x00000000)
  52  * - Flash (0xFFF80000)
  53  * - SRAM  (0xFFF00000)
  54  * - NVRAM (0xF0000000)
  55  * - FPGA  (0xF0300000)
  56  */
  57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  58 struct ref405ep_fpga_t {
  59     uint32_t base;
  60     uint8_t reg0;
  61     uint8_t reg1;
  62 };
  63
  64 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  65 {
  66     ref405ep_fpga_t *fpga;
  67     uint32_t ret;
  68
  69     fpga = opaque;
  70     addr -= fpga->base;
  71     switch (addr) {
  72     case 0x0:
  73         ret = fpga->reg0;
  74         break;
  75     case 0x1:
  76         ret = fpga->reg1;
  77         break;
  78     default:
  79         ret = 0;
  80         break;
  81     }
  82
  83     return ret;
  84 }
  85
  86 static void ref405ep_fpga_writeb (void *opaque,
  87                                   target_phys_addr_t addr, uint32_t value)
  88 {
  89     ref405ep_fpga_t *fpga;
  90
  91     fpga = opaque;
  92     addr -= fpga->base;
  93     switch (addr) {
  94     case 0x0:
  95         /* Read only */
  96         break;
  97     case 0x1:
  98         fpga->reg1 = value;
  99         break;
 100     default:
 101         break;
 102     }
 103 }
 104
 105 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 106 {
 107     uint32_t ret;
 108
 109     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 110     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 111
 112     return ret;
 113 }
 114
 115 static void ref405ep_fpga_writew (void *opaque,
 116                                   target_phys_addr_t addr, uint32_t value)
 117 {
 118     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 119     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 120 }
 121
 122 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 123 {
 124     uint32_t ret;
 125
 126     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 127     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 128     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 129     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 130
 131     return ret;
 132 }
 133
 134 static void ref405ep_fpga_writel (void *opaque,
 135                                   target_phys_addr_t addr, uint32_t value)
 136 {
 137     ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
 138     ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 139     ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 140     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 141 }
 142
 143 static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
 144     &ref405ep_fpga_readb,
 145     &ref405ep_fpga_readw,
 146     &ref405ep_fpga_readl,
 147 };
 148
 149 static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
 150     &ref405ep_fpga_writeb,
 151     &ref405ep_fpga_writew,
 152     &ref405ep_fpga_writel,
 153 };
 154
 155 static void ref405ep_fpga_reset (void *opaque)
 156 {
 157     ref405ep_fpga_t *fpga;
 158
 159     fpga = opaque;
 160     fpga->reg0 = 0x00;
 161     fpga->reg1 = 0x0F;
 162 }
 163
 164 static void ref405ep_fpga_init (uint32_t base)
 165 {
 166     ref405ep_fpga_t *fpga;
 167     int fpga_memory;
 168
 169     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 170     if (fpga != NULL) {
 171         fpga->base = base;
 172         fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
 173                                              ref405ep_fpga_write, fpga);
 174         cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 175         ref405ep_fpga_reset(fpga);
 176         qemu_register_reset(&ref405ep_fpga_reset, fpga);
 177     }
 178 }
 179
 180 static void ref405ep_init (int ram_size, int vga_ram_size,
 181                            const char *boot_device, DisplayState *ds,
 182                            const char *kernel_filename,
 183                            const char *kernel_cmdline,
 184                            const char *initrd_filename,
 185                            const char *cpu_model)
 186 {
 187     char buf[1024];
 188     ppc4xx_bd_info_t bd;
 189     CPUPPCState *env;
 190     qemu_irq *pic;
 191     ram_addr_t sram_offset, bios_offset, bdloc;
 192     target_phys_addr_t ram_bases[2], ram_sizes[2];
 193     target_ulong sram_size, bios_size;
 194     //int phy_addr = 0;
 195     //static int phy_addr = 1;
 196     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 197     int linux_boot;
 198     int fl_idx, fl_sectors, len;
 199     int ppc_boot_device = boot_device[0];
 200
 201     /* XXX: fix this */
 202     ram_bases[0] = 0x00000000;
 203     ram_sizes[0] = 0x08000000;
 204     ram_bases[1] = 0x00000000;
 205     ram_sizes[1] = 0x00000000;
 206     ram_size = 128 * 1024 * 1024;
 207 #ifdef DEBUG_BOARD_INIT
 208     printf("%s: register cpu\n", __func__);
 209 #endif
 210     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset,
 211                         kernel_filename == NULL ? 0 : 1);
 212     /* allocate SRAM */
 213 #ifdef DEBUG_BOARD_INIT
 214     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 215 #endif
 216     sram_size = 512 * 1024;
 217     cpu_register_physical_memory(0xFFF00000, sram_size,
 218                                  sram_offset | IO_MEM_RAM);
 219     /* allocate and load BIOS */
 220 #ifdef DEBUG_BOARD_INIT
 221     printf("%s: register BIOS\n", __func__);
 222 #endif
 223     bios_offset = sram_offset + sram_size;
 224     fl_idx = 0;
 225 #ifdef USE_FLASH_BIOS
 226     if (pflash_table[fl_idx] != NULL) {
 227         bios_size = bdrv_getlength(pflash_table[fl_idx]);
 228         fl_sectors = (bios_size + 65535) >> 16;
 229 #ifdef DEBUG_BOARD_INIT
 230         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 231                " addr " ADDRX " '%s' %d\n",
 232                fl_idx, bios_size, bios_offset, -bios_size,
 233                bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
 234 #endif
 235         pflash_register((uint32_t)(-bios_size), bios_offset,
 236                         pflash_table[fl_idx], 65536, fl_sectors, 2,
 237                         0x0001, 0x22DA, 0x0000, 0x0000);
 238         fl_idx++;
 239     } else
 240 #endif
 241     {
 242 #ifdef DEBUG_BOARD_INIT
 243         printf("Load BIOS from file\n");
 244 #endif
 245         if (bios_name == NULL)
 246             bios_name = BIOS_FILENAME;
 247         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 248         bios_size = load_image(buf, phys_ram_base + bios_offset);
 249         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 250             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 251             exit(1);
 252         }
 253         bios_size = (bios_size + 0xfff) & ~0xfff;
 254         cpu_register_physical_memory((uint32_t)(-bios_size),
 255                                      bios_size, bios_offset | IO_MEM_ROM);
 256     }
 257     bios_offset += bios_size;
 258     /* Register FPGA */
 259 #ifdef DEBUG_BOARD_INIT
 260     printf("%s: register FPGA\n", __func__);
 261 #endif
 262     ref405ep_fpga_init(0xF0300000);
 263     /* Register NVRAM */
 264 #ifdef DEBUG_BOARD_INIT
 265     printf("%s: register NVRAM\n", __func__);
 266 #endif
 267     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 268     /* Load kernel */
 269     linux_boot = (kernel_filename != NULL);
 270     if (linux_boot) {
 271 #ifdef DEBUG_BOARD_INIT
 272         printf("%s: load kernel\n", __func__);
 273 #endif
 274         memset(&bd, 0, sizeof(bd));
 275         bd.bi_memstart = 0x00000000;
 276         bd.bi_memsize = ram_size;
 277         bd.bi_flashstart = -bios_size;
 278         bd.bi_flashsize = -bios_size;
 279         bd.bi_flashoffset = 0;
 280         bd.bi_sramstart = 0xFFF00000;
 281         bd.bi_sramsize = sram_size;
 282         bd.bi_bootflags = 0;
 283         bd.bi_intfreq = 133333333;
 284         bd.bi_busfreq = 33333333;
 285         bd.bi_baudrate = 115200;
 286         bd.bi_s_version[0] = 'Q';
 287         bd.bi_s_version[1] = 'M';
 288         bd.bi_s_version[2] = 'U';
 289         bd.bi_s_version[3] = '\0';
 290         bd.bi_r_version[0] = 'Q';
 291         bd.bi_r_version[1] = 'E';
 292         bd.bi_r_version[2] = 'M';
 293         bd.bi_r_version[3] = 'U';
 294         bd.bi_r_version[4] = '\0';
 295         bd.bi_procfreq = 133333333;
 296         bd.bi_plb_busfreq = 33333333;
 297         bd.bi_pci_busfreq = 33333333;
 298         bd.bi_opbfreq = 33333333;
 299         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 300         env->gpr[3] = bdloc;
 301         kernel_base = KERNEL_LOAD_ADDR;
 302         /* now we can load the kernel */
 303         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 304         if (kernel_size < 0) {
 305             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 306                     kernel_filename);
 307             exit(1);
 308         }
 309         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx
 310                " %02x %02x %02x %02x\n", kernel_size, kernel_base,
 311                *(char *)(phys_ram_base + kernel_base),
 312                *(char *)(phys_ram_base + kernel_base + 1),
 313                *(char *)(phys_ram_base + kernel_base + 2),
 314                *(char *)(phys_ram_base + kernel_base + 3));
 315         /* load initrd */
 316         if (initrd_filename) {
 317             initrd_base = INITRD_LOAD_ADDR;
 318             initrd_size = load_image(initrd_filename,
 319                                      phys_ram_base + initrd_base);
 320             if (initrd_size < 0) {
 321                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 322                         initrd_filename);
 323                 exit(1);
 324             }
 325         } else {
 326             initrd_base = 0;
 327             initrd_size = 0;
 328         }
 329         env->gpr[4] = initrd_base;
 330         env->gpr[5] = initrd_size;
 331         ppc_boot_device = 'm';
 332         if (kernel_cmdline != NULL) {
 333             len = strlen(kernel_cmdline);
 334             bdloc -= ((len + 255) & ~255);
 335             memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);
 336             env->gpr[6] = bdloc;
 337             env->gpr[7] = bdloc + len;
 338         } else {
 339             env->gpr[6] = 0;
 340             env->gpr[7] = 0;
 341         }
 342         env->nip = KERNEL_LOAD_ADDR;
 343     } else {
 344         kernel_base = 0;
 345         kernel_size = 0;
 346         initrd_base = 0;
 347         initrd_size = 0;
 348         bdloc = 0;
 349     }
 350 #ifdef DEBUG_BOARD_INIT
 351     printf("%s: Done\n", __func__);
 352 #endif
 353     printf("bdloc %016lx %s\n",
 354            (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));
 355 }
 356
 357 QEMUMachine ref405ep_machine = {
 358     "ref405ep",
 359     "ref405ep",
 360     ref405ep_init,
 361 };
 362
 363 /*****************************************************************************/
 364 /* AMCC Taihu evaluation board */
 365 /* - PowerPC 405EP processor
 366  * - SDRAM               128 MB at 0x00000000
 367  * - Boot flash          2 MB   at 0xFFE00000
 368  * - Application flash   32 MB  at 0xFC000000
 369  * - 2 serial ports
 370  * - 2 ethernet PHY
 371  * - 1 USB 1.1 device    0x50000000
 372  * - 1 LCD display       0x50100000
 373  * - 1 CPLD              0x50100000
 374  * - 1 I2C EEPROM
 375  * - 1 I2C thermal sensor
 376  * - a set of LEDs
 377  * - bit-bang SPI port using GPIOs
 378  * - 1 EBC interface connector 0 0x50200000
 379  * - 1 cardbus controller + expansion slot.
 380  * - 1 PCI expansion slot.
 381  */
 382 typedef struct taihu_cpld_t taihu_cpld_t;
 383 struct taihu_cpld_t {
 384     uint32_t base;
 385     uint8_t reg0;
 386     uint8_t reg1;
 387 };
 388
 389 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 390 {
 391     taihu_cpld_t *cpld;
 392     uint32_t ret;
 393
 394     cpld = opaque;
 395     addr -= cpld->base;
 396     switch (addr) {
 397     case 0x0:
 398         ret = cpld->reg0;
 399         break;
 400     case 0x1:
 401         ret = cpld->reg1;
 402         break;
 403     default:
 404         ret = 0;
 405         break;
 406     }
 407
 408     return ret;
 409 }
 410
 411 static void taihu_cpld_writeb (void *opaque,
 412                                target_phys_addr_t addr, uint32_t value)
 413 {
 414     taihu_cpld_t *cpld;
 415
 416     cpld = opaque;
 417     addr -= cpld->base;
 418     switch (addr) {
 419     case 0x0:
 420         /* Read only */
 421         break;
 422     case 0x1:
 423         cpld->reg1 = value;
 424         break;
 425     default:
 426         break;
 427     }
 428 }
 429
 430 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 431 {
 432     uint32_t ret;
 433
 434     ret = taihu_cpld_readb(opaque, addr) << 8;
 435     ret |= taihu_cpld_readb(opaque, addr + 1);
 436
 437     return ret;
 438 }
 439
 440 static void taihu_cpld_writew (void *opaque,
 441                                target_phys_addr_t addr, uint32_t value)
 442 {
 443     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 444     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 445 }
 446
 447 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 448 {
 449     uint32_t ret;
 450
 451     ret = taihu_cpld_readb(opaque, addr) << 24;
 452     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 453     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 454     ret |= taihu_cpld_readb(opaque, addr + 3);
 455
 456     return ret;
 457 }
 458
 459 static void taihu_cpld_writel (void *opaque,
 460                                target_phys_addr_t addr, uint32_t value)
 461 {
 462     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 463     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 464     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 465     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 466 }
 467
 468 static CPUReadMemoryFunc *taihu_cpld_read[] = {
 469     &taihu_cpld_readb,
 470     &taihu_cpld_readw,
 471     &taihu_cpld_readl,
 472 };
 473
 474 static CPUWriteMemoryFunc *taihu_cpld_write[] = {
 475     &taihu_cpld_writeb,
 476     &taihu_cpld_writew,
 477     &taihu_cpld_writel,
 478 };
 479
 480 static void taihu_cpld_reset (void *opaque)
 481 {
 482     taihu_cpld_t *cpld;
 483
 484     cpld = opaque;
 485     cpld->reg0 = 0x01;
 486     cpld->reg1 = 0x80;
 487 }
 488
 489 static void taihu_cpld_init (uint32_t base)
 490 {
 491     taihu_cpld_t *cpld;
 492     int cpld_memory;
 493
 494     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 495     if (cpld != NULL) {
 496         cpld->base = base;
 497         cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
 498                                              taihu_cpld_write, cpld);
 499         cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 500         taihu_cpld_reset(cpld);
 501         qemu_register_reset(&taihu_cpld_reset, cpld);
 502     }
 503 }
 504
 505 static void taihu_405ep_init(int ram_size, int vga_ram_size,
 506                              const char *boot_device, DisplayState *ds,
 507                              const char *kernel_filename,
 508                              const char *kernel_cmdline,
 509                              const char *initrd_filename,
 510                              const char *cpu_model)
 511 {
 512     char buf[1024];
 513     CPUPPCState *env;
 514     qemu_irq *pic;
 515     ram_addr_t bios_offset;
 516     target_phys_addr_t ram_bases[2], ram_sizes[2];
 517     target_ulong bios_size;
 518     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 519     int linux_boot;
 520     int fl_idx, fl_sectors;
 521     int ppc_boot_device = boot_device[0];
 522
 523     /* RAM is soldered to the board so the size cannot be changed */
 524     ram_bases[0] = 0x00000000;
 525     ram_sizes[0] = 0x04000000;
 526     ram_bases[1] = 0x04000000;
 527     ram_sizes[1] = 0x04000000;
 528 #ifdef DEBUG_BOARD_INIT
 529     printf("%s: register cpu\n", __func__);
 530 #endif
 531     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,
 532                         kernel_filename == NULL ? 0 : 1);
 533     /* allocate and load BIOS */
 534 #ifdef DEBUG_BOARD_INIT
 535     printf("%s: register BIOS\n", __func__);
 536 #endif
 537     fl_idx = 0;
 538 #if defined(USE_FLASH_BIOS)
 539     if (pflash_table[fl_idx] != NULL) {
 540         bios_size = bdrv_getlength(pflash_table[fl_idx]);
 541         /* XXX: should check that size is 2MB */
 542         //        bios_size = 2 * 1024 * 1024;
 543         fl_sectors = (bios_size + 65535) >> 16;
 544 #ifdef DEBUG_BOARD_INIT
 545         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 546                " addr " ADDRX " '%s' %d\n",
 547                fl_idx, bios_size, bios_offset, -bios_size,
 548                bdrv_get_device_name(pflash_table[fl_idx]), fl_sectors);
 549 #endif
 550         pflash_register((uint32_t)(-bios_size), bios_offset,
 551                         pflash_table[fl_idx], 65536, fl_sectors, 4,
 552                         0x0001, 0x22DA, 0x0000, 0x0000);
 553         fl_idx++;
 554     } else
 555 #endif
 556     {
 557 #ifdef DEBUG_BOARD_INIT
 558         printf("Load BIOS from file\n");
 559 #endif
 560         if (bios_name == NULL)
 561             bios_name = BIOS_FILENAME;
 562         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 563         bios_size = load_image(buf, phys_ram_base + bios_offset);
 564         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 565             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
 566             exit(1);
 567         }
 568         bios_size = (bios_size + 0xfff) & ~0xfff;
 569         cpu_register_physical_memory((uint32_t)(-bios_size),
 570                                      bios_size, bios_offset | IO_MEM_ROM);
 571     }
 572     bios_offset += bios_size;
 573     /* Register Linux flash */
 574     if (pflash_table[fl_idx] != NULL) {
 575         bios_size = bdrv_getlength(pflash_table[fl_idx]);
 576         /* XXX: should check that size is 32MB */
 577         bios_size = 32 * 1024 * 1024;
 578         fl_sectors = (bios_size + 65535) >> 16;
 579 #ifdef DEBUG_BOARD_INIT
 580         printf("Register parallel flash %d size " ADDRX " at offset %08lx "
 581                " addr " ADDRX " '%s'\n",
 582                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 583                bdrv_get_device_name(pflash_table[fl_idx]));
 584 #endif
 585         pflash_register(0xfc000000, bios_offset, pflash_table[fl_idx],
 586                         65536, fl_sectors, 4,
 587                         0x0001, 0x22DA, 0x0000, 0x0000);
 588         fl_idx++;
 589     }
 590     /* Register CLPD & LCD display */
 591 #ifdef DEBUG_BOARD_INIT
 592     printf("%s: register CPLD\n", __func__);
 593 #endif
 594     taihu_cpld_init(0x50100000);
 595     /* Load kernel */
 596     linux_boot = (kernel_filename != NULL);
 597     if (linux_boot) {
 598 #ifdef DEBUG_BOARD_INIT
 599         printf("%s: load kernel\n", __func__);
 600 #endif
 601         kernel_base = KERNEL_LOAD_ADDR;
 602         /* now we can load the kernel */
 603         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 604         if (kernel_size < 0) {
 605             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 606                     kernel_filename);
 607             exit(1);
 608         }
 609         /* load initrd */
 610         if (initrd_filename) {
 611             initrd_base = INITRD_LOAD_ADDR;
 612             initrd_size = load_image(initrd_filename,
 613                                      phys_ram_base + initrd_base);
 614             if (initrd_size < 0) {
 615                 fprintf(stderr,
 616                         "qemu: could not load initial ram disk '%s'\n",
 617                         initrd_filename);
 618                 exit(1);
 619             }
 620         } else {
 621             initrd_base = 0;
 622             initrd_size = 0;
 623         }
 624         ppc_boot_device = 'm';
 625     } else {
 626         kernel_base = 0;
 627         kernel_size = 0;
 628         initrd_base = 0;
 629         initrd_size = 0;
 630     }
 631 #ifdef DEBUG_BOARD_INIT
 632     printf("%s: Done\n", __func__);
 633 #endif
 634 }
 635
 636 QEMUMachine taihu_machine = {
 637     "taihu",
 638     "taihu",
 639     taihu_405ep_init,
 640 };