2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
39 //#define DEBUG_UNASSIGNED
41 ram_addr_t
ppc405_set_bootinfo (CPUState
*env
, ppc4xx_bd_info_t
*bd
,
47 /* We put the bd structure at the top of memory */
48 if (bd
->bi_memsize
>= 0x01000000UL
)
49 bdloc
= 0x01000000UL
- sizeof(struct ppc4xx_bd_info_t
);
51 bdloc
= bd
->bi_memsize
- sizeof(struct ppc4xx_bd_info_t
);
52 stl_raw(phys_ram_base
+ bdloc
+ 0x00, bd
->bi_memstart
);
53 stl_raw(phys_ram_base
+ bdloc
+ 0x04, bd
->bi_memsize
);
54 stl_raw(phys_ram_base
+ bdloc
+ 0x08, bd
->bi_flashstart
);
55 stl_raw(phys_ram_base
+ bdloc
+ 0x0C, bd
->bi_flashsize
);
56 stl_raw(phys_ram_base
+ bdloc
+ 0x10, bd
->bi_flashoffset
);
57 stl_raw(phys_ram_base
+ bdloc
+ 0x14, bd
->bi_sramstart
);
58 stl_raw(phys_ram_base
+ bdloc
+ 0x18, bd
->bi_sramsize
);
59 stl_raw(phys_ram_base
+ bdloc
+ 0x1C, bd
->bi_bootflags
);
60 stl_raw(phys_ram_base
+ bdloc
+ 0x20, bd
->bi_ipaddr
);
61 for (i
= 0; i
< 6; i
++)
62 stb_raw(phys_ram_base
+ bdloc
+ 0x24 + i
, bd
->bi_enetaddr
[i
]);
63 stw_raw(phys_ram_base
+ bdloc
+ 0x2A, bd
->bi_ethspeed
);
64 stl_raw(phys_ram_base
+ bdloc
+ 0x2C, bd
->bi_intfreq
);
65 stl_raw(phys_ram_base
+ bdloc
+ 0x30, bd
->bi_busfreq
);
66 stl_raw(phys_ram_base
+ bdloc
+ 0x34, bd
->bi_baudrate
);
67 for (i
= 0; i
< 4; i
++)
68 stb_raw(phys_ram_base
+ bdloc
+ 0x38 + i
, bd
->bi_s_version
[i
]);
69 for (i
= 0; i
< 32; i
++)
70 stb_raw(phys_ram_base
+ bdloc
+ 0x3C + i
, bd
->bi_s_version
[i
]);
71 stl_raw(phys_ram_base
+ bdloc
+ 0x5C, bd
->bi_plb_busfreq
);
72 stl_raw(phys_ram_base
+ bdloc
+ 0x60, bd
->bi_pci_busfreq
);
73 for (i
= 0; i
< 6; i
++)
74 stb_raw(phys_ram_base
+ bdloc
+ 0x64 + i
, bd
->bi_pci_enetaddr
[i
]);
76 if (flags
& 0x00000001) {
77 for (i
= 0; i
< 6; i
++)
78 stb_raw(phys_ram_base
+ bdloc
+ n
++, bd
->bi_pci_enetaddr2
[i
]);
80 stl_raw(phys_ram_base
+ bdloc
+ n
, bd
->bi_opbfreq
);
82 for (i
= 0; i
< 2; i
++) {
83 stl_raw(phys_ram_base
+ bdloc
+ n
, bd
->bi_iic_fast
[i
]);
90 /*****************************************************************************/
91 /* Shared peripherals */
93 /*****************************************************************************/
94 /* Peripheral local bus arbitrer */
101 typedef struct ppc4xx_plb_t ppc4xx_plb_t
;
102 struct ppc4xx_plb_t
{
108 static target_ulong
dcr_read_plb (void *opaque
, int dcrn
)
125 /* Avoid gcc warning */
133 static void dcr_write_plb (void *opaque
, int dcrn
, target_ulong val
)
140 /* We don't care about the actual parameters written as
141 * we don't manage any priorities on the bus
143 plb
->acr
= val
& 0xF8000000;
155 static void ppc4xx_plb_reset (void *opaque
)
160 plb
->acr
= 0x00000000;
161 plb
->bear
= 0x00000000;
162 plb
->besr
= 0x00000000;
165 void ppc4xx_plb_init (CPUState
*env
)
169 plb
= qemu_mallocz(sizeof(ppc4xx_plb_t
));
171 ppc_dcr_register(env
, PLB0_ACR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
172 ppc_dcr_register(env
, PLB0_BEAR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
173 ppc_dcr_register(env
, PLB0_BESR
, plb
, &dcr_read_plb
, &dcr_write_plb
);
174 ppc4xx_plb_reset(plb
);
175 qemu_register_reset(ppc4xx_plb_reset
, plb
);
179 /*****************************************************************************/
180 /* PLB to OPB bridge */
187 typedef struct ppc4xx_pob_t ppc4xx_pob_t
;
188 struct ppc4xx_pob_t
{
193 static target_ulong
dcr_read_pob (void *opaque
, int dcrn
)
205 ret
= pob
->besr
[dcrn
- POB0_BESR0
];
208 /* Avoid gcc warning */
216 static void dcr_write_pob (void *opaque
, int dcrn
, target_ulong val
)
228 pob
->besr
[dcrn
- POB0_BESR0
] &= ~val
;
233 static void ppc4xx_pob_reset (void *opaque
)
239 pob
->bear
= 0x00000000;
240 pob
->besr
[0] = 0x0000000;
241 pob
->besr
[1] = 0x0000000;
244 void ppc4xx_pob_init (CPUState
*env
)
248 pob
= qemu_mallocz(sizeof(ppc4xx_pob_t
));
250 ppc_dcr_register(env
, POB0_BEAR
, pob
, &dcr_read_pob
, &dcr_write_pob
);
251 ppc_dcr_register(env
, POB0_BESR0
, pob
, &dcr_read_pob
, &dcr_write_pob
);
252 ppc_dcr_register(env
, POB0_BESR1
, pob
, &dcr_read_pob
, &dcr_write_pob
);
253 qemu_register_reset(ppc4xx_pob_reset
, pob
);
254 ppc4xx_pob_reset(env
);
258 /*****************************************************************************/
260 typedef struct ppc4xx_opba_t ppc4xx_opba_t
;
261 struct ppc4xx_opba_t
{
262 target_phys_addr_t base
;
267 static uint32_t opba_readb (void *opaque
, target_phys_addr_t addr
)
273 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
276 switch (addr
- opba
->base
) {
291 static void opba_writeb (void *opaque
,
292 target_phys_addr_t addr
, uint32_t value
)
297 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
300 switch (addr
- opba
->base
) {
302 opba
->cr
= value
& 0xF8;
305 opba
->pr
= value
& 0xFF;
312 static uint32_t opba_readw (void *opaque
, target_phys_addr_t addr
)
317 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
319 ret
= opba_readb(opaque
, addr
) << 8;
320 ret
|= opba_readb(opaque
, addr
+ 1);
325 static void opba_writew (void *opaque
,
326 target_phys_addr_t addr
, uint32_t value
)
329 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
331 opba_writeb(opaque
, addr
, value
>> 8);
332 opba_writeb(opaque
, addr
+ 1, value
);
335 static uint32_t opba_readl (void *opaque
, target_phys_addr_t addr
)
340 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
342 ret
= opba_readb(opaque
, addr
) << 24;
343 ret
|= opba_readb(opaque
, addr
+ 1) << 16;
348 static void opba_writel (void *opaque
,
349 target_phys_addr_t addr
, uint32_t value
)
352 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
354 opba_writeb(opaque
, addr
, value
>> 24);
355 opba_writeb(opaque
, addr
+ 1, value
>> 16);
358 static CPUReadMemoryFunc
*opba_read
[] = {
364 static CPUWriteMemoryFunc
*opba_write
[] = {
370 static void ppc4xx_opba_reset (void *opaque
)
375 opba
->cr
= 0x00; /* No dynamic priorities - park disabled */
379 void ppc4xx_opba_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
380 target_phys_addr_t offset
)
384 opba
= qemu_mallocz(sizeof(ppc4xx_opba_t
));
388 printf("%s: offset=" PADDRX
"\n", __func__
, offset
);
390 ppc4xx_mmio_register(env
, mmio
, offset
, 0x002,
391 opba_read
, opba_write
, opba
);
392 qemu_register_reset(ppc4xx_opba_reset
, opba
);
393 ppc4xx_opba_reset(opba
);
397 /*****************************************************************************/
398 /* Code decompression controller */
401 /*****************************************************************************/
402 /* SDRAM controller */
403 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t
;
404 struct ppc4xx_sdram_t
{
407 target_phys_addr_t ram_bases
[4];
408 target_phys_addr_t ram_sizes
[4];
424 SDRAM0_CFGADDR
= 0x010,
425 SDRAM0_CFGDATA
= 0x011,
428 static uint32_t sdram_bcr (target_phys_addr_t ram_base
,
429 target_phys_addr_t ram_size
)
434 case (4 * 1024 * 1024):
437 case (8 * 1024 * 1024):
440 case (16 * 1024 * 1024):
443 case (32 * 1024 * 1024):
446 case (64 * 1024 * 1024):
449 case (128 * 1024 * 1024):
452 case (256 * 1024 * 1024):
456 printf("%s: invalid RAM size " TARGET_FMT_plx
"\n",
460 bcr
|= ram_base
& 0xFF800000;
466 static always_inline target_phys_addr_t
sdram_base (uint32_t bcr
)
468 return bcr
& 0xFF800000;
471 static target_ulong
sdram_size (uint32_t bcr
)
476 sh
= (bcr
>> 17) & 0x7;
480 size
= (4 * 1024 * 1024) << sh
;
485 static void sdram_set_bcr (uint32_t *bcrp
, uint32_t bcr
, int enabled
)
487 if (*bcrp
& 0x00000001) {
490 printf("%s: unmap RAM area " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
491 __func__
, sdram_base(*bcrp
), sdram_size(*bcrp
));
493 cpu_register_physical_memory(sdram_base(*bcrp
), sdram_size(*bcrp
),
496 *bcrp
= bcr
& 0xFFDEE001;
497 if (enabled
&& (bcr
& 0x00000001)) {
499 printf("%s: Map RAM area " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
500 __func__
, sdram_base(bcr
), sdram_size(bcr
));
502 cpu_register_physical_memory(sdram_base(bcr
), sdram_size(bcr
),
503 sdram_base(bcr
) | IO_MEM_RAM
);
507 static void sdram_map_bcr (ppc4xx_sdram_t
*sdram
)
511 for (i
= 0; i
< sdram
->nbanks
; i
++) {
512 if (sdram
->ram_sizes
[i
] != 0) {
513 sdram_set_bcr(&sdram
->bcr
[i
],
514 sdram_bcr(sdram
->ram_bases
[i
], sdram
->ram_sizes
[i
]),
517 sdram_set_bcr(&sdram
->bcr
[i
], 0x00000000, 0);
522 static void sdram_unmap_bcr (ppc4xx_sdram_t
*sdram
)
526 for (i
= 0; i
< sdram
->nbanks
; i
++) {
528 printf("%s: Unmap RAM area " TARGET_FMT_plx
" " TARGET_FMT_lx
"\n",
529 __func__
, sdram_base(sdram
->bcr
[i
]), sdram_size(sdram
->bcr
[i
]));
531 cpu_register_physical_memory(sdram_base(sdram
->bcr
[i
]),
532 sdram_size(sdram
->bcr
[i
]),
537 static target_ulong
dcr_read_sdram (void *opaque
, int dcrn
)
539 ppc4xx_sdram_t
*sdram
;
548 switch (sdram
->addr
) {
549 case 0x00: /* SDRAM_BESR0 */
552 case 0x08: /* SDRAM_BESR1 */
555 case 0x10: /* SDRAM_BEAR */
558 case 0x20: /* SDRAM_CFG */
561 case 0x24: /* SDRAM_STATUS */
564 case 0x30: /* SDRAM_RTR */
567 case 0x34: /* SDRAM_PMIT */
570 case 0x40: /* SDRAM_B0CR */
573 case 0x44: /* SDRAM_B1CR */
576 case 0x48: /* SDRAM_B2CR */
579 case 0x4C: /* SDRAM_B3CR */
582 case 0x80: /* SDRAM_TR */
585 case 0x94: /* SDRAM_ECCCFG */
588 case 0x98: /* SDRAM_ECCESR */
597 /* Avoid gcc warning */
605 static void dcr_write_sdram (void *opaque
, int dcrn
, target_ulong val
)
607 ppc4xx_sdram_t
*sdram
;
615 switch (sdram
->addr
) {
616 case 0x00: /* SDRAM_BESR0 */
617 sdram
->besr0
&= ~val
;
619 case 0x08: /* SDRAM_BESR1 */
620 sdram
->besr1
&= ~val
;
622 case 0x10: /* SDRAM_BEAR */
625 case 0x20: /* SDRAM_CFG */
627 if (!(sdram
->cfg
& 0x80000000) && (val
& 0x80000000)) {
629 printf("%s: enable SDRAM controller\n", __func__
);
631 /* validate all RAM mappings */
632 sdram_map_bcr(sdram
);
633 sdram
->status
&= ~0x80000000;
634 } else if ((sdram
->cfg
& 0x80000000) && !(val
& 0x80000000)) {
636 printf("%s: disable SDRAM controller\n", __func__
);
638 /* invalidate all RAM mappings */
639 sdram_unmap_bcr(sdram
);
640 sdram
->status
|= 0x80000000;
642 if (!(sdram
->cfg
& 0x40000000) && (val
& 0x40000000))
643 sdram
->status
|= 0x40000000;
644 else if ((sdram
->cfg
& 0x40000000) && !(val
& 0x40000000))
645 sdram
->status
&= ~0x40000000;
648 case 0x24: /* SDRAM_STATUS */
649 /* Read-only register */
651 case 0x30: /* SDRAM_RTR */
652 sdram
->rtr
= val
& 0x3FF80000;
654 case 0x34: /* SDRAM_PMIT */
655 sdram
->pmit
= (val
& 0xF8000000) | 0x07C00000;
657 case 0x40: /* SDRAM_B0CR */
658 sdram_set_bcr(&sdram
->bcr
[0], val
, sdram
->cfg
& 0x80000000);
660 case 0x44: /* SDRAM_B1CR */
661 sdram_set_bcr(&sdram
->bcr
[1], val
, sdram
->cfg
& 0x80000000);
663 case 0x48: /* SDRAM_B2CR */
664 sdram_set_bcr(&sdram
->bcr
[2], val
, sdram
->cfg
& 0x80000000);
666 case 0x4C: /* SDRAM_B3CR */
667 sdram_set_bcr(&sdram
->bcr
[3], val
, sdram
->cfg
& 0x80000000);
669 case 0x80: /* SDRAM_TR */
670 sdram
->tr
= val
& 0x018FC01F;
672 case 0x94: /* SDRAM_ECCCFG */
673 sdram
->ecccfg
= val
& 0x00F00000;
675 case 0x98: /* SDRAM_ECCESR */
677 if (sdram
->eccesr
== 0 && val
!= 0)
678 qemu_irq_raise(sdram
->irq
);
679 else if (sdram
->eccesr
!= 0 && val
== 0)
680 qemu_irq_lower(sdram
->irq
);
690 static void sdram_reset (void *opaque
)
692 ppc4xx_sdram_t
*sdram
;
695 sdram
->addr
= 0x00000000;
696 sdram
->bear
= 0x00000000;
697 sdram
->besr0
= 0x00000000; /* No error */
698 sdram
->besr1
= 0x00000000; /* No error */
699 sdram
->cfg
= 0x00000000;
700 sdram
->ecccfg
= 0x00000000; /* No ECC */
701 sdram
->eccesr
= 0x00000000; /* No error */
702 sdram
->pmit
= 0x07C00000;
703 sdram
->rtr
= 0x05F00000;
704 sdram
->tr
= 0x00854009;
705 /* We pre-initialize RAM banks */
706 sdram
->status
= 0x00000000;
707 sdram
->cfg
= 0x00800000;
708 sdram_unmap_bcr(sdram
);
711 void ppc405_sdram_init (CPUState
*env
, qemu_irq irq
, int nbanks
,
712 target_phys_addr_t
*ram_bases
,
713 target_phys_addr_t
*ram_sizes
,
716 ppc4xx_sdram_t
*sdram
;
718 sdram
= qemu_mallocz(sizeof(ppc4xx_sdram_t
));
721 sdram
->nbanks
= nbanks
;
722 memset(sdram
->ram_bases
, 0, 4 * sizeof(target_phys_addr_t
));
723 memcpy(sdram
->ram_bases
, ram_bases
,
724 nbanks
* sizeof(target_phys_addr_t
));
725 memset(sdram
->ram_sizes
, 0, 4 * sizeof(target_phys_addr_t
));
726 memcpy(sdram
->ram_sizes
, ram_sizes
,
727 nbanks
* sizeof(target_phys_addr_t
));
729 qemu_register_reset(&sdram_reset
, sdram
);
730 ppc_dcr_register(env
, SDRAM0_CFGADDR
,
731 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
732 ppc_dcr_register(env
, SDRAM0_CFGDATA
,
733 sdram
, &dcr_read_sdram
, &dcr_write_sdram
);
735 sdram_map_bcr(sdram
);
739 /*****************************************************************************/
740 /* Peripheral controller */
741 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t
;
742 struct ppc4xx_ebc_t
{
753 EBC0_CFGADDR
= 0x012,
754 EBC0_CFGDATA
= 0x013,
757 static target_ulong
dcr_read_ebc (void *opaque
, int dcrn
)
769 case 0x00: /* B0CR */
772 case 0x01: /* B1CR */
775 case 0x02: /* B2CR */
778 case 0x03: /* B3CR */
781 case 0x04: /* B4CR */
784 case 0x05: /* B5CR */
787 case 0x06: /* B6CR */
790 case 0x07: /* B7CR */
793 case 0x10: /* B0AP */
796 case 0x11: /* B1AP */
799 case 0x12: /* B2AP */
802 case 0x13: /* B3AP */
805 case 0x14: /* B4AP */
808 case 0x15: /* B5AP */
811 case 0x16: /* B6AP */
814 case 0x17: /* B7AP */
817 case 0x20: /* BEAR */
820 case 0x21: /* BESR0 */
823 case 0x22: /* BESR1 */
841 static void dcr_write_ebc (void *opaque
, int dcrn
, target_ulong val
)
852 case 0x00: /* B0CR */
854 case 0x01: /* B1CR */
856 case 0x02: /* B2CR */
858 case 0x03: /* B3CR */
860 case 0x04: /* B4CR */
862 case 0x05: /* B5CR */
864 case 0x06: /* B6CR */
866 case 0x07: /* B7CR */
868 case 0x10: /* B0AP */
870 case 0x11: /* B1AP */
872 case 0x12: /* B2AP */
874 case 0x13: /* B3AP */
876 case 0x14: /* B4AP */
878 case 0x15: /* B5AP */
880 case 0x16: /* B6AP */
882 case 0x17: /* B7AP */
884 case 0x20: /* BEAR */
886 case 0x21: /* BESR0 */
888 case 0x22: /* BESR1 */
901 static void ebc_reset (void *opaque
)
907 ebc
->addr
= 0x00000000;
908 ebc
->bap
[0] = 0x7F8FFE80;
909 ebc
->bcr
[0] = 0xFFE28000;
910 for (i
= 0; i
< 8; i
++) {
911 ebc
->bap
[i
] = 0x00000000;
912 ebc
->bcr
[i
] = 0x00000000;
914 ebc
->besr0
= 0x00000000;
915 ebc
->besr1
= 0x00000000;
916 ebc
->cfg
= 0x80400000;
919 void ppc405_ebc_init (CPUState
*env
)
923 ebc
= qemu_mallocz(sizeof(ppc4xx_ebc_t
));
926 qemu_register_reset(&ebc_reset
, ebc
);
927 ppc_dcr_register(env
, EBC0_CFGADDR
,
928 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
929 ppc_dcr_register(env
, EBC0_CFGDATA
,
930 ebc
, &dcr_read_ebc
, &dcr_write_ebc
);
934 /*****************************************************************************/
963 typedef struct ppc405_dma_t ppc405_dma_t
;
964 struct ppc405_dma_t
{
977 static target_ulong
dcr_read_dma (void *opaque
, int dcrn
)
986 static void dcr_write_dma (void *opaque
, int dcrn
, target_ulong val
)
993 static void ppc405_dma_reset (void *opaque
)
999 for (i
= 0; i
< 4; i
++) {
1000 dma
->cr
[i
] = 0x00000000;
1001 dma
->ct
[i
] = 0x00000000;
1002 dma
->da
[i
] = 0x00000000;
1003 dma
->sa
[i
] = 0x00000000;
1004 dma
->sg
[i
] = 0x00000000;
1006 dma
->sr
= 0x00000000;
1007 dma
->sgc
= 0x00000000;
1008 dma
->slp
= 0x7C000000;
1009 dma
->pol
= 0x00000000;
1012 void ppc405_dma_init (CPUState
*env
, qemu_irq irqs
[4])
1016 dma
= qemu_mallocz(sizeof(ppc405_dma_t
));
1018 memcpy(dma
->irqs
, irqs
, 4 * sizeof(qemu_irq
));
1019 ppc405_dma_reset(dma
);
1020 qemu_register_reset(&ppc405_dma_reset
, dma
);
1021 ppc_dcr_register(env
, DMA0_CR0
,
1022 dma
, &dcr_read_dma
, &dcr_write_dma
);
1023 ppc_dcr_register(env
, DMA0_CT0
,
1024 dma
, &dcr_read_dma
, &dcr_write_dma
);
1025 ppc_dcr_register(env
, DMA0_DA0
,
1026 dma
, &dcr_read_dma
, &dcr_write_dma
);
1027 ppc_dcr_register(env
, DMA0_SA0
,
1028 dma
, &dcr_read_dma
, &dcr_write_dma
);
1029 ppc_dcr_register(env
, DMA0_SG0
,
1030 dma
, &dcr_read_dma
, &dcr_write_dma
);
1031 ppc_dcr_register(env
, DMA0_CR1
,
1032 dma
, &dcr_read_dma
, &dcr_write_dma
);
1033 ppc_dcr_register(env
, DMA0_CT1
,
1034 dma
, &dcr_read_dma
, &dcr_write_dma
);
1035 ppc_dcr_register(env
, DMA0_DA1
,
1036 dma
, &dcr_read_dma
, &dcr_write_dma
);
1037 ppc_dcr_register(env
, DMA0_SA1
,
1038 dma
, &dcr_read_dma
, &dcr_write_dma
);
1039 ppc_dcr_register(env
, DMA0_SG1
,
1040 dma
, &dcr_read_dma
, &dcr_write_dma
);
1041 ppc_dcr_register(env
, DMA0_CR2
,
1042 dma
, &dcr_read_dma
, &dcr_write_dma
);
1043 ppc_dcr_register(env
, DMA0_CT2
,
1044 dma
, &dcr_read_dma
, &dcr_write_dma
);
1045 ppc_dcr_register(env
, DMA0_DA2
,
1046 dma
, &dcr_read_dma
, &dcr_write_dma
);
1047 ppc_dcr_register(env
, DMA0_SA2
,
1048 dma
, &dcr_read_dma
, &dcr_write_dma
);
1049 ppc_dcr_register(env
, DMA0_SG2
,
1050 dma
, &dcr_read_dma
, &dcr_write_dma
);
1051 ppc_dcr_register(env
, DMA0_CR3
,
1052 dma
, &dcr_read_dma
, &dcr_write_dma
);
1053 ppc_dcr_register(env
, DMA0_CT3
,
1054 dma
, &dcr_read_dma
, &dcr_write_dma
);
1055 ppc_dcr_register(env
, DMA0_DA3
,
1056 dma
, &dcr_read_dma
, &dcr_write_dma
);
1057 ppc_dcr_register(env
, DMA0_SA3
,
1058 dma
, &dcr_read_dma
, &dcr_write_dma
);
1059 ppc_dcr_register(env
, DMA0_SG3
,
1060 dma
, &dcr_read_dma
, &dcr_write_dma
);
1061 ppc_dcr_register(env
, DMA0_SR
,
1062 dma
, &dcr_read_dma
, &dcr_write_dma
);
1063 ppc_dcr_register(env
, DMA0_SGC
,
1064 dma
, &dcr_read_dma
, &dcr_write_dma
);
1065 ppc_dcr_register(env
, DMA0_SLP
,
1066 dma
, &dcr_read_dma
, &dcr_write_dma
);
1067 ppc_dcr_register(env
, DMA0_POL
,
1068 dma
, &dcr_read_dma
, &dcr_write_dma
);
1072 /*****************************************************************************/
1074 typedef struct ppc405_gpio_t ppc405_gpio_t
;
1075 struct ppc405_gpio_t
{
1076 target_phys_addr_t base
;
1090 static uint32_t ppc405_gpio_readb (void *opaque
, target_phys_addr_t addr
)
1092 ppc405_gpio_t
*gpio
;
1096 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1102 static void ppc405_gpio_writeb (void *opaque
,
1103 target_phys_addr_t addr
, uint32_t value
)
1105 ppc405_gpio_t
*gpio
;
1109 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1113 static uint32_t ppc405_gpio_readw (void *opaque
, target_phys_addr_t addr
)
1115 ppc405_gpio_t
*gpio
;
1119 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1125 static void ppc405_gpio_writew (void *opaque
,
1126 target_phys_addr_t addr
, uint32_t value
)
1128 ppc405_gpio_t
*gpio
;
1132 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1136 static uint32_t ppc405_gpio_readl (void *opaque
, target_phys_addr_t addr
)
1138 ppc405_gpio_t
*gpio
;
1142 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1148 static void ppc405_gpio_writel (void *opaque
,
1149 target_phys_addr_t addr
, uint32_t value
)
1151 ppc405_gpio_t
*gpio
;
1155 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1159 static CPUReadMemoryFunc
*ppc405_gpio_read
[] = {
1165 static CPUWriteMemoryFunc
*ppc405_gpio_write
[] = {
1166 &ppc405_gpio_writeb
,
1167 &ppc405_gpio_writew
,
1168 &ppc405_gpio_writel
,
1171 static void ppc405_gpio_reset (void *opaque
)
1173 ppc405_gpio_t
*gpio
;
1178 void ppc405_gpio_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
1179 target_phys_addr_t offset
)
1181 ppc405_gpio_t
*gpio
;
1183 gpio
= qemu_mallocz(sizeof(ppc405_gpio_t
));
1185 gpio
->base
= offset
;
1186 ppc405_gpio_reset(gpio
);
1187 qemu_register_reset(&ppc405_gpio_reset
, gpio
);
1189 printf("%s: offset=" PADDRX
"\n", __func__
, offset
);
1191 ppc4xx_mmio_register(env
, mmio
, offset
, 0x038,
1192 ppc405_gpio_read
, ppc405_gpio_write
, gpio
);
1196 /*****************************************************************************/
1198 static CPUReadMemoryFunc
*serial_mm_read
[] = {
1204 static CPUWriteMemoryFunc
*serial_mm_write
[] = {
1210 void ppc405_serial_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
1211 target_phys_addr_t offset
, qemu_irq irq
,
1212 CharDriverState
*chr
)
1217 printf("%s: offset=" PADDRX
"\n", __func__
, offset
);
1219 serial
= serial_mm_init(offset
, 0, irq
, chr
, 0);
1220 ppc4xx_mmio_register(env
, mmio
, offset
, 0x008,
1221 serial_mm_read
, serial_mm_write
, serial
);
1224 /*****************************************************************************/
1225 /* On Chip Memory */
1228 OCM0_ISACNTL
= 0x019,
1230 OCM0_DSACNTL
= 0x01B,
1233 typedef struct ppc405_ocm_t ppc405_ocm_t
;
1234 struct ppc405_ocm_t
{
1235 target_ulong offset
;
1242 static void ocm_update_mappings (ppc405_ocm_t
*ocm
,
1243 uint32_t isarc
, uint32_t isacntl
,
1244 uint32_t dsarc
, uint32_t dsacntl
)
1247 printf("OCM update ISA %08x %08x (%08x %08x) DSA %08x %08x (%08x %08x)\n",
1248 isarc
, isacntl
, dsarc
, dsacntl
,
1249 ocm
->isarc
, ocm
->isacntl
, ocm
->dsarc
, ocm
->dsacntl
);
1251 if (ocm
->isarc
!= isarc
||
1252 (ocm
->isacntl
& 0x80000000) != (isacntl
& 0x80000000)) {
1253 if (ocm
->isacntl
& 0x80000000) {
1254 /* Unmap previously assigned memory region */
1255 printf("OCM unmap ISA %08x\n", ocm
->isarc
);
1256 cpu_register_physical_memory(ocm
->isarc
, 0x04000000,
1259 if (isacntl
& 0x80000000) {
1260 /* Map new instruction memory region */
1262 printf("OCM map ISA %08x\n", isarc
);
1264 cpu_register_physical_memory(isarc
, 0x04000000,
1265 ocm
->offset
| IO_MEM_RAM
);
1268 if (ocm
->dsarc
!= dsarc
||
1269 (ocm
->dsacntl
& 0x80000000) != (dsacntl
& 0x80000000)) {
1270 if (ocm
->dsacntl
& 0x80000000) {
1271 /* Beware not to unmap the region we just mapped */
1272 if (!(isacntl
& 0x80000000) || ocm
->dsarc
!= isarc
) {
1273 /* Unmap previously assigned memory region */
1275 printf("OCM unmap DSA %08x\n", ocm
->dsarc
);
1277 cpu_register_physical_memory(ocm
->dsarc
, 0x04000000,
1281 if (dsacntl
& 0x80000000) {
1282 /* Beware not to remap the region we just mapped */
1283 if (!(isacntl
& 0x80000000) || dsarc
!= isarc
) {
1284 /* Map new data memory region */
1286 printf("OCM map DSA %08x\n", dsarc
);
1288 cpu_register_physical_memory(dsarc
, 0x04000000,
1289 ocm
->offset
| IO_MEM_RAM
);
1295 static target_ulong
dcr_read_ocm (void *opaque
, int dcrn
)
1322 static void dcr_write_ocm (void *opaque
, int dcrn
, target_ulong val
)
1325 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
1330 isacntl
= ocm
->isacntl
;
1331 dsacntl
= ocm
->dsacntl
;
1334 isarc
= val
& 0xFC000000;
1337 isacntl
= val
& 0xC0000000;
1340 isarc
= val
& 0xFC000000;
1343 isacntl
= val
& 0xC0000000;
1346 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
1349 ocm
->isacntl
= isacntl
;
1350 ocm
->dsacntl
= dsacntl
;
1353 static void ocm_reset (void *opaque
)
1356 uint32_t isarc
, dsarc
, isacntl
, dsacntl
;
1360 isacntl
= 0x00000000;
1362 dsacntl
= 0x00000000;
1363 ocm_update_mappings(ocm
, isarc
, isacntl
, dsarc
, dsacntl
);
1366 ocm
->isacntl
= isacntl
;
1367 ocm
->dsacntl
= dsacntl
;
1370 void ppc405_ocm_init (CPUState
*env
, unsigned long offset
)
1374 ocm
= qemu_mallocz(sizeof(ppc405_ocm_t
));
1376 ocm
->offset
= offset
;
1378 qemu_register_reset(&ocm_reset
, ocm
);
1379 ppc_dcr_register(env
, OCM0_ISARC
,
1380 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
1381 ppc_dcr_register(env
, OCM0_ISACNTL
,
1382 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
1383 ppc_dcr_register(env
, OCM0_DSARC
,
1384 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
1385 ppc_dcr_register(env
, OCM0_DSACNTL
,
1386 ocm
, &dcr_read_ocm
, &dcr_write_ocm
);
1390 /*****************************************************************************/
1391 /* I2C controller */
1392 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t
;
1393 struct ppc4xx_i2c_t
{
1394 target_phys_addr_t base
;
1413 static uint32_t ppc4xx_i2c_readb (void *opaque
, target_phys_addr_t addr
)
1419 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1422 switch (addr
- i2c
->base
) {
1424 // i2c_readbyte(&i2c->mdata);
1464 ret
= i2c
->xtcntlss
;
1467 ret
= i2c
->directcntl
;
1474 printf("%s: addr " PADDRX
" %02x\n", __func__
, addr
, ret
);
1480 static void ppc4xx_i2c_writeb (void *opaque
,
1481 target_phys_addr_t addr
, uint32_t value
)
1486 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1489 switch (addr
- i2c
->base
) {
1492 // i2c_sendbyte(&i2c->mdata);
1507 i2c
->mdcntl
= value
& 0xDF;
1510 i2c
->sts
&= ~(value
& 0x0A);
1513 i2c
->extsts
&= ~(value
& 0x8F);
1522 i2c
->clkdiv
= value
;
1525 i2c
->intrmsk
= value
;
1528 i2c
->xfrcnt
= value
& 0x77;
1531 i2c
->xtcntlss
= value
;
1534 i2c
->directcntl
= value
& 0x7;
1539 static uint32_t ppc4xx_i2c_readw (void *opaque
, target_phys_addr_t addr
)
1544 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1546 ret
= ppc4xx_i2c_readb(opaque
, addr
) << 8;
1547 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 1);
1552 static void ppc4xx_i2c_writew (void *opaque
,
1553 target_phys_addr_t addr
, uint32_t value
)
1556 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1558 ppc4xx_i2c_writeb(opaque
, addr
, value
>> 8);
1559 ppc4xx_i2c_writeb(opaque
, addr
+ 1, value
);
1562 static uint32_t ppc4xx_i2c_readl (void *opaque
, target_phys_addr_t addr
)
1567 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1569 ret
= ppc4xx_i2c_readb(opaque
, addr
) << 24;
1570 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 1) << 16;
1571 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 2) << 8;
1572 ret
|= ppc4xx_i2c_readb(opaque
, addr
+ 3);
1577 static void ppc4xx_i2c_writel (void *opaque
,
1578 target_phys_addr_t addr
, uint32_t value
)
1581 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1583 ppc4xx_i2c_writeb(opaque
, addr
, value
>> 24);
1584 ppc4xx_i2c_writeb(opaque
, addr
+ 1, value
>> 16);
1585 ppc4xx_i2c_writeb(opaque
, addr
+ 2, value
>> 8);
1586 ppc4xx_i2c_writeb(opaque
, addr
+ 3, value
);
1589 static CPUReadMemoryFunc
*i2c_read
[] = {
1595 static CPUWriteMemoryFunc
*i2c_write
[] = {
1601 static void ppc4xx_i2c_reset (void *opaque
)
1614 i2c
->directcntl
= 0x0F;
1617 void ppc405_i2c_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
1618 target_phys_addr_t offset
, qemu_irq irq
)
1622 i2c
= qemu_mallocz(sizeof(ppc4xx_i2c_t
));
1626 ppc4xx_i2c_reset(i2c
);
1628 printf("%s: offset=" PADDRX
"\n", __func__
, offset
);
1630 ppc4xx_mmio_register(env
, mmio
, offset
, 0x011,
1631 i2c_read
, i2c_write
, i2c
);
1632 qemu_register_reset(ppc4xx_i2c_reset
, i2c
);
1636 /*****************************************************************************/
1637 /* General purpose timers */
1638 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t
;
1639 struct ppc4xx_gpt_t
{
1640 target_phys_addr_t base
;
1643 struct QEMUTimer
*timer
;
1654 static uint32_t ppc4xx_gpt_readb (void *opaque
, target_phys_addr_t addr
)
1657 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1659 /* XXX: generate a bus fault */
1663 static void ppc4xx_gpt_writeb (void *opaque
,
1664 target_phys_addr_t addr
, uint32_t value
)
1667 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1669 /* XXX: generate a bus fault */
1672 static uint32_t ppc4xx_gpt_readw (void *opaque
, target_phys_addr_t addr
)
1675 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1677 /* XXX: generate a bus fault */
1681 static void ppc4xx_gpt_writew (void *opaque
,
1682 target_phys_addr_t addr
, uint32_t value
)
1685 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1687 /* XXX: generate a bus fault */
1690 static int ppc4xx_gpt_compare (ppc4xx_gpt_t
*gpt
, int n
)
1696 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t
*gpt
, int n
, int level
)
1701 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t
*gpt
)
1707 for (i
= 0; i
< 5; i
++) {
1708 if (gpt
->oe
& mask
) {
1709 /* Output is enabled */
1710 if (ppc4xx_gpt_compare(gpt
, i
)) {
1711 /* Comparison is OK */
1712 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
);
1714 /* Comparison is KO */
1715 ppc4xx_gpt_set_output(gpt
, i
, gpt
->ol
& mask
? 0 : 1);
1722 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t
*gpt
)
1728 for (i
= 0; i
< 5; i
++) {
1729 if (gpt
->is
& gpt
->im
& mask
)
1730 qemu_irq_raise(gpt
->irqs
[i
]);
1732 qemu_irq_lower(gpt
->irqs
[i
]);
1737 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t
*gpt
)
1742 static uint32_t ppc4xx_gpt_readl (void *opaque
, target_phys_addr_t addr
)
1749 printf("%s: addr " PADDRX
"\n", __func__
, addr
);
1752 switch (addr
- gpt
->base
) {
1754 /* Time base counter */
1755 ret
= muldiv64(qemu_get_clock(vm_clock
) + gpt
->tb_offset
,
1756 gpt
->tb_freq
, ticks_per_sec
);
1767 /* Interrupt mask */
1772 /* Interrupt status */
1776 /* Interrupt enable */
1781 idx
= ((addr
- gpt
->base
) - 0x80) >> 2;
1782 ret
= gpt
->comp
[idx
];
1786 idx
= ((addr
- gpt
->base
) - 0xC0) >> 2;
1787 ret
= gpt
->mask
[idx
];
1797 static void ppc4xx_gpt_writel (void *opaque
,
1798 target_phys_addr_t addr
, uint32_t value
)
1804 printf("%s: addr " PADDRX
" val %08x\n", __func__
, addr
, value
);
1807 switch (addr
- gpt
->base
) {
1809 /* Time base counter */
1810 gpt
->tb_offset
= muldiv64(value
, ticks_per_sec
, gpt
->tb_freq
)
1811 - qemu_get_clock(vm_clock
);
1812 ppc4xx_gpt_compute_timer(gpt
);
1816 gpt
->oe
= value
& 0xF8000000;
1817 ppc4xx_gpt_set_outputs(gpt
);
1821 gpt
->ol
= value
& 0xF8000000;
1822 ppc4xx_gpt_set_outputs(gpt
);
1825 /* Interrupt mask */
1826 gpt
->im
= value
& 0x0000F800;
1829 /* Interrupt status set */
1830 gpt
->is
|= value
& 0x0000F800;
1831 ppc4xx_gpt_set_irqs(gpt
);
1834 /* Interrupt status clear */
1835 gpt
->is
&= ~(value
& 0x0000F800);
1836 ppc4xx_gpt_set_irqs(gpt
);
1839 /* Interrupt enable */
1840 gpt
->ie
= value
& 0x0000F800;
1841 ppc4xx_gpt_set_irqs(gpt
);
1845 idx
= ((addr
- gpt
->base
) - 0x80) >> 2;
1846 gpt
->comp
[idx
] = value
& 0xF8000000;
1847 ppc4xx_gpt_compute_timer(gpt
);
1851 idx
= ((addr
- gpt
->base
) - 0xC0) >> 2;
1852 gpt
->mask
[idx
] = value
& 0xF8000000;
1853 ppc4xx_gpt_compute_timer(gpt
);
1858 static CPUReadMemoryFunc
*gpt_read
[] = {
1864 static CPUWriteMemoryFunc
*gpt_write
[] = {
1870 static void ppc4xx_gpt_cb (void *opaque
)
1875 ppc4xx_gpt_set_irqs(gpt
);
1876 ppc4xx_gpt_set_outputs(gpt
);
1877 ppc4xx_gpt_compute_timer(gpt
);
1880 static void ppc4xx_gpt_reset (void *opaque
)
1886 qemu_del_timer(gpt
->timer
);
1887 gpt
->oe
= 0x00000000;
1888 gpt
->ol
= 0x00000000;
1889 gpt
->im
= 0x00000000;
1890 gpt
->is
= 0x00000000;
1891 gpt
->ie
= 0x00000000;
1892 for (i
= 0; i
< 5; i
++) {
1893 gpt
->comp
[i
] = 0x00000000;
1894 gpt
->mask
[i
] = 0x00000000;
1898 void ppc4xx_gpt_init (CPUState
*env
, ppc4xx_mmio_t
*mmio
,
1899 target_phys_addr_t offset
, qemu_irq irqs
[5])
1904 gpt
= qemu_mallocz(sizeof(ppc4xx_gpt_t
));
1907 for (i
= 0; i
< 5; i
++)
1908 gpt
->irqs
[i
] = irqs
[i
];
1909 gpt
->timer
= qemu_new_timer(vm_clock
, &ppc4xx_gpt_cb
, gpt
);
1910 ppc4xx_gpt_reset(gpt
);
1912 printf("%s: offset=" PADDRX
"\n", __func__
, offset
);
1914 ppc4xx_mmio_register(env
, mmio
, offset
, 0x0D4,
1915 gpt_read
, gpt_write
, gpt
);
1916 qemu_register_reset(ppc4xx_gpt_reset
, gpt
);
1920 /*****************************************************************************/
1926 MAL0_TXCASR
= 0x184,
1927 MAL0_TXCARR
= 0x185,
1928 MAL0_TXEOBISR
= 0x186,
1929 MAL0_TXDEIR
= 0x187,
1930 MAL0_RXCASR
= 0x190,
1931 MAL0_RXCARR
= 0x191,
1932 MAL0_RXEOBISR
= 0x192,
1933 MAL0_RXDEIR
= 0x193,
1934 MAL0_TXCTP0R
= 0x1A0,
1935 MAL0_TXCTP1R
= 0x1A1,
1936 MAL0_TXCTP2R
= 0x1A2,
1937 MAL0_TXCTP3R
= 0x1A3,
1938 MAL0_RXCTP0R
= 0x1C0,
1939 MAL0_RXCTP1R
= 0x1C1,
1944 typedef struct ppc40x_mal_t ppc40x_mal_t
;
1945 struct ppc40x_mal_t
{
1963 static void ppc40x_mal_reset (void *opaque
);
1965 static target_ulong
dcr_read_mal (void *opaque
, int dcrn
)
1988 ret
= mal
->txeobisr
;
2000 ret
= mal
->rxeobisr
;
2006 ret
= mal
->txctpr
[0];
2009 ret
= mal
->txctpr
[1];
2012 ret
= mal
->txctpr
[2];
2015 ret
= mal
->txctpr
[3];
2018 ret
= mal
->rxctpr
[0];
2021 ret
= mal
->rxctpr
[1];
2037 static void dcr_write_mal (void *opaque
, int dcrn
, target_ulong val
)
2045 if (val
& 0x80000000)
2046 ppc40x_mal_reset(mal
);
2047 mal
->cfg
= val
& 0x00FFC087;
2054 mal
->ier
= val
& 0x0000001F;
2057 mal
->txcasr
= val
& 0xF0000000;
2060 mal
->txcarr
= val
& 0xF0000000;
2064 mal
->txeobisr
&= ~val
;
2068 mal
->txdeir
&= ~val
;
2071 mal
->rxcasr
= val
& 0xC0000000;
2074 mal
->rxcarr
= val
& 0xC0000000;
2078 mal
->rxeobisr
&= ~val
;
2082 mal
->rxdeir
&= ~val
;
2096 mal
->txctpr
[idx
] = val
;
2104 mal
->rxctpr
[idx
] = val
;
2108 goto update_rx_size
;
2112 mal
->rcbs
[idx
] = val
& 0x000000FF;
2117 static void ppc40x_mal_reset (void *opaque
)
2122 mal
->cfg
= 0x0007C000;
2123 mal
->esr
= 0x00000000;
2124 mal
->ier
= 0x00000000;
2125 mal
->rxcasr
= 0x00000000;
2126 mal
->rxdeir
= 0x00000000;
2127 mal
->rxeobisr
= 0x00000000;
2128 mal
->txcasr
= 0x00000000;
2129 mal
->txdeir
= 0x00000000;
2130 mal
->txeobisr
= 0x00000000;
2133 void ppc405_mal_init (CPUState
*env
, qemu_irq irqs
[4])
2138 mal
= qemu_mallocz(sizeof(ppc40x_mal_t
));
2140 for (i
= 0; i
< 4; i
++)
2141 mal
->irqs
[i
] = irqs
[i
];
2142 ppc40x_mal_reset(mal
);
2143 qemu_register_reset(&ppc40x_mal_reset
, mal
);
2144 ppc_dcr_register(env
, MAL0_CFG
,
2145 mal
, &dcr_read_mal
, &dcr_write_mal
);
2146 ppc_dcr_register(env
, MAL0_ESR
,
2147 mal
, &dcr_read_mal
, &dcr_write_mal
);
2148 ppc_dcr_register(env
, MAL0_IER
,
2149 mal
, &dcr_read_mal
, &dcr_write_mal
);
2150 ppc_dcr_register(env
, MAL0_TXCASR
,
2151 mal
, &dcr_read_mal
, &dcr_write_mal
);
2152 ppc_dcr_register(env
, MAL0_TXCARR
,
2153 mal
, &dcr_read_mal
, &dcr_write_mal
);
2154 ppc_dcr_register(env
, MAL0_TXEOBISR
,
2155 mal
, &dcr_read_mal
, &dcr_write_mal
);
2156 ppc_dcr_register(env
, MAL0_TXDEIR
,
2157 mal
, &dcr_read_mal
, &dcr_write_mal
);
2158 ppc_dcr_register(env
, MAL0_RXCASR
,
2159 mal
, &dcr_read_mal
, &dcr_write_mal
);
2160 ppc_dcr_register(env
, MAL0_RXCARR
,
2161 mal
, &dcr_read_mal
, &dcr_write_mal
);
2162 ppc_dcr_register(env
, MAL0_RXEOBISR
,
2163 mal
, &dcr_read_mal
, &dcr_write_mal
);
2164 ppc_dcr_register(env
, MAL0_RXDEIR
,
2165 mal
, &dcr_read_mal
, &dcr_write_mal
);
2166 ppc_dcr_register(env
, MAL0_TXCTP0R
,
2167 mal
, &dcr_read_mal
, &dcr_write_mal
);
2168 ppc_dcr_register(env
, MAL0_TXCTP1R
,
2169 mal
, &dcr_read_mal
, &dcr_write_mal
);
2170 ppc_dcr_register(env
, MAL0_TXCTP2R
,
2171 mal
, &dcr_read_mal
, &dcr_write_mal
);
2172 ppc_dcr_register(env
, MAL0_TXCTP3R
,
2173 mal
, &dcr_read_mal
, &dcr_write_mal
);
2174 ppc_dcr_register(env
, MAL0_RXCTP0R
,
2175 mal
, &dcr_read_mal
, &dcr_write_mal
);
2176 ppc_dcr_register(env
, MAL0_RXCTP1R
,
2177 mal
, &dcr_read_mal
, &dcr_write_mal
);
2178 ppc_dcr_register(env
, MAL0_RCBS0
,
2179 mal
, &dcr_read_mal
, &dcr_write_mal
);
2180 ppc_dcr_register(env
, MAL0_RCBS1
,
2181 mal
, &dcr_read_mal
, &dcr_write_mal
);
2185 /*****************************************************************************/
2187 void ppc40x_core_reset (CPUState
*env
)
2191 printf("Reset PowerPC core\n");
2192 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
2197 qemu_system_reset_request();
2199 dbsr
= env
->spr
[SPR_40x_DBSR
];
2200 dbsr
&= ~0x00000300;
2202 env
->spr
[SPR_40x_DBSR
] = dbsr
;
2205 void ppc40x_chip_reset (CPUState
*env
)
2209 printf("Reset PowerPC chip\n");
2210 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
2215 qemu_system_reset_request();
2217 /* XXX: TODO reset all internal peripherals */
2218 dbsr
= env
->spr
[SPR_40x_DBSR
];
2219 dbsr
&= ~0x00000300;
2221 env
->spr
[SPR_40x_DBSR
] = dbsr
;
2224 void ppc40x_system_reset (CPUState
*env
)
2226 printf("Reset PowerPC system\n");
2227 qemu_system_reset_request();
2230 void store_40x_dbcr0 (CPUState
*env
, uint32_t val
)
2232 switch ((val
>> 28) & 0x3) {
2238 ppc40x_core_reset(env
);
2242 ppc40x_chip_reset(env
);
2246 ppc40x_system_reset(env
);
2251 /*****************************************************************************/
2254 PPC405CR_CPC0_PLLMR
= 0x0B0,
2255 PPC405CR_CPC0_CR0
= 0x0B1,
2256 PPC405CR_CPC0_CR1
= 0x0B2,
2257 PPC405CR_CPC0_PSR
= 0x0B4,
2258 PPC405CR_CPC0_JTAGID
= 0x0B5,
2259 PPC405CR_CPC0_ER
= 0x0B9,
2260 PPC405CR_CPC0_FR
= 0x0BA,
2261 PPC405CR_CPC0_SR
= 0x0BB,
2265 PPC405CR_CPU_CLK
= 0,
2266 PPC405CR_TMR_CLK
= 1,
2267 PPC405CR_PLB_CLK
= 2,
2268 PPC405CR_SDRAM_CLK
= 3,
2269 PPC405CR_OPB_CLK
= 4,
2270 PPC405CR_EXT_CLK
= 5,
2271 PPC405CR_UART_CLK
= 6,
2272 PPC405CR_CLK_NB
= 7,
2275 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t
;
2276 struct ppc405cr_cpc_t
{
2277 clk_setup_t clk_setup
[PPC405CR_CLK_NB
];
2288 static void ppc405cr_clk_setup (ppc405cr_cpc_t
*cpc
)
2290 uint64_t VCO_out
, PLL_out
;
2291 uint32_t CPU_clk
, TMR_clk
, SDRAM_clk
, PLB_clk
, OPB_clk
, EXT_clk
, UART_clk
;
2294 D0
= ((cpc
->pllmr
>> 26) & 0x3) + 1; /* CBDV */
2295 if (cpc
->pllmr
& 0x80000000) {
2296 D1
= (((cpc
->pllmr
>> 20) - 1) & 0xF) + 1; /* FBDV */
2297 D2
= 8 - ((cpc
->pllmr
>> 16) & 0x7); /* FWDVA */
2299 VCO_out
= cpc
->sysclk
* M
;
2300 if (VCO_out
< 400000000 || VCO_out
> 800000000) {
2301 /* PLL cannot lock */
2302 cpc
->pllmr
&= ~0x80000000;
2305 PLL_out
= VCO_out
/ D2
;
2310 PLL_out
= cpc
->sysclk
* M
;
2313 if (cpc
->cr1
& 0x00800000)
2314 TMR_clk
= cpc
->sysclk
; /* Should have a separate clock */
2317 PLB_clk
= CPU_clk
/ D0
;
2318 SDRAM_clk
= PLB_clk
;
2319 D0
= ((cpc
->pllmr
>> 10) & 0x3) + 1;
2320 OPB_clk
= PLB_clk
/ D0
;
2321 D0
= ((cpc
->pllmr
>> 24) & 0x3) + 2;
2322 EXT_clk
= PLB_clk
/ D0
;
2323 D0
= ((cpc
->cr0
>> 1) & 0x1F) + 1;
2324 UART_clk
= CPU_clk
/ D0
;
2325 /* Setup CPU clocks */
2326 clk_setup(&cpc
->clk_setup
[PPC405CR_CPU_CLK
], CPU_clk
);
2327 /* Setup time-base clock */
2328 clk_setup(&cpc
->clk_setup
[PPC405CR_TMR_CLK
], TMR_clk
);
2329 /* Setup PLB clock */
2330 clk_setup(&cpc
->clk_setup
[PPC405CR_PLB_CLK
], PLB_clk
);
2331 /* Setup SDRAM clock */
2332 clk_setup(&cpc
->clk_setup
[PPC405CR_SDRAM_CLK
], SDRAM_clk
);
2333 /* Setup OPB clock */
2334 clk_setup(&cpc
->clk_setup
[PPC405CR_OPB_CLK
], OPB_clk
);
2335 /* Setup external clock */
2336 clk_setup(&cpc
->clk_setup
[PPC405CR_EXT_CLK
], EXT_clk
);
2337 /* Setup UART clock */
2338 clk_setup(&cpc
->clk_setup
[PPC405CR_UART_CLK
], UART_clk
);
2341 static target_ulong
dcr_read_crcpc (void *opaque
, int dcrn
)
2343 ppc405cr_cpc_t
*cpc
;
2348 case PPC405CR_CPC0_PLLMR
:
2351 case PPC405CR_CPC0_CR0
:
2354 case PPC405CR_CPC0_CR1
:
2357 case PPC405CR_CPC0_PSR
:
2360 case PPC405CR_CPC0_JTAGID
:
2363 case PPC405CR_CPC0_ER
:
2366 case PPC405CR_CPC0_FR
:
2369 case PPC405CR_CPC0_SR
:
2370 ret
= ~(cpc
->er
| cpc
->fr
) & 0xFFFF0000;
2373 /* Avoid gcc warning */
2381 static void dcr_write_crcpc (void *opaque
, int dcrn
, target_ulong val
)
2383 ppc405cr_cpc_t
*cpc
;
2387 case PPC405CR_CPC0_PLLMR
:
2388 cpc
->pllmr
= val
& 0xFFF77C3F;
2390 case PPC405CR_CPC0_CR0
:
2391 cpc
->cr0
= val
& 0x0FFFFFFE;
2393 case PPC405CR_CPC0_CR1
:
2394 cpc
->cr1
= val
& 0x00800000;
2396 case PPC405CR_CPC0_PSR
:
2399 case PPC405CR_CPC0_JTAGID
:
2402 case PPC405CR_CPC0_ER
:
2403 cpc
->er
= val
& 0xBFFC0000;
2405 case PPC405CR_CPC0_FR
:
2406 cpc
->fr
= val
& 0xBFFC0000;
2408 case PPC405CR_CPC0_SR
:
2414 static void ppc405cr_cpc_reset (void *opaque
)
2416 ppc405cr_cpc_t
*cpc
;
2420 /* Compute PLLMR value from PSR settings */
2421 cpc
->pllmr
= 0x80000000;
2423 switch ((cpc
->psr
>> 30) & 3) {
2426 cpc
->pllmr
&= ~0x80000000;
2430 cpc
->pllmr
|= 5 << 16;
2434 cpc
->pllmr
|= 4 << 16;
2438 cpc
->pllmr
|= 2 << 16;
2442 D
= (cpc
->psr
>> 28) & 3;
2443 cpc
->pllmr
|= (D
+ 1) << 20;
2445 D
= (cpc
->psr
>> 25) & 7;
2460 D
= (cpc
->psr
>> 23) & 3;
2461 cpc
->pllmr
|= D
<< 26;
2463 D
= (cpc
->psr
>> 21) & 3;
2464 cpc
->pllmr
|= D
<< 10;
2466 D
= (cpc
->psr
>> 17) & 3;
2467 cpc
->pllmr
|= D
<< 24;
2468 cpc
->cr0
= 0x0000003C;
2469 cpc
->cr1
= 0x2B0D8800;
2470 cpc
->er
= 0x00000000;
2471 cpc
->fr
= 0x00000000;
2472 ppc405cr_clk_setup(cpc
);
2475 static void ppc405cr_clk_init (ppc405cr_cpc_t
*cpc
)
2479 /* XXX: this should be read from IO pins */
2480 cpc
->psr
= 0x00000000; /* 8 bits ROM */
2482 D
= 0x2; /* Divide by 4 */
2483 cpc
->psr
|= D
<< 30;
2485 D
= 0x1; /* Divide by 2 */
2486 cpc
->psr
|= D
<< 28;
2488 D
= 0x1; /* Divide by 2 */
2489 cpc
->psr
|= D
<< 23;
2491 D
= 0x5; /* M = 16 */
2492 cpc
->psr
|= D
<< 25;
2494 D
= 0x1; /* Divide by 2 */
2495 cpc
->psr
|= D
<< 21;
2497 D
= 0x2; /* Divide by 4 */
2498 cpc
->psr
|= D
<< 17;
2501 static void ppc405cr_cpc_init (CPUState
*env
, clk_setup_t clk_setup
[7],
2504 ppc405cr_cpc_t
*cpc
;
2506 cpc
= qemu_mallocz(sizeof(ppc405cr_cpc_t
));
2508 memcpy(cpc
->clk_setup
, clk_setup
,
2509 PPC405CR_CLK_NB
* sizeof(clk_setup_t
));
2510 cpc
->sysclk
= sysclk
;
2511 cpc
->jtagid
= 0x42051049;
2512 ppc_dcr_register(env
, PPC405CR_CPC0_PSR
, cpc
,
2513 &dcr_read_crcpc
, &dcr_write_crcpc
);
2514 ppc_dcr_register(env
, PPC405CR_CPC0_CR0
, cpc
,
2515 &dcr_read_crcpc
, &dcr_write_crcpc
);
2516 ppc_dcr_register(env
, PPC405CR_CPC0_CR1
, cpc
,
2517 &dcr_read_crcpc
, &dcr_write_crcpc
);
2518 ppc_dcr_register(env
, PPC405CR_CPC0_JTAGID
, cpc
,
2519 &dcr_read_crcpc
, &dcr_write_crcpc
);
2520 ppc_dcr_register(env
, PPC405CR_CPC0_PLLMR
, cpc
,
2521 &dcr_read_crcpc
, &dcr_write_crcpc
);
2522 ppc_dcr_register(env
, PPC405CR_CPC0_ER
, cpc
,
2523 &dcr_read_crcpc
, &dcr_write_crcpc
);
2524 ppc_dcr_register(env
, PPC405CR_CPC0_FR
, cpc
,
2525 &dcr_read_crcpc
, &dcr_write_crcpc
);
2526 ppc_dcr_register(env
, PPC405CR_CPC0_SR
, cpc
,
2527 &dcr_read_crcpc
, &dcr_write_crcpc
);
2528 ppc405cr_clk_init(cpc
);
2529 qemu_register_reset(ppc405cr_cpc_reset
, cpc
);
2530 ppc405cr_cpc_reset(cpc
);
2534 CPUState
*ppc405cr_init (target_phys_addr_t ram_bases
[4],
2535 target_phys_addr_t ram_sizes
[4],
2536 uint32_t sysclk
, qemu_irq
**picp
,
2537 ram_addr_t
*offsetp
, int do_init
)
2539 clk_setup_t clk_setup
[PPC405CR_CLK_NB
];
2540 qemu_irq dma_irqs
[4];
2542 ppc4xx_mmio_t
*mmio
;
2543 qemu_irq
*pic
, *irqs
;
2547 memset(clk_setup
, 0, sizeof(clk_setup
));
2548 env
= ppc4xx_init("405cr", &clk_setup
[PPC405CR_CPU_CLK
],
2549 &clk_setup
[PPC405CR_TMR_CLK
], sysclk
);
2550 /* Memory mapped devices registers */
2551 mmio
= ppc4xx_mmio_init(env
, 0xEF600000);
2553 ppc4xx_plb_init(env
);
2554 /* PLB to OPB bridge */
2555 ppc4xx_pob_init(env
);
2557 ppc4xx_opba_init(env
, mmio
, 0x600);
2558 /* Universal interrupt controller */
2559 irqs
= qemu_mallocz(sizeof(qemu_irq
) * PPCUIC_OUTPUT_NB
);
2560 irqs
[PPCUIC_OUTPUT_INT
] =
2561 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_INT
];
2562 irqs
[PPCUIC_OUTPUT_CINT
] =
2563 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_CINT
];
2564 pic
= ppcuic_init(env
, irqs
, 0x0C0, 0, 1);
2566 /* SDRAM controller */
2567 ppc405_sdram_init(env
, pic
[14], 1, ram_bases
, ram_sizes
, do_init
);
2569 for (i
= 0; i
< 4; i
++)
2570 offset
+= ram_sizes
[i
];
2571 /* External bus controller */
2572 ppc405_ebc_init(env
);
2573 /* DMA controller */
2574 dma_irqs
[0] = pic
[26];
2575 dma_irqs
[1] = pic
[25];
2576 dma_irqs
[2] = pic
[24];
2577 dma_irqs
[3] = pic
[23];
2578 ppc405_dma_init(env
, dma_irqs
);
2580 if (serial_hds
[0] != NULL
) {
2581 ppc405_serial_init(env
, mmio
, 0x300, pic
[31], serial_hds
[0]);
2583 if (serial_hds
[1] != NULL
) {
2584 ppc405_serial_init(env
, mmio
, 0x400, pic
[30], serial_hds
[1]);
2586 /* IIC controller */
2587 ppc405_i2c_init(env
, mmio
, 0x500, pic
[29]);
2589 ppc405_gpio_init(env
, mmio
, 0x700);
2591 ppc405cr_cpc_init(env
, clk_setup
, sysclk
);
2597 /*****************************************************************************/
2601 PPC405EP_CPC0_PLLMR0
= 0x0F0,
2602 PPC405EP_CPC0_BOOT
= 0x0F1,
2603 PPC405EP_CPC0_EPCTL
= 0x0F3,
2604 PPC405EP_CPC0_PLLMR1
= 0x0F4,
2605 PPC405EP_CPC0_UCR
= 0x0F5,
2606 PPC405EP_CPC0_SRR
= 0x0F6,
2607 PPC405EP_CPC0_JTAGID
= 0x0F7,
2608 PPC405EP_CPC0_PCI
= 0x0F9,
2610 PPC405EP_CPC0_ER
= xxx
,
2611 PPC405EP_CPC0_FR
= xxx
,
2612 PPC405EP_CPC0_SR
= xxx
,
2617 PPC405EP_CPU_CLK
= 0,
2618 PPC405EP_PLB_CLK
= 1,
2619 PPC405EP_OPB_CLK
= 2,
2620 PPC405EP_EBC_CLK
= 3,
2621 PPC405EP_MAL_CLK
= 4,
2622 PPC405EP_PCI_CLK
= 5,
2623 PPC405EP_UART0_CLK
= 6,
2624 PPC405EP_UART1_CLK
= 7,
2625 PPC405EP_CLK_NB
= 8,
2628 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t
;
2629 struct ppc405ep_cpc_t
{
2631 clk_setup_t clk_setup
[PPC405EP_CLK_NB
];
2639 /* Clock and power management */
2645 static void ppc405ep_compute_clocks (ppc405ep_cpc_t
*cpc
)
2647 uint32_t CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
;
2648 uint32_t UART0_clk
, UART1_clk
;
2649 uint64_t VCO_out
, PLL_out
;
2653 if ((cpc
->pllmr
[1] & 0x80000000) && !(cpc
->pllmr
[1] & 0x40000000)) {
2654 M
= (((cpc
->pllmr
[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2655 // printf("FBMUL %01x %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2656 D
= 8 - ((cpc
->pllmr
[1] >> 16) & 0x7); /* FWDA */
2657 // printf("FWDA %01x %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2658 VCO_out
= cpc
->sysclk
* M
* D
;
2659 if (VCO_out
< 500000000UL || VCO_out
> 1000000000UL) {
2660 /* Error - unlock the PLL */
2661 printf("VCO out of range %" PRIu64
"\n", VCO_out
);
2663 cpc
->pllmr
[1] &= ~0x80000000;
2667 PLL_out
= VCO_out
/ D
;
2668 /* Pretend the PLL is locked */
2669 cpc
->boot
|= 0x00000001;
2674 PLL_out
= cpc
->sysclk
;
2675 if (cpc
->pllmr
[1] & 0x40000000) {
2676 /* Pretend the PLL is not locked */
2677 cpc
->boot
&= ~0x00000001;
2680 /* Now, compute all other clocks */
2681 D
= ((cpc
->pllmr
[0] >> 20) & 0x3) + 1; /* CCDV */
2683 // printf("CCDV %01x %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2685 CPU_clk
= PLL_out
/ D
;
2686 D
= ((cpc
->pllmr
[0] >> 16) & 0x3) + 1; /* CBDV */
2688 // printf("CBDV %01x %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2690 PLB_clk
= CPU_clk
/ D
;
2691 D
= ((cpc
->pllmr
[0] >> 12) & 0x3) + 1; /* OPDV */
2693 // printf("OPDV %01x %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2695 OPB_clk
= PLB_clk
/ D
;
2696 D
= ((cpc
->pllmr
[0] >> 8) & 0x3) + 2; /* EPDV */
2698 // printf("EPDV %01x %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2700 EBC_clk
= PLB_clk
/ D
;
2701 D
= ((cpc
->pllmr
[0] >> 4) & 0x3) + 1; /* MPDV */
2703 // printf("MPDV %01x %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2705 MAL_clk
= PLB_clk
/ D
;
2706 D
= (cpc
->pllmr
[0] & 0x3) + 1; /* PPDV */
2708 // printf("PPDV %01x %d\n", cpc->pllmr[0] & 0x3, D);
2710 PCI_clk
= PLB_clk
/ D
;
2711 D
= ((cpc
->ucr
- 1) & 0x7F) + 1; /* U0DIV */
2713 // printf("U0DIV %01x %d\n", cpc->ucr & 0x7F, D);
2715 UART0_clk
= PLL_out
/ D
;
2716 D
= (((cpc
->ucr
>> 8) - 1) & 0x7F) + 1; /* U1DIV */
2718 // printf("U1DIV %01x %d\n", (cpc->ucr >> 8) & 0x7F, D);
2720 UART1_clk
= PLL_out
/ D
;
2722 printf("Setup PPC405EP clocks - sysclk %d VCO %" PRIu64
2723 " PLL out %" PRIu64
" Hz\n", cpc
->sysclk
, VCO_out
, PLL_out
);
2724 printf("CPU %d PLB %d OPB %d EBC %d MAL %d PCI %d UART0 %d UART1 %d\n",
2725 CPU_clk
, PLB_clk
, OPB_clk
, EBC_clk
, MAL_clk
, PCI_clk
,
2726 UART0_clk
, UART1_clk
);
2727 printf("CB %p opaque %p\n", cpc
->clk_setup
[PPC405EP_CPU_CLK
].cb
,
2728 cpc
->clk_setup
[PPC405EP_CPU_CLK
].opaque
);
2730 /* Setup CPU clocks */
2731 clk_setup(&cpc
->clk_setup
[PPC405EP_CPU_CLK
], CPU_clk
);
2732 /* Setup PLB clock */
2733 clk_setup(&cpc
->clk_setup
[PPC405EP_PLB_CLK
], PLB_clk
);
2734 /* Setup OPB clock */
2735 clk_setup(&cpc
->clk_setup
[PPC405EP_OPB_CLK
], OPB_clk
);
2736 /* Setup external clock */
2737 clk_setup(&cpc
->clk_setup
[PPC405EP_EBC_CLK
], EBC_clk
);
2738 /* Setup MAL clock */
2739 clk_setup(&cpc
->clk_setup
[PPC405EP_MAL_CLK
], MAL_clk
);
2740 /* Setup PCI clock */
2741 clk_setup(&cpc
->clk_setup
[PPC405EP_PCI_CLK
], PCI_clk
);
2742 /* Setup UART0 clock */
2743 clk_setup(&cpc
->clk_setup
[PPC405EP_UART0_CLK
], UART0_clk
);
2744 /* Setup UART1 clock */
2745 clk_setup(&cpc
->clk_setup
[PPC405EP_UART1_CLK
], UART1_clk
);
2748 static target_ulong
dcr_read_epcpc (void *opaque
, int dcrn
)
2750 ppc405ep_cpc_t
*cpc
;
2755 case PPC405EP_CPC0_BOOT
:
2758 case PPC405EP_CPC0_EPCTL
:
2761 case PPC405EP_CPC0_PLLMR0
:
2762 ret
= cpc
->pllmr
[0];
2764 case PPC405EP_CPC0_PLLMR1
:
2765 ret
= cpc
->pllmr
[1];
2767 case PPC405EP_CPC0_UCR
:
2770 case PPC405EP_CPC0_SRR
:
2773 case PPC405EP_CPC0_JTAGID
:
2776 case PPC405EP_CPC0_PCI
:
2780 /* Avoid gcc warning */
2788 static void dcr_write_epcpc (void *opaque
, int dcrn
, target_ulong val
)
2790 ppc405ep_cpc_t
*cpc
;
2794 case PPC405EP_CPC0_BOOT
:
2795 /* Read-only register */
2797 case PPC405EP_CPC0_EPCTL
:
2798 /* Don't care for now */
2799 cpc
->epctl
= val
& 0xC00000F3;
2801 case PPC405EP_CPC0_PLLMR0
:
2802 cpc
->pllmr
[0] = val
& 0x00633333;
2803 ppc405ep_compute_clocks(cpc
);
2805 case PPC405EP_CPC0_PLLMR1
:
2806 cpc
->pllmr
[1] = val
& 0xC0F73FFF;
2807 ppc405ep_compute_clocks(cpc
);
2809 case PPC405EP_CPC0_UCR
:
2810 /* UART control - don't care for now */
2811 cpc
->ucr
= val
& 0x003F7F7F;
2813 case PPC405EP_CPC0_SRR
:
2816 case PPC405EP_CPC0_JTAGID
:
2819 case PPC405EP_CPC0_PCI
:
2825 static void ppc405ep_cpc_reset (void *opaque
)
2827 ppc405ep_cpc_t
*cpc
= opaque
;
2829 cpc
->boot
= 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2830 cpc
->epctl
= 0x00000000;
2831 cpc
->pllmr
[0] = 0x00011010;
2832 cpc
->pllmr
[1] = 0x40000000;
2833 cpc
->ucr
= 0x00000000;
2834 cpc
->srr
= 0x00040000;
2835 cpc
->pci
= 0x00000000;
2836 cpc
->er
= 0x00000000;
2837 cpc
->fr
= 0x00000000;
2838 cpc
->sr
= 0x00000000;
2839 ppc405ep_compute_clocks(cpc
);
2842 /* XXX: sysclk should be between 25 and 100 MHz */
2843 static void ppc405ep_cpc_init (CPUState
*env
, clk_setup_t clk_setup
[8],
2846 ppc405ep_cpc_t
*cpc
;
2848 cpc
= qemu_mallocz(sizeof(ppc405ep_cpc_t
));
2850 memcpy(cpc
->clk_setup
, clk_setup
,
2851 PPC405EP_CLK_NB
* sizeof(clk_setup_t
));
2852 cpc
->jtagid
= 0x20267049;
2853 cpc
->sysclk
= sysclk
;
2854 ppc405ep_cpc_reset(cpc
);
2855 qemu_register_reset(&ppc405ep_cpc_reset
, cpc
);
2856 ppc_dcr_register(env
, PPC405EP_CPC0_BOOT
, cpc
,
2857 &dcr_read_epcpc
, &dcr_write_epcpc
);
2858 ppc_dcr_register(env
, PPC405EP_CPC0_EPCTL
, cpc
,
2859 &dcr_read_epcpc
, &dcr_write_epcpc
);
2860 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR0
, cpc
,
2861 &dcr_read_epcpc
, &dcr_write_epcpc
);
2862 ppc_dcr_register(env
, PPC405EP_CPC0_PLLMR1
, cpc
,
2863 &dcr_read_epcpc
, &dcr_write_epcpc
);
2864 ppc_dcr_register(env
, PPC405EP_CPC0_UCR
, cpc
,
2865 &dcr_read_epcpc
, &dcr_write_epcpc
);
2866 ppc_dcr_register(env
, PPC405EP_CPC0_SRR
, cpc
,
2867 &dcr_read_epcpc
, &dcr_write_epcpc
);
2868 ppc_dcr_register(env
, PPC405EP_CPC0_JTAGID
, cpc
,
2869 &dcr_read_epcpc
, &dcr_write_epcpc
);
2870 ppc_dcr_register(env
, PPC405EP_CPC0_PCI
, cpc
,
2871 &dcr_read_epcpc
, &dcr_write_epcpc
);
2873 ppc_dcr_register(env
, PPC405EP_CPC0_ER
, cpc
,
2874 &dcr_read_epcpc
, &dcr_write_epcpc
);
2875 ppc_dcr_register(env
, PPC405EP_CPC0_FR
, cpc
,
2876 &dcr_read_epcpc
, &dcr_write_epcpc
);
2877 ppc_dcr_register(env
, PPC405EP_CPC0_SR
, cpc
,
2878 &dcr_read_epcpc
, &dcr_write_epcpc
);
2883 CPUState
*ppc405ep_init (target_phys_addr_t ram_bases
[2],
2884 target_phys_addr_t ram_sizes
[2],
2885 uint32_t sysclk
, qemu_irq
**picp
,
2886 ram_addr_t
*offsetp
, int do_init
)
2888 clk_setup_t clk_setup
[PPC405EP_CLK_NB
], tlb_clk_setup
;
2889 qemu_irq dma_irqs
[4], gpt_irqs
[5], mal_irqs
[4];
2891 ppc4xx_mmio_t
*mmio
;
2892 qemu_irq
*pic
, *irqs
;
2896 memset(clk_setup
, 0, sizeof(clk_setup
));
2898 env
= ppc4xx_init("405ep", &clk_setup
[PPC405EP_CPU_CLK
],
2899 &tlb_clk_setup
, sysclk
);
2900 clk_setup
[PPC405EP_CPU_CLK
].cb
= tlb_clk_setup
.cb
;
2901 clk_setup
[PPC405EP_CPU_CLK
].opaque
= tlb_clk_setup
.opaque
;
2902 /* Internal devices init */
2903 /* Memory mapped devices registers */
2904 mmio
= ppc4xx_mmio_init(env
, 0xEF600000);
2906 ppc4xx_plb_init(env
);
2907 /* PLB to OPB bridge */
2908 ppc4xx_pob_init(env
);
2910 ppc4xx_opba_init(env
, mmio
, 0x600);
2911 /* Universal interrupt controller */
2912 irqs
= qemu_mallocz(sizeof(qemu_irq
) * PPCUIC_OUTPUT_NB
);
2913 irqs
[PPCUIC_OUTPUT_INT
] =
2914 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_INT
];
2915 irqs
[PPCUIC_OUTPUT_CINT
] =
2916 ((qemu_irq
*)env
->irq_inputs
)[PPC40x_INPUT_CINT
];
2917 pic
= ppcuic_init(env
, irqs
, 0x0C0, 0, 1);
2919 /* SDRAM controller */
2920 ppc405_sdram_init(env
, pic
[14], 2, ram_bases
, ram_sizes
, do_init
);
2922 for (i
= 0; i
< 2; i
++)
2923 offset
+= ram_sizes
[i
];
2924 /* External bus controller */
2925 ppc405_ebc_init(env
);
2926 /* DMA controller */
2927 dma_irqs
[0] = pic
[26];
2928 dma_irqs
[1] = pic
[25];
2929 dma_irqs
[2] = pic
[24];
2930 dma_irqs
[3] = pic
[23];
2931 ppc405_dma_init(env
, dma_irqs
);
2932 /* IIC controller */
2933 ppc405_i2c_init(env
, mmio
, 0x500, pic
[29]);
2935 ppc405_gpio_init(env
, mmio
, 0x700);
2937 if (serial_hds
[0] != NULL
) {
2938 ppc405_serial_init(env
, mmio
, 0x300, pic
[31], serial_hds
[0]);
2940 if (serial_hds
[1] != NULL
) {
2941 ppc405_serial_init(env
, mmio
, 0x400, pic
[30], serial_hds
[1]);
2944 ppc405_ocm_init(env
, ram_sizes
[0] + ram_sizes
[1]);
2947 gpt_irqs
[0] = pic
[12];
2948 gpt_irqs
[1] = pic
[11];
2949 gpt_irqs
[2] = pic
[10];
2950 gpt_irqs
[3] = pic
[9];
2951 gpt_irqs
[4] = pic
[8];
2952 ppc4xx_gpt_init(env
, mmio
, 0x000, gpt_irqs
);
2954 /* Uses pic[28], pic[15], pic[13] */
2956 mal_irqs
[0] = pic
[20];
2957 mal_irqs
[1] = pic
[19];
2958 mal_irqs
[2] = pic
[18];
2959 mal_irqs
[3] = pic
[17];
2960 ppc405_mal_init(env
, mal_irqs
);
2962 /* Uses pic[22], pic[16], pic[14] */
2964 ppc405ep_cpc_init(env
, clk_setup
, sysclk
);