2 * QEMU PPC CHRP/PMAC hardware System Emulator
4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #define BIOS_FILENAME "ppc_rom.bin"
27 #define VGABIOS_FILENAME "video.x"
28 #define NVRAM_SIZE 0x2000
30 #define KERNEL_LOAD_ADDR 0x01000000
31 #define INITRD_LOAD_ADDR 0x01800000
33 /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
34 NVRAM (not implemented). */
36 static int dbdma_mem_index
;
37 static int cuda_mem_index
;
38 static int ide0_mem_index
= -1;
39 static int ide1_mem_index
= -1;
40 static int openpic_mem_index
= -1;
41 static int heathrow_pic_mem_index
= -1;
43 /* DBDMA: currently no op - should suffice right now */
45 static void dbdma_writeb (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
47 printf("%s: 0x%08x <= 0x%08x\n", __func__
, addr
, value
);
50 static void dbdma_writew (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
54 static void dbdma_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
58 static uint32_t dbdma_readb (void *opaque
, target_phys_addr_t addr
)
60 printf("%s: 0x%08x => 0x00000000\n", __func__
, addr
);
64 static uint32_t dbdma_readw (void *opaque
, target_phys_addr_t addr
)
69 static uint32_t dbdma_readl (void *opaque
, target_phys_addr_t addr
)
74 static CPUWriteMemoryFunc
*dbdma_write
[] = {
80 static CPUReadMemoryFunc
*dbdma_read
[] = {
86 static void macio_map(PCIDevice
*pci_dev
, int region_num
,
87 uint32_t addr
, uint32_t size
, int type
)
89 if (heathrow_pic_mem_index
>= 0) {
90 cpu_register_physical_memory(addr
+ 0x00000, 0x1000,
91 heathrow_pic_mem_index
);
93 cpu_register_physical_memory(addr
+ 0x08000, 0x1000, dbdma_mem_index
);
94 cpu_register_physical_memory(addr
+ 0x16000, 0x2000, cuda_mem_index
);
95 if (ide0_mem_index
>= 0)
96 cpu_register_physical_memory(addr
+ 0x1f000, 0x1000, ide0_mem_index
);
97 if (ide1_mem_index
>= 0)
98 cpu_register_physical_memory(addr
+ 0x20000, 0x1000, ide1_mem_index
);
99 if (openpic_mem_index
>= 0) {
100 cpu_register_physical_memory(addr
+ 0x40000, 0x40000,
105 static void macio_init(PCIBus
*bus
)
109 d
= pci_register_device(bus
, "macio", sizeof(PCIDevice
),
111 /* Note: this code is strongly inspirated from the corresponding code
113 d
->config
[0x00] = 0x6b; // vendor_id
114 d
->config
[0x01] = 0x10;
115 d
->config
[0x02] = 0x22;
116 d
->config
[0x03] = 0x00;
118 d
->config
[0x0a] = 0x00; // class_sub = pci2pci
119 d
->config
[0x0b] = 0xff; // class_base = bridge
120 d
->config
[0x0e] = 0x00; // header_type
122 d
->config
[0x3d] = 0x01; // interrupt on pin 1
124 dbdma_mem_index
= cpu_register_io_memory(0, dbdma_read
, dbdma_write
, NULL
);
126 pci_register_io_region(d
, 0, 0x80000,
127 PCI_ADDRESS_SPACE_MEM
, macio_map
);
131 static void unin_writel (void *opaque
, target_phys_addr_t addr
, uint32_t value
)
135 static uint32_t unin_readl (void *opaque
, target_phys_addr_t addr
)
140 static CPUWriteMemoryFunc
*unin_write
[] = {
146 static CPUReadMemoryFunc
*unin_read
[] = {
152 /* temporary frame buffer OSI calls for the video.x driver. The right
153 solution is to modify the driver to use VGA PCI I/Os */
154 static int vga_osi_call(CPUState
*env
)
156 static int vga_vbl_enabled
;
159 // printf("osi_call R5=%d\n", env->gpr[5]);
161 /* same handler as PearPC, coming from the original MOL video
163 switch(env
->gpr
[5]) {
166 case 28: /* set_vmode */
167 if (env
->gpr
[6] != 1 || env
->gpr
[7] != 0)
172 case 29: /* get_vmode_info */
173 if (env
->gpr
[6] != 0) {
174 if (env
->gpr
[6] != 1 || env
->gpr
[7] != 0) {
180 env
->gpr
[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
181 env
->gpr
[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
182 env
->gpr
[6] = (graphic_width
<< 16) | graphic_height
; /* w, h */
183 env
->gpr
[7] = 85 << 16; /* refresh rate */
184 env
->gpr
[8] = (graphic_depth
+ 7) & ~7; /* depth (round to byte) */
185 linesize
= ((graphic_depth
+ 7) >> 3) * graphic_width
;
186 linesize
= (linesize
+ 3) & ~3;
187 env
->gpr
[9] = (linesize
<< 16) | 0; /* row_bytes, offset */
189 case 31: /* set_video power */
192 case 39: /* video_ctrl */
193 if (env
->gpr
[6] == 0 || env
->gpr
[6] == 1)
194 vga_vbl_enabled
= env
->gpr
[6];
199 case 59: /* set_color */
200 /* R6 = index, R7 = RGB */
203 case 64: /* get color */
207 case 116: /* set hwcursor */
208 /* R6 = x, R7 = y, R8 = visible, R9 = data */
211 fprintf(stderr
, "unsupported OSI call R5=%08x\n", env
->gpr
[5]);
214 return 1; /* osi_call handled */
217 /* XXX: suppress that */
218 static void pic_irq_request(void *opaque
, int level
)
222 /* PowerPC CHRP hardware initialisation */
223 static void ppc_chrp_init(int ram_size
, int vga_ram_size
, int boot_device
,
224 DisplayState
*ds
, const char **fd_filename
,
226 const char *kernel_filename
,
227 const char *kernel_cmdline
,
228 const char *initrd_filename
,
235 int PPC_io_memory
, unin_memory
;
237 unsigned long bios_offset
, vga_bios_offset
;
238 uint32_t kernel_base
, kernel_size
, initrd_base
, initrd_size
;
241 const char *arch_name
;
242 int vga_bios_size
, bios_size
;
244 linux_boot
= (kernel_filename
!= NULL
);
247 cpu_register_physical_memory(0, ram_size
, IO_MEM_RAM
);
249 /* allocate and load BIOS */
250 bios_offset
= ram_size
+ vga_ram_size
;
251 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, BIOS_FILENAME
);
252 bios_size
= load_image(buf
, phys_ram_base
+ bios_offset
);
253 if (bios_size
< 0 || bios_size
> BIOS_SIZE
) {
254 fprintf(stderr
, "qemu: could not load PowerPC bios '%s'\n", buf
);
257 bios_size
= (bios_size
+ 0xfff) & ~0xfff;
258 cpu_register_physical_memory((uint32_t)(-bios_size
),
259 bios_size
, bios_offset
| IO_MEM_ROM
);
261 /* allocate and load VGA BIOS */
262 vga_bios_offset
= bios_offset
+ bios_size
;
263 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, VGABIOS_FILENAME
);
264 vga_bios_size
= load_image(buf
, phys_ram_base
+ vga_bios_offset
+ 8);
265 if (vga_bios_size
< 0) {
266 /* if no bios is present, we can still work */
267 fprintf(stderr
, "qemu: warning: could not load VGA bios '%s'\n", buf
);
270 /* set a specific header (XXX: find real Apple format for NDRV
272 phys_ram_base
[vga_bios_offset
] = 'N';
273 phys_ram_base
[vga_bios_offset
+ 1] = 'D';
274 phys_ram_base
[vga_bios_offset
+ 2] = 'R';
275 phys_ram_base
[vga_bios_offset
+ 3] = 'V';
276 cpu_to_be32w((uint32_t *)(phys_ram_base
+ vga_bios_offset
+ 4),
280 vga_bios_size
= (vga_bios_size
+ 0xfff) & ~0xfff;
283 kernel_base
= KERNEL_LOAD_ADDR
;
284 /* now we can load the kernel */
285 kernel_size
= load_image(kernel_filename
, phys_ram_base
+ kernel_base
);
286 if (kernel_size
< 0) {
287 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
292 if (initrd_filename
) {
293 initrd_base
= INITRD_LOAD_ADDR
;
294 initrd_size
= load_image(initrd_filename
,
295 phys_ram_base
+ initrd_base
);
296 if (initrd_size
< 0) {
297 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
312 /* Register CPU as a 74x/75x */
313 /* XXX: CPU model (or PVR) should be provided on command line */
314 // ppc_find_by_name("750gx", &def); // Linux boot OK
315 // ppc_find_by_name("750fx", &def); // Linux boot OK
316 /* Linux does not boot on 750cxe (and probably other 750cx based)
317 * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
319 // ppc_find_by_name("750cxe", &def);
320 // ppc_find_by_name("750p", &def);
321 // ppc_find_by_name("740p", &def);
322 ppc_find_by_name("750", &def
);
323 // ppc_find_by_name("740", &def);
324 // ppc_find_by_name("G3", &def);
325 // ppc_find_by_name("604r", &def);
326 // ppc_find_by_name("604e", &def);
327 // ppc_find_by_name("604", &def);
329 cpu_abort(cpu_single_env
, "Unable to find PowerPC CPU definition\n");
331 cpu_ppc_register(cpu_single_env
, def
);
333 /* Set time-base frequency to 100 Mhz */
334 cpu_ppc_tb_init(cpu_single_env
, 100UL * 1000UL * 1000UL);
336 cpu_single_env
->osi_call
= vga_osi_call
;
339 isa_mem_base
= 0x80000000;
340 pci_bus
= pci_grackle_init(0xfec00000);
342 /* Register 2 MB of ISA IO space */
343 PPC_io_memory
= cpu_register_io_memory(0, PPC_io_read
, PPC_io_write
, NULL
);
344 cpu_register_physical_memory(0xfe000000, 0x00200000, PPC_io_memory
);
346 /* init basic PC hardware */
347 vga_initialize(pci_bus
, ds
, phys_ram_base
+ ram_size
,
348 ram_size
, vga_ram_size
,
349 vga_bios_offset
, vga_bios_size
);
350 pic
= heathrow_pic_init(&heathrow_pic_mem_index
);
351 set_irq
= heathrow_pic_set_irq
;
352 pci_set_pic(pci_bus
, set_irq
, pic
);
354 /* XXX: suppress that */
355 isa_pic
= pic_init(pic_irq_request
, NULL
);
357 /* XXX: use Mac Serial port */
358 serial_init(0x3f8, 4, serial_hds
[0]);
360 for(i
= 0; i
< nb_nics
; i
++) {
361 pci_ne2000_init(pci_bus
, &nd_table
[i
]);
364 pci_cmd646_ide_init(pci_bus
, &bs_table
[0], 0);
366 /* cuda also initialize ADB */
367 cuda_mem_index
= cuda_init(set_irq
, pic
, 0x12);
369 adb_kbd_init(&adb_bus
);
370 adb_mouse_init(&adb_bus
);
374 nvram
= m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE
);
376 arch_name
= "HEATHROW";
378 isa_mem_base
= 0x80000000;
379 pci_bus
= pci_pmac_init();
381 /* Register 8 MB of ISA IO space */
382 PPC_io_memory
= cpu_register_io_memory(0, PPC_io_read
, PPC_io_write
, NULL
);
383 cpu_register_physical_memory(0xF2000000, 0x00800000, PPC_io_memory
);
386 unin_memory
= cpu_register_io_memory(0, unin_read
, unin_write
, NULL
);
387 cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory
);
389 /* init basic PC hardware */
390 vga_initialize(pci_bus
, ds
, phys_ram_base
+ ram_size
,
391 ram_size
, vga_ram_size
,
392 vga_bios_offset
, vga_bios_size
);
393 pic
= openpic_init(NULL
, &openpic_mem_index
, 1);
394 set_irq
= openpic_set_irq
;
395 pci_set_pic(pci_bus
, set_irq
, pic
);
397 /* XXX: suppress that */
398 isa_pic
= pic_init(pic_irq_request
, NULL
);
400 /* XXX: use Mac Serial port */
401 serial_init(0x3f8, 4, serial_hds
[0]);
403 for(i
= 0; i
< nb_nics
; i
++) {
404 pci_ne2000_init(pci_bus
, &nd_table
[i
]);
408 ide0_mem_index
= pmac_ide_init(&bs_table
[0], set_irq
, pic
, 0x13);
409 ide1_mem_index
= pmac_ide_init(&bs_table
[2], set_irq
, pic
, 0x14);
411 pci_cmd646_ide_init(pci_bus
, &bs_table
[0], 0);
413 /* cuda also initialize ADB */
414 cuda_mem_index
= cuda_init(set_irq
, pic
, 0x19);
416 adb_kbd_init(&adb_bus
);
417 adb_mouse_init(&adb_bus
);
421 nvram
= m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE
);
426 if (graphic_depth
!= 15 && graphic_depth
!= 32 && graphic_depth
!= 8)
429 PPC_NVRAM_set_params(nvram
, NVRAM_SIZE
, arch_name
, ram_size
, boot_device
,
430 kernel_base
, kernel_size
,
432 initrd_base
, initrd_size
,
433 /* XXX: need an option to load a NVRAM image */
435 graphic_width
, graphic_height
, graphic_depth
);
436 /* No PCI init: the BIOS will do it */
438 /* Special port to get debug messages from Open-Firmware */
439 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write
, NULL
);
442 static void ppc_core99_init(int ram_size
, int vga_ram_size
, int boot_device
,
443 DisplayState
*ds
, const char **fd_filename
,
445 const char *kernel_filename
,
446 const char *kernel_cmdline
,
447 const char *initrd_filename
)
449 ppc_chrp_init(ram_size
, vga_ram_size
, boot_device
,
450 ds
, fd_filename
, snapshot
,
451 kernel_filename
, kernel_cmdline
,
455 static void ppc_heathrow_init(int ram_size
, int vga_ram_size
, int boot_device
,
456 DisplayState
*ds
, const char **fd_filename
,
458 const char *kernel_filename
,
459 const char *kernel_cmdline
,
460 const char *initrd_filename
)
462 ppc_chrp_init(ram_size
, vga_ram_size
, boot_device
,
463 ds
, fd_filename
, snapshot
,
464 kernel_filename
, kernel_cmdline
,
468 QEMUMachine core99_machine
= {
470 "Mac99 based PowerMAC",
474 QEMUMachine heathrow_machine
= {
476 "Heathrow based PowerMAC",