hw/ppc_newworld.c

   1 /*
   2  * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * PCI bus layout on a real G5 (U3 based):
  26  *
  27  * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
  28  * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
  29  * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
  30  * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  31  * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  32  * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
  33  * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
  34  * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
  35  * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
  36  * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
  37  * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
  38  * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  39  * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  40  * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  41  * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  42  * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
  43  * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
  44  * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
  45  * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
  46  * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
  47  *
  48  */
  49 #include "hw.h"
  50 #include "ppc.h"
  51 #include "ppc_mac.h"
  52 #include "adb.h"
  53 #include "mac_dbdma.h"
  54 #include "nvram.h"
  55 #include "pci/pci.h"
  56 #include "net.h"
  57 #include "sysemu.h"
  58 #include "boards.h"
  59 #include "fw_cfg.h"
  60 #include "escc.h"
  61 #include "openpic.h"
  62 #include "ide.h"
  63 #include "loader.h"
  64 #include "elf.h"
  65 #include "kvm.h"
  66 #include "kvm_ppc.h"
  67 #include "hw/usb.h"
  68 #include "blockdev.h"
  69 #include "exec-memory.h"
  70
  71 #define MAX_IDE_BUS 2
  72 #define CFG_ADDR 0xf0000510
  73
  74 /* debug UniNorth */
  75 //#define DEBUG_UNIN
  76
  77 #ifdef DEBUG_UNIN
  78 #define UNIN_DPRINTF(fmt, ...)                                  \
  79     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  80 #else
  81 #define UNIN_DPRINTF(fmt, ...)
  82 #endif
  83
  84 /* UniN device */
  85 static void unin_write(void *opaque, hwaddr addr, uint64_t value,
  86                        unsigned size)
  87 {
  88     UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
  89 }
  90
  91 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
  92 {
  93     uint32_t value;
  94
  95     value = 0;
  96     UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
  97
  98     return value;
  99 }
 100
 101 static const MemoryRegionOps unin_ops = {
 102     .read = unin_read,
 103     .write = unin_write,
 104     .endianness = DEVICE_NATIVE_ENDIAN,
 105 };
 106
 107 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 108 {
 109     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 110     return 0;
 111 }
 112
 113 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
 114 {
 115     return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
 116 }
 117
 118 static hwaddr round_page(hwaddr addr)
 119 {
 120     return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
 121 }
 122
 123 static void ppc_core99_reset(void *opaque)
 124 {
 125     PowerPCCPU *cpu = opaque;
 126
 127     cpu_reset(CPU(cpu));
 128 }
 129
 130 /* PowerPC Mac99 hardware initialisation */
 131 static void ppc_core99_init(QEMUMachineInitArgs *args)
 132 {
 133     ram_addr_t ram_size = args->ram_size;
 134     const char *cpu_model = args->cpu_model;
 135     const char *kernel_filename = args->kernel_filename;
 136     const char *kernel_cmdline = args->kernel_cmdline;
 137     const char *initrd_filename = args->initrd_filename;
 138     const char *boot_device = args->boot_device;
 139     PowerPCCPU *cpu = NULL;
 140     CPUPPCState *env = NULL;
 141     char *filename;
 142     qemu_irq *pic, **openpic_irqs;
 143     MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
 144     int linux_boot, i;
 145     MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
 146     hwaddr kernel_base, initrd_base, cmdline_base = 0;
 147     long kernel_size, initrd_size;
 148     PCIBus *pci_bus;
 149     MacIONVRAMState *nvr;
 150     int bios_size;
 151     MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem;
 152     MemoryRegion *escc_bar = g_new(MemoryRegion, 1);
 153     MemoryRegion *ide_mem[3];
 154     int ppc_boot_device;
 155     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 156     void *fw_cfg;
 157     void *dbdma;
 158     int machine_arch;
 159
 160     linux_boot = (kernel_filename != NULL);
 161
 162     /* init CPUs */
 163     if (cpu_model == NULL)
 164 #ifdef TARGET_PPC64
 165         cpu_model = "970fx";
 166 #else
 167         cpu_model = "G4";
 168 #endif
 169     for (i = 0; i < smp_cpus; i++) {
 170         cpu = cpu_ppc_init(cpu_model);
 171         if (cpu == NULL) {
 172             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 173             exit(1);
 174         }
 175         env = &cpu->env;
 176
 177         /* Set time-base frequency to 100 Mhz */
 178         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 179         qemu_register_reset(ppc_core99_reset, cpu);
 180     }
 181
 182     /* allocate RAM */
 183     memory_region_init_ram(ram, "ppc_core99.ram", ram_size);
 184     vmstate_register_ram_global(ram);
 185     memory_region_add_subregion(get_system_memory(), 0, ram);
 186
 187     /* allocate and load BIOS */
 188     memory_region_init_ram(bios, "ppc_core99.bios", BIOS_SIZE);
 189     vmstate_register_ram_global(bios);
 190     if (bios_name == NULL)
 191         bios_name = PROM_FILENAME;
 192     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 193     memory_region_set_readonly(bios, true);
 194     memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
 195
 196     /* Load OpenBIOS (ELF) */
 197     if (filename) {
 198         bios_size = load_elf(filename, NULL, NULL, NULL,
 199                              NULL, NULL, 1, ELF_MACHINE, 0);
 200
 201         g_free(filename);
 202     } else {
 203         bios_size = -1;
 204     }
 205     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 206         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 207         exit(1);
 208     }
 209
 210     if (linux_boot) {
 211         uint64_t lowaddr = 0;
 212         int bswap_needed;
 213
 214 #ifdef BSWAP_NEEDED
 215         bswap_needed = 1;
 216 #else
 217         bswap_needed = 0;
 218 #endif
 219         kernel_base = KERNEL_LOAD_ADDR;
 220
 221         kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
 222                                NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
 223         if (kernel_size < 0)
 224             kernel_size = load_aout(kernel_filename, kernel_base,
 225                                     ram_size - kernel_base, bswap_needed,
 226                                     TARGET_PAGE_SIZE);
 227         if (kernel_size < 0)
 228             kernel_size = load_image_targphys(kernel_filename,
 229                                               kernel_base,
 230                                               ram_size - kernel_base);
 231         if (kernel_size < 0) {
 232             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 233             exit(1);
 234         }
 235         /* load initrd */
 236         if (initrd_filename) {
 237             initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 238             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 239                                               ram_size - initrd_base);
 240             if (initrd_size < 0) {
 241                 hw_error("qemu: could not load initial ram disk '%s'\n",
 242                          initrd_filename);
 243                 exit(1);
 244             }
 245             cmdline_base = round_page(initrd_base + initrd_size);
 246         } else {
 247             initrd_base = 0;
 248             initrd_size = 0;
 249             cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
 250         }
 251         ppc_boot_device = 'm';
 252     } else {
 253         kernel_base = 0;
 254         kernel_size = 0;
 255         initrd_base = 0;
 256         initrd_size = 0;
 257         ppc_boot_device = '\0';
 258         /* We consider that NewWorld PowerMac never have any floppy drive
 259          * For now, OHW cannot boot from the network.
 260          */
 261         for (i = 0; boot_device[i] != '\0'; i++) {
 262             if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
 263                 ppc_boot_device = boot_device[i];
 264                 break;
 265             }
 266         }
 267         if (ppc_boot_device == '\0') {
 268             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 269             exit(1);
 270         }
 271     }
 272
 273     /* Register 8 MB of ISA IO space */
 274     isa_mmio_init(0xf2000000, 0x00800000);
 275
 276     /* UniN init */
 277     memory_region_init_io(unin_memory, &unin_ops, NULL, "unin", 0x1000);
 278     memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
 279
 280     openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 281     openpic_irqs[0] =
 282         g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 283     for (i = 0; i < smp_cpus; i++) {
 284         /* Mac99 IRQ connection between OpenPIC outputs pins
 285          * and PowerPC input pins
 286          */
 287         switch (PPC_INPUT(env)) {
 288         case PPC_FLAGS_INPUT_6xx:
 289             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 290             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 291                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 292             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 293                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 294             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 295                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
 296             /* Not connected ? */
 297             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 298             /* Check this */
 299             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 300                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
 301             break;
 302 #if defined(TARGET_PPC64)
 303         case PPC_FLAGS_INPUT_970:
 304             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 305             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 306                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 307             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 308                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 309             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 310                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
 311             /* Not connected ? */
 312             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 313             /* Check this */
 314             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 315                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
 316             break;
 317 #endif /* defined(TARGET_PPC64) */
 318         default:
 319             hw_error("Bus model not supported on mac99 machine\n");
 320             exit(1);
 321         }
 322     }
 323     pic = openpic_init(&pic_mem, smp_cpus, openpic_irqs, NULL);
 324     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
 325         /* 970 gets a U3 bus */
 326         pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
 327         machine_arch = ARCH_MAC99_U3;
 328     } else {
 329         pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
 330         machine_arch = ARCH_MAC99;
 331     }
 332     /* init basic PC hardware */
 333     pci_vga_init(pci_bus);
 334
 335     escc_mem = escc_init(0, pic[0x25], pic[0x24],
 336                          serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
 337     memory_region_init_alias(escc_bar, "escc-bar",
 338                              escc_mem, 0, memory_region_size(escc_mem));
 339
 340     for(i = 0; i < nb_nics; i++)
 341         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 342
 343     ide_drive_get(hd, MAX_IDE_BUS);
 344     dbdma = DBDMA_init(&dbdma_mem);
 345
 346     /* We only emulate 2 out of 3 IDE controllers for now */
 347     ide_mem[0] = NULL;
 348     ide_mem[1] = pmac_ide_init(hd, pic[0x0d], dbdma, 0x16, pic[0x02]);
 349     ide_mem[2] = pmac_ide_init(&hd[MAX_IDE_DEVS], pic[0x0e], dbdma, 0x1a, pic[0x02]);
 350
 351     cuda_init(&cuda_mem, pic[0x19]);
 352
 353     adb_kbd_init(&adb_bus);
 354     adb_mouse_init(&adb_bus);
 355
 356     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem,
 357                dbdma_mem, cuda_mem, NULL, 3, ide_mem, escc_bar);
 358
 359     if (usb_enabled(machine_arch == ARCH_MAC99_U3)) {
 360         pci_create_simple(pci_bus, -1, "pci-ohci");
 361         /* U3 needs to use USB for input because Linux doesn't support via-cuda
 362         on PPC64 */
 363         if (machine_arch == ARCH_MAC99_U3) {
 364             usbdevice_create("keyboard");
 365             usbdevice_create("mouse");
 366         }
 367     }
 368
 369     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 370         graphic_depth = 15;
 371
 372     /* The NewWorld NVRAM is not located in the MacIO device */
 373     nvr = macio_nvram_init(0x2000, 1);
 374     pmac_format_nvram_partition(nvr, 0x2000);
 375     macio_nvram_setup_bar(nvr, get_system_memory(), 0xFFF04000);
 376     /* No PCI init: the BIOS will do it */
 377
 378     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 379     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 380     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 381     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
 382     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 383     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 384     if (kernel_cmdline) {
 385         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
 386         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
 387     } else {
 388         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 389     }
 390     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 391     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 392     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 393
 394     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 395     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 396     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 397
 398     fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
 399     if (kvm_enabled()) {
 400 #ifdef CONFIG_KVM
 401         uint8_t *hypercall;
 402
 403         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
 404         hypercall = g_malloc(16);
 405         kvmppc_get_hypercall(env, hypercall, 16);
 406         fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
 407         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
 408 #endif
 409     } else {
 410         fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, get_ticks_per_sec());
 411     }
 412
 413     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 414 }
 415
 416 static QEMUMachine core99_machine = {
 417     .name = "mac99",
 418     .desc = "Mac99 based PowerMAC",
 419     .init = ppc_core99_init,
 420     .max_cpus = MAX_CPUS,
 421 #ifdef TARGET_PPC64
 422     .is_default = 1,
 423 #endif
 424 };
 425
 426 static void core99_machine_init(void)
 427 {
 428     qemu_register_machine(&core99_machine);
 429 }
 430
 431 machine_init(core99_machine_init);