hw/ppc_newworld.c

   1 /*
   2  * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * PCI bus layout on a real G5 (U3 based):
  26  *
  27  * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
  28  * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
  29  * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
  30  * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  31  * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
  32  * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
  33  * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
  34  * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
  35  * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
  36  * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
  37  * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
  38  * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  39  * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
  40  * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  41  * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
  42  * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
  43  * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
  44  * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
  45  * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
  46  * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
  47  *
  48  */
  49 #include "hw.h"
  50 #include "ppc.h"
  51 #include "ppc_mac.h"
  52 #include "mac_dbdma.h"
  53 #include "nvram.h"
  54 #include "pc.h"
  55 #include "pci.h"
  56 #include "usb-ohci.h"
  57 #include "net.h"
  58 #include "sysemu.h"
  59 #include "boards.h"
  60 #include "fw_cfg.h"
  61 #include "escc.h"
  62 #include "openpic.h"
  63 #include "ide.h"
  64 #include "loader.h"
  65 #include "elf.h"
  66 #include "kvm.h"
  67
  68 #define MAX_IDE_BUS 2
  69 #define VGA_BIOS_SIZE 65536
  70 #define CFG_ADDR 0xf0000510
  71
  72 /* debug UniNorth */
  73 //#define DEBUG_UNIN
  74
  75 #ifdef DEBUG_UNIN
  76 #define UNIN_DPRINTF(fmt, ...)                                  \
  77     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  78 #else
  79 #define UNIN_DPRINTF(fmt, ...)
  80 #endif
  81
  82 /* UniN device */
  83 static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
  84 {
  85     UNIN_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", addr, value);
  86 }
  87
  88 static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
  89 {
  90     uint32_t value;
  91
  92     value = 0;
  93     UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value);
  94
  95     return value;
  96 }
  97
  98 static CPUWriteMemoryFunc * const unin_write[] = {
  99     &unin_writel,
 100     &unin_writel,
 101     &unin_writel,
 102 };
 103
 104 static CPUReadMemoryFunc * const unin_read[] = {
 105     &unin_readl,
 106     &unin_readl,
 107     &unin_readl,
 108 };
 109
 110 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 111 {
 112     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 113     return 0;
 114 }
 115
 116 /* PowerPC Mac99 hardware initialisation */
 117 static void ppc_core99_init (ram_addr_t ram_size,
 118                              const char *boot_device,
 119                              const char *kernel_filename,
 120                              const char *kernel_cmdline,
 121                              const char *initrd_filename,
 122                              const char *cpu_model)
 123 {
 124     CPUState *env = NULL, *envs[MAX_CPUS];
 125     char *filename;
 126     qemu_irq *pic, **openpic_irqs;
 127     int unin_memory;
 128     int linux_boot, i;
 129     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 130     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 131     PCIBus *pci_bus;
 132     MacIONVRAMState *nvr;
 133     int nvram_mem_index;
 134     int vga_bios_size, bios_size;
 135     int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index;
 136     int ppc_boot_device;
 137     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 138     void *fw_cfg;
 139     void *dbdma;
 140     uint8_t *vga_bios_ptr;
 141     int machine_arch;
 142
 143     linux_boot = (kernel_filename != NULL);
 144
 145     /* init CPUs */
 146     if (cpu_model == NULL)
 147 #ifdef TARGET_PPC64
 148         cpu_model = "970fx";
 149 #else
 150         cpu_model = "G4";
 151 #endif
 152     for (i = 0; i < smp_cpus; i++) {
 153         env = cpu_init(cpu_model);
 154         if (!env) {
 155             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 156             exit(1);
 157         }
 158         /* Set time-base frequency to 100 Mhz */
 159         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 160 #if 0
 161         env->osi_call = vga_osi_call;
 162 #endif
 163         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 164         envs[i] = env;
 165     }
 166
 167     /* Make sure all register sets take effect */
 168     cpu_synchronize_state(env);
 169
 170     /* allocate RAM */
 171     ram_offset = qemu_ram_alloc(ram_size);
 172     cpu_register_physical_memory(0, ram_size, ram_offset);
 173
 174     /* allocate and load BIOS */
 175     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 176     if (bios_name == NULL)
 177         bios_name = PROM_FILENAME;
 178     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 179     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 180
 181     /* Load OpenBIOS (ELF) */
 182     if (filename) {
 183         bios_size = load_elf(filename, 0, NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 184
 185         qemu_free(filename);
 186     } else {
 187         bios_size = -1;
 188     }
 189     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 190         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 191         exit(1);
 192     }
 193
 194     /* allocate and load VGA BIOS */
 195     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 196     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 197     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 198     if (filename) {
 199         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 200         qemu_free(filename);
 201     } else {
 202         vga_bios_size = -1;
 203     }
 204     if (vga_bios_size < 0) {
 205         /* if no bios is present, we can still work */
 206         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 207                 VGABIOS_FILENAME);
 208         vga_bios_size = 0;
 209     } else {
 210         /* set a specific header (XXX: find real Apple format for NDRV
 211            drivers) */
 212         vga_bios_ptr[0] = 'N';
 213         vga_bios_ptr[1] = 'D';
 214         vga_bios_ptr[2] = 'R';
 215         vga_bios_ptr[3] = 'V';
 216         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 217         vga_bios_size += 8;
 218
 219         /* Round to page boundary */
 220         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 221             TARGET_PAGE_MASK;
 222     }
 223
 224     if (linux_boot) {
 225         uint64_t lowaddr = 0;
 226         int bswap_needed;
 227
 228 #ifdef BSWAP_NEEDED
 229         bswap_needed = 1;
 230 #else
 231         bswap_needed = 0;
 232 #endif
 233         kernel_base = KERNEL_LOAD_ADDR;
 234
 235         /* Now we can load the kernel. The first step tries to load the kernel
 236            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 237            loaded again, the new PhysAddr being computed from lowaddr. */
 238         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL,
 239                                1, ELF_MACHINE, 0);
 240         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 241             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 242                                    NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 243         }
 244         if (kernel_size < 0)
 245             kernel_size = load_aout(kernel_filename, kernel_base,
 246                                     ram_size - kernel_base, bswap_needed,
 247                                     TARGET_PAGE_SIZE);
 248         if (kernel_size < 0)
 249             kernel_size = load_image_targphys(kernel_filename,
 250                                               kernel_base,
 251                                               ram_size - kernel_base);
 252         if (kernel_size < 0) {
 253             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 254             exit(1);
 255         }
 256         /* load initrd */
 257         if (initrd_filename) {
 258             initrd_base = INITRD_LOAD_ADDR;
 259             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 260                                               ram_size - initrd_base);
 261             if (initrd_size < 0) {
 262                 hw_error("qemu: could not load initial ram disk '%s'\n",
 263                          initrd_filename);
 264                 exit(1);
 265             }
 266         } else {
 267             initrd_base = 0;
 268             initrd_size = 0;
 269         }
 270         ppc_boot_device = 'm';
 271     } else {
 272         kernel_base = 0;
 273         kernel_size = 0;
 274         initrd_base = 0;
 275         initrd_size = 0;
 276         ppc_boot_device = '\0';
 277         /* We consider that NewWorld PowerMac never have any floppy drive
 278          * For now, OHW cannot boot from the network.
 279          */
 280         for (i = 0; boot_device[i] != '\0'; i++) {
 281             if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
 282                 ppc_boot_device = boot_device[i];
 283                 break;
 284             }
 285         }
 286         if (ppc_boot_device == '\0') {
 287             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 288             exit(1);
 289         }
 290     }
 291
 292     isa_mem_base = 0x80000000;
 293
 294     /* Register 8 MB of ISA IO space */
 295     isa_mmio_init(0xf2000000, 0x00800000);
 296
 297     /* UniN init */
 298     unin_memory = cpu_register_io_memory(unin_read, unin_write, NULL);
 299     cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
 300
 301     openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 302     openpic_irqs[0] =
 303         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 304     for (i = 0; i < smp_cpus; i++) {
 305         /* Mac99 IRQ connection between OpenPIC outputs pins
 306          * and PowerPC input pins
 307          */
 308         switch (PPC_INPUT(env)) {
 309         case PPC_FLAGS_INPUT_6xx:
 310             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 311             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 312                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 313             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 314                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 315             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 316                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
 317             /* Not connected ? */
 318             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 319             /* Check this */
 320             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 321                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
 322             break;
 323 #if defined(TARGET_PPC64)
 324         case PPC_FLAGS_INPUT_970:
 325             openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
 326             openpic_irqs[i][OPENPIC_OUTPUT_INT] =
 327                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 328             openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
 329                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
 330             openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
 331                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
 332             /* Not connected ? */
 333             openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
 334             /* Check this */
 335             openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
 336                 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
 337             break;
 338 #endif /* defined(TARGET_PPC64) */
 339         default:
 340             hw_error("Bus model not supported on mac99 machine\n");
 341             exit(1);
 342         }
 343     }
 344     pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
 345     if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
 346         /* 970 gets a U3 bus */
 347         pci_bus = pci_pmac_u3_init(pic);
 348         machine_arch = ARCH_MAC99_U3;
 349     } else {
 350         pci_bus = pci_pmac_init(pic);
 351         machine_arch = ARCH_MAC99;
 352     }
 353     /* init basic PC hardware */
 354     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 355
 356     escc_mem_index = escc_init(0x80013000, pic[0x25], pic[0x24],
 357                                serial_hds[0], serial_hds[1], ESCC_CLOCK, 4);
 358
 359     for(i = 0; i < nb_nics; i++)
 360         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 361
 362     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 363         fprintf(stderr, "qemu: too many IDE bus\n");
 364         exit(1);
 365     }
 366     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 367         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 368     }
 369     dbdma = DBDMA_init(&dbdma_mem_index);
 370     pci_cmd646_ide_init(pci_bus, hd, 0);
 371
 372     /* cuda also initialize ADB */
 373     cuda_init(&cuda_mem_index, pic[0x19]);
 374
 375     adb_kbd_init(&adb_bus);
 376     adb_mouse_init(&adb_bus);
 377
 378
 379     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_UNI_N_KEYL, 0, pic_mem_index,
 380                dbdma_mem_index, cuda_mem_index, NULL, 0, NULL,
 381                escc_mem_index);
 382
 383     if (usb_enabled) {
 384         usb_ohci_init_pci(pci_bus, -1);
 385     }
 386
 387     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 388         graphic_depth = 15;
 389
 390     /* The NewWorld NVRAM is not located in the MacIO device */
 391     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 1);
 392     pmac_format_nvram_partition(nvr, 0x2000);
 393     macio_nvram_map(nvr, 0xFFF04000);
 394     /* No PCI init: the BIOS will do it */
 395
 396     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 397     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 398     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 399     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
 400     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 401     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 402     if (kernel_cmdline) {
 403         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 404         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 405     } else {
 406         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 407     }
 408     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 409     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 410     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 411
 412     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 413     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 414     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 415
 416     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 417 }
 418
 419 static QEMUMachine core99_machine = {
 420     .name = "mac99",
 421     .desc = "Mac99 based PowerMAC",
 422     .init = ppc_core99_init,
 423     .max_cpus = MAX_CPUS,
 424 #ifdef TARGET_PPC64
 425     .is_default = 1,
 426 #endif
 427 };
 428
 429 static void core99_machine_init(void)
 430 {
 431     qemu_register_machine(&core99_machine);
 432 }
 433
 434 machine_init(core99_machine_init);