hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 B&W) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "nvram.h"
  29 #include "pc.h"
  30 #include "sysemu.h"
  31 #include "net.h"
  32 #include "isa.h"
  33 #include "pci.h"
  34 #include "boards.h"
  35
  36 /* temporary frame buffer OSI calls for the video.x driver. The right
  37    solution is to modify the driver to use VGA PCI I/Os */
  38 /* XXX: to be removed. This is no way related to emulation */
  39 static int vga_osi_call (CPUState *env)
  40 {
  41     static int vga_vbl_enabled;
  42     int linesize;
  43
  44     //    printf("osi_call R5=%d\n", env->gpr[5]);
  45
  46     /* same handler as PearPC, coming from the original MOL video
  47        driver. */
  48     switch(env->gpr[5]) {
  49     case 4:
  50         break;
  51     case 28: /* set_vmode */
  52         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  53             env->gpr[3] = 1;
  54         else
  55             env->gpr[3] = 0;
  56         break;
  57     case 29: /* get_vmode_info */
  58         if (env->gpr[6] != 0) {
  59             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  60                 env->gpr[3] = 1;
  61                 break;
  62             }
  63         }
  64         env->gpr[3] = 0;
  65         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  66         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  67         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  68         env->gpr[7] = 85 << 16; /* refresh rate */
  69         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  70         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  71         linesize = (linesize + 3) & ~3;
  72         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  73         break;
  74     case 31: /* set_video power */
  75         env->gpr[3] = 0;
  76         break;
  77     case 39: /* video_ctrl */
  78         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  79             vga_vbl_enabled = env->gpr[6];
  80         env->gpr[3] = 0;
  81         break;
  82     case 47:
  83         break;
  84     case 59: /* set_color */
  85         /* R6 = index, R7 = RGB */
  86         env->gpr[3] = 0;
  87         break;
  88     case 64: /* get color */
  89         /* R6 = index */
  90         env->gpr[3] = 0;
  91         break;
  92     case 116: /* set hwcursor */
  93         /* R6 = x, R7 = y, R8 = visible, R9 = data */
  94         break;
  95     default:
  96         fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
  97         break;
  98     }
  99
 100     return 1; /* osi_call handled */
 101 }
 102
 103 static void ppc_heathrow_init (int ram_size, int vga_ram_size,
 104                                const char *boot_device, DisplayState *ds,
 105                                const char *kernel_filename,
 106                                const char *kernel_cmdline,
 107                                const char *initrd_filename,
 108                                const char *cpu_model)
 109 {
 110     CPUState *env = NULL, *envs[MAX_CPUS];
 111     char buf[1024];
 112     qemu_irq *pic, **heathrow_irqs;
 113     nvram_t nvram;
 114     m48t59_t *m48t59;
 115     int linux_boot, i;
 116     unsigned long bios_offset, vga_bios_offset;
 117     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 118     PCIBus *pci_bus;
 119     MacIONVRAMState *nvr;
 120     int vga_bios_size, bios_size;
 121     qemu_irq *dummy_irq;
 122     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 123     int ide_mem_index[2];
 124     int ppc_boot_device;
 125
 126     linux_boot = (kernel_filename != NULL);
 127
 128     /* init CPUs */
 129     if (cpu_model == NULL)
 130         cpu_model = "default";
 131     for (i = 0; i < smp_cpus; i++) {
 132         env = cpu_init(cpu_model);
 133         if (!env) {
 134             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 135             exit(1);
 136         }
 137         /* Set time-base frequency to 100 Mhz */
 138         cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 139         env->osi_call = vga_osi_call;
 140         qemu_register_reset(&cpu_ppc_reset, env);
 141         register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 142         envs[i] = env;
 143     }
 144     if (env->nip < 0xFFF80000) {
 145         /* Special test for PowerPC 601:
 146          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 147          * But the NVRAM is located at 0xFFF04000...
 148          */
 149         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 150     }
 151
 152     /* allocate RAM */
 153     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 154
 155     /* allocate and load BIOS */
 156     bios_offset = ram_size + vga_ram_size;
 157     if (bios_name == NULL)
 158         bios_name = BIOS_FILENAME;
 159     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 160     bios_size = load_image(buf, phys_ram_base + bios_offset);
 161     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 162         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 163         exit(1);
 164     }
 165     bios_size = (bios_size + 0xfff) & ~0xfff;
 166     if (bios_size > 0x00080000) {
 167         /* As the NVRAM is located at 0xFFF04000, we cannot use 1 MB BIOSes */
 168         cpu_abort(env, "G3BW Mac hardware can not handle 1 MB BIOS\n");
 169     }
 170     cpu_register_physical_memory((uint32_t)(-bios_size),
 171                                  bios_size, bios_offset | IO_MEM_ROM);
 172
 173     /* allocate and load VGA BIOS */
 174     vga_bios_offset = bios_offset + bios_size;
 175     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 176     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 177     if (vga_bios_size < 0) {
 178         /* if no bios is present, we can still work */
 179         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 180         vga_bios_size = 0;
 181     } else {
 182         /* set a specific header (XXX: find real Apple format for NDRV
 183            drivers) */
 184         phys_ram_base[vga_bios_offset] = 'N';
 185         phys_ram_base[vga_bios_offset + 1] = 'D';
 186         phys_ram_base[vga_bios_offset + 2] = 'R';
 187         phys_ram_base[vga_bios_offset + 3] = 'V';
 188         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 189                      vga_bios_size);
 190         vga_bios_size += 8;
 191     }
 192     vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
 193
 194     if (linux_boot) {
 195         kernel_base = KERNEL_LOAD_ADDR;
 196         /* now we can load the kernel */
 197         kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
 198         if (kernel_size < 0) {
 199             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 200                       kernel_filename);
 201             exit(1);
 202         }
 203         /* load initrd */
 204         if (initrd_filename) {
 205             initrd_base = INITRD_LOAD_ADDR;
 206             initrd_size = load_image(initrd_filename,
 207                                      phys_ram_base + initrd_base);
 208             if (initrd_size < 0) {
 209                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 210                           initrd_filename);
 211                 exit(1);
 212             }
 213         } else {
 214             initrd_base = 0;
 215             initrd_size = 0;
 216         }
 217         ppc_boot_device = 'm';
 218     } else {
 219         kernel_base = 0;
 220         kernel_size = 0;
 221         initrd_base = 0;
 222         initrd_size = 0;
 223         ppc_boot_device = '\0';
 224         for (i = 0; boot_device[i] != '\0'; i++) {
 225             /* TOFIX: for now, the second IDE channel is not properly
 226              *        used by OHW. The Mac floppy disk are not emulated.
 227              *        For now, OHW cannot boot from the network.
 228              */
 229 #if 0
 230             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 231                 ppc_boot_device = boot_device[i];
 232                 break;
 233             }
 234 #else
 235             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 236                 ppc_boot_device = boot_device[i];
 237                 break;
 238             }
 239 #endif
 240         }
 241         if (ppc_boot_device == '\0') {
 242             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 243             exit(1);
 244         }
 245     }
 246
 247     isa_mem_base = 0x80000000;
 248
 249     /* Register 2 MB of ISA IO space */
 250     isa_mmio_init(0xfe000000, 0x00200000);
 251
 252     /* XXX: we register only 1 output pin for heathrow PIC */
 253     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 254     heathrow_irqs[0] =
 255         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 256     /* Connect the heathrow PIC outputs to the 6xx bus */
 257     for (i = 0; i < smp_cpus; i++) {
 258         switch (PPC_INPUT(env)) {
 259         case PPC_FLAGS_INPUT_6xx:
 260             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 261             heathrow_irqs[i][0] =
 262                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 263             break;
 264         default:
 265             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 266             exit(1);
 267         }
 268     }
 269
 270     /* init basic PC hardware */
 271     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 272         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 273         exit(1);
 274     }
 275     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 276     pci_bus = pci_grackle_init(0xfec00000, pic);
 277     pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
 278                  ram_size, vga_ram_size,
 279                  vga_bios_offset, vga_bios_size);
 280
 281     /* XXX: suppress that */
 282     dummy_irq = i8259_init(NULL);
 283
 284     /* XXX: use Mac Serial port */
 285     serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
 286
 287     for(i = 0; i < nb_nics; i++) {
 288         if (!nd_table[i].model)
 289             nd_table[i].model = "ne2k_pci";
 290         pci_nic_init(pci_bus, &nd_table[i], -1);
 291     }
 292
 293     /* First IDE channel is a CMD646 on the PCI bus */
 294     pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
 295     /* Second IDE channel is a MAC IDE on the MacIO bus */
 296     ide_mem_index[0] = -1;
 297     ide_mem_index[1] = pmac_ide_init(&bs_table[2], pic[0x0D]);
 298
 299     /* cuda also initialize ADB */
 300     cuda_init(&cuda_mem_index, pic[0x12]);
 301
 302     adb_kbd_init(&adb_bus);
 303     adb_mouse_init(&adb_bus);
 304
 305     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 306     pmac_format_nvram_partition(nvr, 0x2000);
 307
 308     dbdma_init(&dbdma_mem_index);
 309
 310     macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
 311                cuda_mem_index, nvr, 2, ide_mem_index);
 312
 313     if (usb_enabled) {
 314         usb_ohci_init_pci(pci_bus, 3, -1);
 315     }
 316
 317     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 318         graphic_depth = 15;
 319
 320     m48t59 = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 321     nvram.opaque = m48t59;
 322     nvram.read_fn = &m48t59_read;
 323     nvram.write_fn = &m48t59_write;
 324     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 325                          ppc_boot_device, kernel_base, kernel_size,
 326                          kernel_cmdline,
 327                          initrd_base, initrd_size,
 328                          /* XXX: need an option to load a NVRAM image */
 329                          0,
 330                          graphic_width, graphic_height, graphic_depth);
 331     /* No PCI init: the BIOS will do it */
 332
 333     /* Special port to get debug messages from Open-Firmware */
 334     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 335 }
 336
 337 QEMUMachine heathrow_machine = {
 338     "g3bw",
 339     "Heathrow based PowerMAC",
 340     ppc_heathrow_init,
 341 };