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1 /*
2 * QEMU PPC PREP hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "nvram.h"
26 #include "pc.h"
27 #include "fdc.h"
28 #include "net.h"
29 #include "sysemu.h"
30 #include "isa.h"
31 #include "pci.h"
32 #include "ppc.h"
33 #include "boards.h"
34 #include "qemu-log.h"
35 #include "ide.h"
36
37 //#define HARD_DEBUG_PPC_IO
38 //#define DEBUG_PPC_IO
39
40 /* SMP is not enabled, for now */
41 #define MAX_CPUS 1
42
43 #define MAX_IDE_BUS 2
44
45 #define BIOS_SIZE (1024 * 1024)
46 #define BIOS_FILENAME "ppc_rom.bin"
47 #define KERNEL_LOAD_ADDR 0x01000000
48 #define INITRD_LOAD_ADDR 0x01800000
49
50 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
51 #define DEBUG_PPC_IO
52 #endif
53
54 #if defined (HARD_DEBUG_PPC_IO)
55 #define PPC_IO_DPRINTF(fmt, ...) \
56 do { \
57 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
58 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
59 } else { \
60 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
61 } \
62 } while (0)
63 #elif defined (DEBUG_PPC_IO)
64 #define PPC_IO_DPRINTF(fmt, ...) \
65 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
66 #else
67 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
68 #endif
69
70 /* Constants for devices init */
71 static const int ide_iobase[2] = { 0x1f0, 0x170 };
72 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
73 static const int ide_irq[2] = { 13, 13 };
74
75 #define NE2000_NB_MAX 6
76
77 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
78 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
79
80 //static PITState *pit;
81
82 /* ISA IO ports bridge */
83 #define PPC_IO_BASE 0x80000000
84
85 #if 0
86 /* Speaker port 0x61 */
87 static int speaker_data_on;
88 static int dummy_refresh_clock;
89 #endif
90
91 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
92 {
93 #if 0
94 speaker_data_on = (val >> 1) & 1;
95 pit_set_gate(pit, 2, val & 1);
96 #endif
97 }
98
99 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
100 {
101 #if 0
102 int out;
103 out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
104 dummy_refresh_clock ^= 1;
105 return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
106 (dummy_refresh_clock << 4);
107 #endif
108 return 0;
109 }
110
111 /* PCI intack register */
112 /* Read-only register (?) */
113 static void _PPC_intack_write (void *opaque,
114 target_phys_addr_t addr, uint32_t value)
115 {
116 #if 0
117 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
118 value);
119 #endif
120 }
121
122 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
123 {
124 uint32_t retval = 0;
125
126 if ((addr & 0xf) == 0)
127 retval = pic_intack_read(isa_pic);
128 #if 0
129 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
130 retval);
131 #endif
132
133 return retval;
134 }
135
136 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
137 {
138 return _PPC_intack_read(addr);
139 }
140
141 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
142 {
143 #ifdef TARGET_WORDS_BIGENDIAN
144 return bswap16(_PPC_intack_read(addr));
145 #else
146 return _PPC_intack_read(addr);
147 #endif
148 }
149
150 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
151 {
152 #ifdef TARGET_WORDS_BIGENDIAN
153 return bswap32(_PPC_intack_read(addr));
154 #else
155 return _PPC_intack_read(addr);
156 #endif
157 }
158
159 static CPUWriteMemoryFunc * const PPC_intack_write[] = {
160 &_PPC_intack_write,
161 &_PPC_intack_write,
162 &_PPC_intack_write,
163 };
164
165 static CPUReadMemoryFunc * const PPC_intack_read[] = {
166 &PPC_intack_readb,
167 &PPC_intack_readw,
168 &PPC_intack_readl,
169 };
170
171 /* PowerPC control and status registers */
172 #if 0 // Not used
173 static struct {
174 /* IDs */
175 uint32_t veni_devi;
176 uint32_t revi;
177 /* Control and status */
178 uint32_t gcsr;
179 uint32_t xcfr;
180 uint32_t ct32;
181 uint32_t mcsr;
182 /* General purpose registers */
183 uint32_t gprg[6];
184 /* Exceptions */
185 uint32_t feen;
186 uint32_t fest;
187 uint32_t fema;
188 uint32_t fecl;
189 uint32_t eeen;
190 uint32_t eest;
191 uint32_t eecl;
192 uint32_t eeint;
193 uint32_t eemck0;
194 uint32_t eemck1;
195 /* Error diagnostic */
196 } XCSR;
197
198 static void PPC_XCSR_writeb (void *opaque,
199 target_phys_addr_t addr, uint32_t value)
200 {
201 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
202 value);
203 }
204
205 static void PPC_XCSR_writew (void *opaque,
206 target_phys_addr_t addr, uint32_t value)
207 {
208 #ifdef TARGET_WORDS_BIGENDIAN
209 value = bswap16(value);
210 #endif
211 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
212 value);
213 }
214
215 static void PPC_XCSR_writel (void *opaque,
216 target_phys_addr_t addr, uint32_t value)
217 {
218 #ifdef TARGET_WORDS_BIGENDIAN
219 value = bswap32(value);
220 #endif
221 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
222 value);
223 }
224
225 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
226 {
227 uint32_t retval = 0;
228
229 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
230 retval);
231
232 return retval;
233 }
234
235 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
236 {
237 uint32_t retval = 0;
238
239 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
240 retval);
241 #ifdef TARGET_WORDS_BIGENDIAN
242 retval = bswap16(retval);
243 #endif
244
245 return retval;
246 }
247
248 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
249 {
250 uint32_t retval = 0;
251
252 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
253 retval);
254 #ifdef TARGET_WORDS_BIGENDIAN
255 retval = bswap32(retval);
256 #endif
257
258 return retval;
259 }
260
261 static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
262 &PPC_XCSR_writeb,
263 &PPC_XCSR_writew,
264 &PPC_XCSR_writel,
265 };
266
267 static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
268 &PPC_XCSR_readb,
269 &PPC_XCSR_readw,
270 &PPC_XCSR_readl,
271 };
272 #endif
273
274 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
275 typedef struct sysctrl_t {
276 qemu_irq reset_irq;
277 m48t59_t *nvram;
278 uint8_t state;
279 uint8_t syscontrol;
280 uint8_t fake_io[2];
281 int contiguous_map;
282 int endian;
283 } sysctrl_t;
284
285 enum {
286 STATE_HARDFILE = 0x01,
287 };
288
289 static sysctrl_t *sysctrl;
290
291 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
292 {
293 sysctrl_t *sysctrl = opaque;
294
295 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
296 val);
297 sysctrl->fake_io[addr - 0x0398] = val;
298 }
299
300 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
301 {
302 sysctrl_t *sysctrl = opaque;
303
304 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
305 sysctrl->fake_io[addr - 0x0398]);
306 return sysctrl->fake_io[addr - 0x0398];
307 }
308
309 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
310 {
311 sysctrl_t *sysctrl = opaque;
312
313 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
314 addr - PPC_IO_BASE, val);
315 switch (addr) {
316 case 0x0092:
317 /* Special port 92 */
318 /* Check soft reset asked */
319 if (val & 0x01) {
320 qemu_irq_raise(sysctrl->reset_irq);
321 } else {
322 qemu_irq_lower(sysctrl->reset_irq);
323 }
324 /* Check LE mode */
325 if (val & 0x02) {
326 sysctrl->endian = 1;
327 } else {
328 sysctrl->endian = 0;
329 }
330 break;
331 case 0x0800:
332 /* Motorola CPU configuration register : read-only */
333 break;
334 case 0x0802:
335 /* Motorola base module feature register : read-only */
336 break;
337 case 0x0803:
338 /* Motorola base module status register : read-only */
339 break;
340 case 0x0808:
341 /* Hardfile light register */
342 if (val & 1)
343 sysctrl->state |= STATE_HARDFILE;
344 else
345 sysctrl->state &= ~STATE_HARDFILE;
346 break;
347 case 0x0810:
348 /* Password protect 1 register */
349 if (sysctrl->nvram != NULL)
350 m48t59_toggle_lock(sysctrl->nvram, 1);
351 break;
352 case 0x0812:
353 /* Password protect 2 register */
354 if (sysctrl->nvram != NULL)
355 m48t59_toggle_lock(sysctrl->nvram, 2);
356 break;
357 case 0x0814:
358 /* L2 invalidate register */
359 // tlb_flush(first_cpu, 1);
360 break;
361 case 0x081C:
362 /* system control register */
363 sysctrl->syscontrol = val & 0x0F;
364 break;
365 case 0x0850:
366 /* I/O map type register */
367 sysctrl->contiguous_map = val & 0x01;
368 break;
369 default:
370 printf("ERROR: unaffected IO port write: %04" PRIx32
371 " => %02" PRIx32"\n", addr, val);
372 break;
373 }
374 }
375
376 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
377 {
378 sysctrl_t *sysctrl = opaque;
379 uint32_t retval = 0xFF;
380
381 switch (addr) {
382 case 0x0092:
383 /* Special port 92 */
384 retval = 0x00;
385 break;
386 case 0x0800:
387 /* Motorola CPU configuration register */
388 retval = 0xEF; /* MPC750 */
389 break;
390 case 0x0802:
391 /* Motorola Base module feature register */
392 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
393 break;
394 case 0x0803:
395 /* Motorola base module status register */
396 retval = 0xE0; /* Standard MPC750 */
397 break;
398 case 0x080C:
399 /* Equipment present register:
400 * no L2 cache
401 * no upgrade processor
402 * no cards in PCI slots
403 * SCSI fuse is bad
404 */
405 retval = 0x3C;
406 break;
407 case 0x0810:
408 /* Motorola base module extended feature register */
409 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
410 break;
411 case 0x0814:
412 /* L2 invalidate: don't care */
413 break;
414 case 0x0818:
415 /* Keylock */
416 retval = 0x00;
417 break;
418 case 0x081C:
419 /* system control register
420 * 7 - 6 / 1 - 0: L2 cache enable
421 */
422 retval = sysctrl->syscontrol;
423 break;
424 case 0x0823:
425 /* */
426 retval = 0x03; /* no L2 cache */
427 break;
428 case 0x0850:
429 /* I/O map type register */
430 retval = sysctrl->contiguous_map;
431 break;
432 default:
433 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
434 break;
435 }
436 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
437 addr - PPC_IO_BASE, retval);
438
439 return retval;
440 }
441
442 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
443 target_phys_addr_t addr)
444 {
445 if (sysctrl->contiguous_map == 0) {
446 /* 64 KB contiguous space for IOs */
447 addr &= 0xFFFF;
448 } else {
449 /* 8 MB non-contiguous space for IOs */
450 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
451 }
452
453 return addr;
454 }
455
456 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
457 uint32_t value)
458 {
459 sysctrl_t *sysctrl = opaque;
460
461 addr = prep_IO_address(sysctrl, addr);
462 cpu_outb(NULL, addr, value);
463 }
464
465 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
466 {
467 sysctrl_t *sysctrl = opaque;
468 uint32_t ret;
469
470 addr = prep_IO_address(sysctrl, addr);
471 ret = cpu_inb(NULL, addr);
472
473 return ret;
474 }
475
476 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
477 uint32_t value)
478 {
479 sysctrl_t *sysctrl = opaque;
480
481 addr = prep_IO_address(sysctrl, addr);
482 #ifdef TARGET_WORDS_BIGENDIAN
483 value = bswap16(value);
484 #endif
485 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
486 cpu_outw(NULL, addr, value);
487 }
488
489 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
490 {
491 sysctrl_t *sysctrl = opaque;
492 uint32_t ret;
493
494 addr = prep_IO_address(sysctrl, addr);
495 ret = cpu_inw(NULL, addr);
496 #ifdef TARGET_WORDS_BIGENDIAN
497 ret = bswap16(ret);
498 #endif
499 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
500
501 return ret;
502 }
503
504 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
505 uint32_t value)
506 {
507 sysctrl_t *sysctrl = opaque;
508
509 addr = prep_IO_address(sysctrl, addr);
510 #ifdef TARGET_WORDS_BIGENDIAN
511 value = bswap32(value);
512 #endif
513 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
514 cpu_outl(NULL, addr, value);
515 }
516
517 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
518 {
519 sysctrl_t *sysctrl = opaque;
520 uint32_t ret;
521
522 addr = prep_IO_address(sysctrl, addr);
523 ret = cpu_inl(NULL, addr);
524 #ifdef TARGET_WORDS_BIGENDIAN
525 ret = bswap32(ret);
526 #endif
527 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
528
529 return ret;
530 }
531
532 static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
533 &PPC_prep_io_writeb,
534 &PPC_prep_io_writew,
535 &PPC_prep_io_writel,
536 };
537
538 static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
539 &PPC_prep_io_readb,
540 &PPC_prep_io_readw,
541 &PPC_prep_io_readl,
542 };
543
544 #define NVRAM_SIZE 0x2000
545
546 /* PowerPC PREP hardware initialisation */
547 static void ppc_prep_init (ram_addr_t ram_size,
548 const char *boot_device,
549 const char *kernel_filename,
550 const char *kernel_cmdline,
551 const char *initrd_filename,
552 const char *cpu_model)
553 {
554 CPUState *env = NULL, *envs[MAX_CPUS];
555 char *filename;
556 nvram_t nvram;
557 m48t59_t *m48t59;
558 int PPC_io_memory;
559 int linux_boot, i, nb_nics1, bios_size;
560 ram_addr_t ram_offset, bios_offset;
561 uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
562 PCIBus *pci_bus;
563 qemu_irq *i8259;
564 int ppc_boot_device;
565 DriveInfo *dinfo;
566 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
567 BlockDriverState *fd[MAX_FD];
568
569 sysctrl = qemu_mallocz(sizeof(sysctrl_t));
570
571 linux_boot = (kernel_filename != NULL);
572
573 /* init CPUs */
574 if (cpu_model == NULL)
575 cpu_model = "default";
576 for (i = 0; i < smp_cpus; i++) {
577 env = cpu_init(cpu_model);
578 if (!env) {
579 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
580 exit(1);
581 }
582 if (env->flags & POWERPC_FLAG_RTC_CLK) {
583 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
584 cpu_ppc_tb_init(env, 7812500UL);
585 } else {
586 /* Set time-base frequency to 100 Mhz */
587 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
588 }
589 qemu_register_reset(&cpu_ppc_reset, env);
590 envs[i] = env;
591 }
592
593 /* allocate RAM */
594 ram_offset = qemu_ram_alloc(ram_size);
595 cpu_register_physical_memory(0, ram_size, ram_offset);
596
597 /* allocate and load BIOS */
598 bios_offset = qemu_ram_alloc(BIOS_SIZE);
599 if (bios_name == NULL)
600 bios_name = BIOS_FILENAME;
601 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
602 if (filename) {
603 bios_size = get_image_size(filename);
604 } else {
605 bios_size = -1;
606 }
607 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
608 target_phys_addr_t bios_addr;
609 bios_size = (bios_size + 0xfff) & ~0xfff;
610 bios_addr = (uint32_t)(-bios_size);
611 cpu_register_physical_memory(bios_addr, bios_size,
612 bios_offset | IO_MEM_ROM);
613 bios_size = load_image_targphys(filename, bios_addr, bios_size);
614 }
615 if (bios_size < 0 || bios_size > BIOS_SIZE) {
616 hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
617 }
618 if (filename) {
619 qemu_free(filename);
620 }
621 if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
622 hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
623 }
624
625 if (linux_boot) {
626 kernel_base = KERNEL_LOAD_ADDR;
627 /* now we can load the kernel */
628 kernel_size = load_image_targphys(kernel_filename, kernel_base,
629 ram_size - kernel_base);
630 if (kernel_size < 0) {
631 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
632 exit(1);
633 }
634 /* load initrd */
635 if (initrd_filename) {
636 initrd_base = INITRD_LOAD_ADDR;
637 initrd_size = load_image_targphys(initrd_filename, initrd_base,
638 ram_size - initrd_base);
639 if (initrd_size < 0) {
640 hw_error("qemu: could not load initial ram disk '%s'\n",
641 initrd_filename);
642 }
643 } else {
644 initrd_base = 0;
645 initrd_size = 0;
646 }
647 ppc_boot_device = 'm';
648 } else {
649 kernel_base = 0;
650 kernel_size = 0;
651 initrd_base = 0;
652 initrd_size = 0;
653 ppc_boot_device = '\0';
654 /* For now, OHW cannot boot from the network. */
655 for (i = 0; boot_device[i] != '\0'; i++) {
656 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
657 ppc_boot_device = boot_device[i];
658 break;
659 }
660 }
661 if (ppc_boot_device == '\0') {
662 fprintf(stderr, "No valid boot device for Mac99 machine\n");
663 exit(1);
664 }
665 }
666
667 isa_mem_base = 0xc0000000;
668 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
669 hw_error("Only 6xx bus is supported on PREP machine\n");
670 }
671 i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
672 pci_bus = pci_prep_init(i8259);
673 // pci_bus = i440fx_init();
674 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
675 PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
676 PPC_prep_io_write, sysctrl);
677 cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
678
679 /* init basic PC hardware */
680 pci_vga_init(pci_bus, 0, 0);
681 // openpic = openpic_init(0x00000000, 0xF0000000, 1);
682 // pit = pit_init(0x40, i8259[0]);
683 rtc_init(0x70, i8259[8], 2000);
684
685 serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
686 nb_nics1 = nb_nics;
687 if (nb_nics1 > NE2000_NB_MAX)
688 nb_nics1 = NE2000_NB_MAX;
689 for(i = 0; i < nb_nics1; i++) {
690 if (nd_table[i].model == NULL) {
691 nd_table[i].model = "ne2k_isa";
692 }
693 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
694 isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
695 } else {
696 pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
697 }
698 }
699
700 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
701 fprintf(stderr, "qemu: too many IDE bus\n");
702 exit(1);
703 }
704
705 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
706 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
707 }
708
709 for(i = 0; i < MAX_IDE_BUS; i++) {
710 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
711 hd[2 * i],
712 hd[2 * i + 1]);
713 }
714 i8042_init(i8259[1], i8259[12], 0x60);
715 DMA_init(1);
716 // SB16_init();
717
718 for(i = 0; i < MAX_FD; i++) {
719 dinfo = drive_get(IF_FLOPPY, 0, i);
720 fd[i] = dinfo ? dinfo->bdrv : NULL;
721 }
722 fdctrl_init_isa(6, 2, 0x3f0, fd);
723
724 /* Register speaker port */
725 register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
726 register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
727 /* Register fake IO ports for PREP */
728 sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
729 register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
730 register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
731 /* System control ports */
732 register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
733 register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
734 register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
735 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
736 /* PCI intack location */
737 PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
738 PPC_intack_write, NULL);
739 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
740 /* PowerPC control and status register group */
741 #if 0
742 PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
743 NULL);
744 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
745 #endif
746
747 if (usb_enabled) {
748 usb_ohci_init_pci(pci_bus, -1);
749 }
750
751 m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
752 if (m48t59 == NULL)
753 return;
754 sysctrl->nvram = m48t59;
755
756 /* Initialise NVRAM */
757 nvram.opaque = m48t59;
758 nvram.read_fn = &m48t59_read;
759 nvram.write_fn = &m48t59_write;
760 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
761 kernel_base, kernel_size,
762 kernel_cmdline,
763 initrd_base, initrd_size,
764 /* XXX: need an option to load a NVRAM image */
765 0,
766 graphic_width, graphic_height, graphic_depth);
767
768 /* Special port to get debug messages from Open-Firmware */
769 register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
770 }
771
772 static QEMUMachine prep_machine = {
773 .name = "prep",
774 .desc = "PowerPC PREP platform",
775 .init = ppc_prep_init,
776 .max_cpus = MAX_CPUS,
777 };
778
779 static void prep_machine_init(void)
780 {
781 qemu_register_machine(&prep_machine);
782 }
783
784 machine_init(prep_machine_init);