hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "ppc.h"
  33 #include "boards.h"
  34 #include "qemu-log.h"
  35
  36 //#define HARD_DEBUG_PPC_IO
  37 //#define DEBUG_PPC_IO
  38
  39 /* SMP is not enabled, for now */
  40 #define MAX_CPUS 1
  41
  42 #define MAX_IDE_BUS 2
  43
  44 #define BIOS_SIZE (1024 * 1024)
  45 #define BIOS_FILENAME "ppc_rom.bin"
  46 #define KERNEL_LOAD_ADDR 0x01000000
  47 #define INITRD_LOAD_ADDR 0x01800000
  48
  49 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  50 #define DEBUG_PPC_IO
  51 #endif
  52
  53 #if defined (HARD_DEBUG_PPC_IO)
  54 #define PPC_IO_DPRINTF(fmt, ...)                         \
  55 do {                                                     \
  56     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  57         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  58     } else {                                             \
  59         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  60     }                                                    \
  61 } while (0)
  62 #elif defined (DEBUG_PPC_IO)
  63 #define PPC_IO_DPRINTF(fmt, ...) \
  64 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  65 #else
  66 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  67 #endif
  68
  69 /* Constants for devices init */
  70 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  71 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  72 static const int ide_irq[2] = { 13, 13 };
  73
  74 #define NE2000_NB_MAX 6
  75
  76 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  77 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  78
  79 //static PITState *pit;
  80
  81 /* ISA IO ports bridge */
  82 #define PPC_IO_BASE 0x80000000
  83
  84 #if 0
  85 /* Speaker port 0x61 */
  86 static int speaker_data_on;
  87 static int dummy_refresh_clock;
  88 #endif
  89
  90 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  91 {
  92 #if 0
  93     speaker_data_on = (val >> 1) & 1;
  94     pit_set_gate(pit, 2, val & 1);
  95 #endif
  96 }
  97
  98 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
  99 {
 100 #if 0
 101     int out;
 102     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 103     dummy_refresh_clock ^= 1;
 104     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 105         (dummy_refresh_clock << 4);
 106 #endif
 107     return 0;
 108 }
 109
 110 /* PCI intack register */
 111 /* Read-only register (?) */
 112 static void _PPC_intack_write (void *opaque,
 113                                target_phys_addr_t addr, uint32_t value)
 114 {
 115 //    printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 116 }
 117
 118 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
 119 {
 120     uint32_t retval = 0;
 121
 122     if ((addr & 0xf) == 0)
 123         retval = pic_intack_read(isa_pic);
 124 //   printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 125
 126     return retval;
 127 }
 128
 129 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 130 {
 131     return _PPC_intack_read(addr);
 132 }
 133
 134 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 135 {
 136 #ifdef TARGET_WORDS_BIGENDIAN
 137     return bswap16(_PPC_intack_read(addr));
 138 #else
 139     return _PPC_intack_read(addr);
 140 #endif
 141 }
 142
 143 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 144 {
 145 #ifdef TARGET_WORDS_BIGENDIAN
 146     return bswap32(_PPC_intack_read(addr));
 147 #else
 148     return _PPC_intack_read(addr);
 149 #endif
 150 }
 151
 152 static CPUWriteMemoryFunc *PPC_intack_write[] = {
 153     &_PPC_intack_write,
 154     &_PPC_intack_write,
 155     &_PPC_intack_write,
 156 };
 157
 158 static CPUReadMemoryFunc *PPC_intack_read[] = {
 159     &PPC_intack_readb,
 160     &PPC_intack_readw,
 161     &PPC_intack_readl,
 162 };
 163
 164 /* PowerPC control and status registers */
 165 #if 0 // Not used
 166 static struct {
 167     /* IDs */
 168     uint32_t veni_devi;
 169     uint32_t revi;
 170     /* Control and status */
 171     uint32_t gcsr;
 172     uint32_t xcfr;
 173     uint32_t ct32;
 174     uint32_t mcsr;
 175     /* General purpose registers */
 176     uint32_t gprg[6];
 177     /* Exceptions */
 178     uint32_t feen;
 179     uint32_t fest;
 180     uint32_t fema;
 181     uint32_t fecl;
 182     uint32_t eeen;
 183     uint32_t eest;
 184     uint32_t eecl;
 185     uint32_t eeint;
 186     uint32_t eemck0;
 187     uint32_t eemck1;
 188     /* Error diagnostic */
 189 } XCSR;
 190
 191 static void PPC_XCSR_writeb (void *opaque,
 192                              target_phys_addr_t addr, uint32_t value)
 193 {
 194     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 195 }
 196
 197 static void PPC_XCSR_writew (void *opaque,
 198                              target_phys_addr_t addr, uint32_t value)
 199 {
 200 #ifdef TARGET_WORDS_BIGENDIAN
 201     value = bswap16(value);
 202 #endif
 203     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 204 }
 205
 206 static void PPC_XCSR_writel (void *opaque,
 207                              target_phys_addr_t addr, uint32_t value)
 208 {
 209 #ifdef TARGET_WORDS_BIGENDIAN
 210     value = bswap32(value);
 211 #endif
 212     printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
 213 }
 214
 215 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 216 {
 217     uint32_t retval = 0;
 218
 219     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 220
 221     return retval;
 222 }
 223
 224 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 225 {
 226     uint32_t retval = 0;
 227
 228     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 229 #ifdef TARGET_WORDS_BIGENDIAN
 230     retval = bswap16(retval);
 231 #endif
 232
 233     return retval;
 234 }
 235
 236 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 237 {
 238     uint32_t retval = 0;
 239
 240     printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
 241 #ifdef TARGET_WORDS_BIGENDIAN
 242     retval = bswap32(retval);
 243 #endif
 244
 245     return retval;
 246 }
 247
 248 static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
 249     &PPC_XCSR_writeb,
 250     &PPC_XCSR_writew,
 251     &PPC_XCSR_writel,
 252 };
 253
 254 static CPUReadMemoryFunc *PPC_XCSR_read[] = {
 255     &PPC_XCSR_readb,
 256     &PPC_XCSR_readw,
 257     &PPC_XCSR_readl,
 258 };
 259 #endif
 260
 261 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 262 typedef struct sysctrl_t {
 263     qemu_irq reset_irq;
 264     m48t59_t *nvram;
 265     uint8_t state;
 266     uint8_t syscontrol;
 267     uint8_t fake_io[2];
 268     int contiguous_map;
 269     int endian;
 270 } sysctrl_t;
 271
 272 enum {
 273     STATE_HARDFILE = 0x01,
 274 };
 275
 276 static sysctrl_t *sysctrl;
 277
 278 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 279 {
 280     sysctrl_t *sysctrl = opaque;
 281
 282     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 283                    val);
 284     sysctrl->fake_io[addr - 0x0398] = val;
 285 }
 286
 287 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 288 {
 289     sysctrl_t *sysctrl = opaque;
 290
 291     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 292                    sysctrl->fake_io[addr - 0x0398]);
 293     return sysctrl->fake_io[addr - 0x0398];
 294 }
 295
 296 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 297 {
 298     sysctrl_t *sysctrl = opaque;
 299
 300     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 301                    addr - PPC_IO_BASE, val);
 302     switch (addr) {
 303     case 0x0092:
 304         /* Special port 92 */
 305         /* Check soft reset asked */
 306         if (val & 0x01) {
 307             qemu_irq_raise(sysctrl->reset_irq);
 308         } else {
 309             qemu_irq_lower(sysctrl->reset_irq);
 310         }
 311         /* Check LE mode */
 312         if (val & 0x02) {
 313             sysctrl->endian = 1;
 314         } else {
 315             sysctrl->endian = 0;
 316         }
 317         break;
 318     case 0x0800:
 319         /* Motorola CPU configuration register : read-only */
 320         break;
 321     case 0x0802:
 322         /* Motorola base module feature register : read-only */
 323         break;
 324     case 0x0803:
 325         /* Motorola base module status register : read-only */
 326         break;
 327     case 0x0808:
 328         /* Hardfile light register */
 329         if (val & 1)
 330             sysctrl->state |= STATE_HARDFILE;
 331         else
 332             sysctrl->state &= ~STATE_HARDFILE;
 333         break;
 334     case 0x0810:
 335         /* Password protect 1 register */
 336         if (sysctrl->nvram != NULL)
 337             m48t59_toggle_lock(sysctrl->nvram, 1);
 338         break;
 339     case 0x0812:
 340         /* Password protect 2 register */
 341         if (sysctrl->nvram != NULL)
 342             m48t59_toggle_lock(sysctrl->nvram, 2);
 343         break;
 344     case 0x0814:
 345         /* L2 invalidate register */
 346         //        tlb_flush(first_cpu, 1);
 347         break;
 348     case 0x081C:
 349         /* system control register */
 350         sysctrl->syscontrol = val & 0x0F;
 351         break;
 352     case 0x0850:
 353         /* I/O map type register */
 354         sysctrl->contiguous_map = val & 0x01;
 355         break;
 356     default:
 357         printf("ERROR: unaffected IO port write: %04" PRIx32
 358                " => %02" PRIx32"\n", addr, val);
 359         break;
 360     }
 361 }
 362
 363 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 364 {
 365     sysctrl_t *sysctrl = opaque;
 366     uint32_t retval = 0xFF;
 367
 368     switch (addr) {
 369     case 0x0092:
 370         /* Special port 92 */
 371         retval = 0x00;
 372         break;
 373     case 0x0800:
 374         /* Motorola CPU configuration register */
 375         retval = 0xEF; /* MPC750 */
 376         break;
 377     case 0x0802:
 378         /* Motorola Base module feature register */
 379         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 380         break;
 381     case 0x0803:
 382         /* Motorola base module status register */
 383         retval = 0xE0; /* Standard MPC750 */
 384         break;
 385     case 0x080C:
 386         /* Equipment present register:
 387          *  no L2 cache
 388          *  no upgrade processor
 389          *  no cards in PCI slots
 390          *  SCSI fuse is bad
 391          */
 392         retval = 0x3C;
 393         break;
 394     case 0x0810:
 395         /* Motorola base module extended feature register */
 396         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 397         break;
 398     case 0x0814:
 399         /* L2 invalidate: don't care */
 400         break;
 401     case 0x0818:
 402         /* Keylock */
 403         retval = 0x00;
 404         break;
 405     case 0x081C:
 406         /* system control register
 407          * 7 - 6 / 1 - 0: L2 cache enable
 408          */
 409         retval = sysctrl->syscontrol;
 410         break;
 411     case 0x0823:
 412         /* */
 413         retval = 0x03; /* no L2 cache */
 414         break;
 415     case 0x0850:
 416         /* I/O map type register */
 417         retval = sysctrl->contiguous_map;
 418         break;
 419     default:
 420         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 421         break;
 422     }
 423     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 424                    addr - PPC_IO_BASE, retval);
 425
 426     return retval;
 427 }
 428
 429 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 430                                                  target_phys_addr_t addr)
 431 {
 432     if (sysctrl->contiguous_map == 0) {
 433         /* 64 KB contiguous space for IOs */
 434         addr &= 0xFFFF;
 435     } else {
 436         /* 8 MB non-contiguous space for IOs */
 437         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 438     }
 439
 440     return addr;
 441 }
 442
 443 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 444                                 uint32_t value)
 445 {
 446     sysctrl_t *sysctrl = opaque;
 447
 448     addr = prep_IO_address(sysctrl, addr);
 449     cpu_outb(NULL, addr, value);
 450 }
 451
 452 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 453 {
 454     sysctrl_t *sysctrl = opaque;
 455     uint32_t ret;
 456
 457     addr = prep_IO_address(sysctrl, addr);
 458     ret = cpu_inb(NULL, addr);
 459
 460     return ret;
 461 }
 462
 463 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 464                                 uint32_t value)
 465 {
 466     sysctrl_t *sysctrl = opaque;
 467
 468     addr = prep_IO_address(sysctrl, addr);
 469 #ifdef TARGET_WORDS_BIGENDIAN
 470     value = bswap16(value);
 471 #endif
 472     PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
 473     cpu_outw(NULL, addr, value);
 474 }
 475
 476 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 477 {
 478     sysctrl_t *sysctrl = opaque;
 479     uint32_t ret;
 480
 481     addr = prep_IO_address(sysctrl, addr);
 482     ret = cpu_inw(NULL, addr);
 483 #ifdef TARGET_WORDS_BIGENDIAN
 484     ret = bswap16(ret);
 485 #endif
 486     PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 487
 488     return ret;
 489 }
 490
 491 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 492                                 uint32_t value)
 493 {
 494     sysctrl_t *sysctrl = opaque;
 495
 496     addr = prep_IO_address(sysctrl, addr);
 497 #ifdef TARGET_WORDS_BIGENDIAN
 498     value = bswap32(value);
 499 #endif
 500     PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value);
 501     cpu_outl(NULL, addr, value);
 502 }
 503
 504 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 505 {
 506     sysctrl_t *sysctrl = opaque;
 507     uint32_t ret;
 508
 509     addr = prep_IO_address(sysctrl, addr);
 510     ret = cpu_inl(NULL, addr);
 511 #ifdef TARGET_WORDS_BIGENDIAN
 512     ret = bswap32(ret);
 513 #endif
 514     PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret);
 515
 516     return ret;
 517 }
 518
 519 static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
 520     &PPC_prep_io_writeb,
 521     &PPC_prep_io_writew,
 522     &PPC_prep_io_writel,
 523 };
 524
 525 static CPUReadMemoryFunc *PPC_prep_io_read[] = {
 526     &PPC_prep_io_readb,
 527     &PPC_prep_io_readw,
 528     &PPC_prep_io_readl,
 529 };
 530
 531 #define NVRAM_SIZE        0x2000
 532
 533 /* PowerPC PREP hardware initialisation */
 534 static void ppc_prep_init (ram_addr_t ram_size,
 535                            const char *boot_device,
 536                            const char *kernel_filename,
 537                            const char *kernel_cmdline,
 538                            const char *initrd_filename,
 539                            const char *cpu_model)
 540 {
 541     CPUState *env = NULL, *envs[MAX_CPUS];
 542     char *filename;
 543     nvram_t nvram;
 544     m48t59_t *m48t59;
 545     int PPC_io_memory;
 546     int linux_boot, i, nb_nics1, bios_size;
 547     ram_addr_t ram_offset, bios_offset;
 548     uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
 549     PCIBus *pci_bus;
 550     qemu_irq *i8259;
 551     int ppc_boot_device;
 552     DriveInfo *dinfo;
 553     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 554     BlockDriverState *fd[MAX_FD];
 555
 556     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 557
 558     linux_boot = (kernel_filename != NULL);
 559
 560     /* init CPUs */
 561     if (cpu_model == NULL)
 562         cpu_model = "default";
 563     for (i = 0; i < smp_cpus; i++) {
 564         env = cpu_init(cpu_model);
 565         if (!env) {
 566             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 567             exit(1);
 568         }
 569         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 570             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 571             cpu_ppc_tb_init(env, 7812500UL);
 572         } else {
 573             /* Set time-base frequency to 100 Mhz */
 574             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 575         }
 576         qemu_register_reset(&cpu_ppc_reset, env);
 577         envs[i] = env;
 578     }
 579
 580     /* allocate RAM */
 581     ram_offset = qemu_ram_alloc(ram_size);
 582     cpu_register_physical_memory(0, ram_size, ram_offset);
 583
 584     /* allocate and load BIOS */
 585     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 586     if (bios_name == NULL)
 587         bios_name = BIOS_FILENAME;
 588     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 589     if (filename) {
 590         bios_size = get_image_size(filename);
 591     } else {
 592         bios_size = -1;
 593     }
 594     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 595         target_phys_addr_t bios_addr;
 596         bios_size = (bios_size + 0xfff) & ~0xfff;
 597         bios_addr = (uint32_t)(-bios_size);
 598         cpu_register_physical_memory(bios_addr, bios_size,
 599                                      bios_offset | IO_MEM_ROM);
 600         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 601     }
 602     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 603         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 604     }
 605     if (filename) {
 606         qemu_free(filename);
 607     }
 608     if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
 609         hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
 610     }
 611
 612     if (linux_boot) {
 613         kernel_base = KERNEL_LOAD_ADDR;
 614         /* now we can load the kernel */
 615         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 616                                           ram_size - kernel_base);
 617         if (kernel_size < 0) {
 618             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 619             exit(1);
 620         }
 621         /* load initrd */
 622         if (initrd_filename) {
 623             initrd_base = INITRD_LOAD_ADDR;
 624             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 625                                               ram_size - initrd_base);
 626             if (initrd_size < 0) {
 627                 hw_error("qemu: could not load initial ram disk '%s'\n",
 628                           initrd_filename);
 629             }
 630         } else {
 631             initrd_base = 0;
 632             initrd_size = 0;
 633         }
 634         ppc_boot_device = 'm';
 635     } else {
 636         kernel_base = 0;
 637         kernel_size = 0;
 638         initrd_base = 0;
 639         initrd_size = 0;
 640         ppc_boot_device = '\0';
 641         /* For now, OHW cannot boot from the network. */
 642         for (i = 0; boot_device[i] != '\0'; i++) {
 643             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 644                 ppc_boot_device = boot_device[i];
 645                 break;
 646             }
 647         }
 648         if (ppc_boot_device == '\0') {
 649             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 650             exit(1);
 651         }
 652     }
 653
 654     isa_mem_base = 0xc0000000;
 655     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 656         hw_error("Only 6xx bus is supported on PREP machine\n");
 657     }
 658     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 659     pci_bus = pci_prep_init(i8259);
 660     //    pci_bus = i440fx_init();
 661     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 662     PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
 663                                            PPC_prep_io_write, sysctrl);
 664     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 665
 666     /* init basic PC hardware */
 667     pci_vga_init(pci_bus, 0, 0);
 668     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 669     //    pit = pit_init(0x40, i8259[0]);
 670     rtc_init(0x70, i8259[8], 2000);
 671
 672     serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
 673     nb_nics1 = nb_nics;
 674     if (nb_nics1 > NE2000_NB_MAX)
 675         nb_nics1 = NE2000_NB_MAX;
 676     for(i = 0; i < nb_nics1; i++) {
 677         if (nd_table[i].model == NULL) {
 678             nd_table[i].model = "ne2k_isa";
 679         }
 680         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 681             isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
 682         } else {
 683             pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
 684         }
 685     }
 686
 687     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 688         fprintf(stderr, "qemu: too many IDE bus\n");
 689         exit(1);
 690     }
 691
 692     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 693         dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 694         hd[i] = dinfo ? dinfo->bdrv : NULL;
 695     }
 696
 697     for(i = 0; i < MAX_IDE_BUS; i++) {
 698         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 699                      hd[2 * i],
 700                      hd[2 * i + 1]);
 701     }
 702     i8042_init(i8259[1], i8259[12], 0x60);
 703     DMA_init(1);
 704     //    SB16_init();
 705
 706     for(i = 0; i < MAX_FD; i++) {
 707         dinfo = drive_get(IF_FLOPPY, 0, i);
 708         fd[i] = dinfo ? dinfo->bdrv : NULL;
 709     }
 710     fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 711
 712     /* Register speaker port */
 713     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 714     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 715     /* Register fake IO ports for PREP */
 716     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 717     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 718     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 719     /* System control ports */
 720     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 721     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 722     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 723     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 724     /* PCI intack location */
 725     PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
 726                                            PPC_intack_write, NULL);
 727     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 728     /* PowerPC control and status register group */
 729 #if 0
 730     PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
 731                                            NULL);
 732     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 733 #endif
 734
 735     if (usb_enabled) {
 736         usb_ohci_init_pci(pci_bus, 3, -1);
 737     }
 738
 739     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 740     if (m48t59 == NULL)
 741         return;
 742     sysctrl->nvram = m48t59;
 743
 744     /* Initialise NVRAM */
 745     nvram.opaque = m48t59;
 746     nvram.read_fn = &m48t59_read;
 747     nvram.write_fn = &m48t59_write;
 748     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 749                          kernel_base, kernel_size,
 750                          kernel_cmdline,
 751                          initrd_base, initrd_size,
 752                          /* XXX: need an option to load a NVRAM image */
 753                          0,
 754                          graphic_width, graphic_height, graphic_depth);
 755
 756     /* Special port to get debug messages from Open-Firmware */
 757     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 758 }
 759
 760 static QEMUMachine prep_machine = {
 761     .name = "prep",
 762     .desc = "PowerPC PREP platform",
 763     .init = ppc_prep_init,
 764     .max_cpus = MAX_CPUS,
 765 };
 766
 767 static void prep_machine_init(void)
 768 {
 769     qemu_register_machine(&prep_machine);
 770 }
 771
 772 machine_init(prep_machine_init);